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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 973e02db35c2c4036693e32ed6f250eefd8c322c / . / drivers / gpu / drm / msm / Makefile
blob: f74d449476f40a4dedfdd41a4fb9dcc9072dd200 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1# SPDX-License-Identifier: GPL-2.0
Masahiro Yamada78f27b12017-04-24 13:50:28 +0900[diff] [blame]2ccflags-y := -Idrivers/gpu/drm/msm
Hai Li5c829022015-08-13 17:45:52 -0400[diff] [blame]3ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]4
5msm-y := \
Rob Clarkbfd28b12014-09-05 13:06:37 -0400[diff] [blame]6 adreno/adreno_device.o \
Rob Clark7198e6b2013-07-19 12:59:32 -0400[diff] [blame]7 adreno/adreno_gpu.o \
8 adreno/a3xx_gpu.o \
Aravind Ganesan23bd62f2014-09-08 13:40:16 -0600[diff] [blame]9 adreno/a4xx_gpu.o \
Jordan Crouseb5f103a2016-11-28 12:28:33 -0700[diff] [blame]10 adreno/a5xx_gpu.o \
Jordan Crouse2401a002016-11-28 12:28:34 -0700[diff] [blame]11 adreno/a5xx_power.o \
Jordan Crouseb1fc2832017-10-20 11:07:01 -0600[diff] [blame]12 adreno/a5xx_preempt.o \
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]13 hdmi/hdmi.o \
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500[diff] [blame]14 hdmi/hdmi_audio.o \
Rob Clarka3376e32013-08-30 13:02:15 -0400[diff] [blame]15 hdmi/hdmi_bridge.o \
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]16 hdmi/hdmi_connector.o \
17 hdmi/hdmi_i2c.o \
Archit Taneja15b4a452016-02-25 11:22:38 +0530[diff] [blame]18 hdmi/hdmi_phy.o \
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]19 hdmi/hdmi_phy_8960.o \
20 hdmi/hdmi_phy_8x60.o \
Rob Clarkdada25b2013-12-01 12:12:54 -0500[diff] [blame]21 hdmi/hdmi_phy_8x74.o \
Hai Liab5b0102015-01-07 18:47:44 -0500[diff] [blame]22 edp/edp.o \
23 edp/edp_aux.o \
24 edp/edp_bridge.o \
25 edp/edp_connector.o \
26 edp/edp_ctrl.o \
27 edp/edp_phy.o \
Rob Clark10a02eb2013-11-30 14:58:23 -0500[diff] [blame]28 mdp/mdp_format.o \
Rob Clark9e0efa62013-11-30 17:24:22 -0500[diff] [blame]29 mdp/mdp_kms.o \
Rob Clark2e54a922013-11-30 12:37:42 -0500[diff] [blame]30 mdp/mdp4/mdp4_crtc.o \
31 mdp/mdp4/mdp4_dtv_encoder.o \
Rob Clark3e875992014-08-01 13:08:11 -0400[diff] [blame]32 mdp/mdp4/mdp4_lcdc_encoder.o \
33 mdp/mdp4/mdp4_lvds_connector.o \
Rob Clark2e54a922013-11-30 12:37:42 -0500[diff] [blame]34 mdp/mdp4/mdp4_irq.o \
35 mdp/mdp4/mdp4_kms.o \
36 mdp/mdp4/mdp4_plane.o \
Stephane Viau2e362e12014-11-18 12:49:48 -0500[diff] [blame]37 mdp/mdp5/mdp5_cfg.o \
Stephane Viau0deed252014-11-18 12:49:49 -0500[diff] [blame]38 mdp/mdp5/mdp5_ctl.o \
Rob Clark06c0dd92013-11-30 17:51:47 -0500[diff] [blame]39 mdp/mdp5/mdp5_crtc.o \
40 mdp/mdp5/mdp5_encoder.o \
41 mdp/mdp5/mdp5_irq.o \
Archit Taneja990a4002016-05-07 23:11:25 +0530[diff] [blame]42 mdp/mdp5/mdp5_mdss.o \
Rob Clark06c0dd92013-11-30 17:51:47 -0500[diff] [blame]43 mdp/mdp5/mdp5_kms.o \
Rob Clarkc056b552016-11-01 09:56:51 -0400[diff] [blame]44 mdp/mdp5/mdp5_pipe.o \
Archit Taneja6803c602017-03-23 15:57:56 +0530[diff] [blame]45 mdp/mdp5/mdp5_mixer.o \
Rob Clark06c0dd92013-11-30 17:51:47 -0500[diff] [blame]46 mdp/mdp5/mdp5_plane.o \
47 mdp/mdp5/mdp5_smp.o \
Rob Clarkcf3a7e42014-11-08 13:21:06 -0500[diff] [blame]48 msm_atomic.o \
Rob Clarkedcd60c2016-03-16 12:56:12 -0400[diff] [blame]49 msm_debugfs.o \
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]50 msm_drv.o \
51 msm_fb.o \
Rob Clarkfde5de62016-03-15 15:35:08 -0400[diff] [blame]52 msm_fence.o \
Rob Clark7198e6b2013-07-19 12:59:32 -0400[diff] [blame]53 msm_gem.o \
Rob Clark05b84912013-09-28 11:28:35 -0400[diff] [blame]54 msm_gem_prime.o \
Rob Clark68209392016-05-17 16:19:32 -0400[diff] [blame]55 msm_gem_shrinker.o \
Rob Clark7198e6b2013-07-19 12:59:32 -0400[diff] [blame]56 msm_gem_submit.o \
Rob Clark667ce332016-09-28 19:58:32 -0400[diff] [blame]57 msm_gem_vma.o \
Rob Clark7198e6b2013-07-19 12:59:32 -0400[diff] [blame]58 msm_gpu.o \
Rob Clark871d8122013-11-16 12:56:06 -0500[diff] [blame]59 msm_iommu.o \
Rob Clark70c70f02014-05-30 14:49:43 -0400[diff] [blame]60 msm_perf.o \
Rob Clarka7d3c952014-05-30 14:47:38 -0400[diff] [blame]61 msm_rd.o \
Jordan Crousef7de1542017-10-20 11:06:55 -0600[diff] [blame]62 msm_ringbuffer.o \
63 msm_submitqueue.o
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]64
Rob Clark331dc0b2017-12-13 15:12:56 -0500[diff] [blame]65msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o
66
Archit Tanejaa9ee34b2015-07-13 12:12:07 +0530[diff] [blame]67msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
Rob Clark3e875992014-08-01 13:08:11 -0400[diff] [blame]68msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
Archit Tanejaea184892016-02-25 11:22:39 +0530[diff] [blame]69msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
Archit Tanejae17afdc2016-02-25 11:22:44 +0530[diff] [blame]70msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o
Hai Li825637b2015-05-15 13:04:04 -0400[diff] [blame]71
Rob Clarkfeb46f02016-03-20 10:16:29 -0400[diff] [blame]72msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
73
Hai Lia6895542015-03-31 14:36:33 -0400[diff] [blame]74msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
Vinay Simha BN776638e2015-10-19 12:27:11 +0530[diff] [blame]75 mdp/mdp4/mdp4_dsi_encoder.o \
Hai Lid248b612015-08-13 17:49:29 -0400[diff] [blame]76 dsi/dsi_cfg.o \
Hai Lia6895542015-03-31 14:36:33 -0400[diff] [blame]77 dsi/dsi_host.o \
78 dsi/dsi_manager.o \
Hai Li5c829022015-08-13 17:45:52 -0400[diff] [blame]79 dsi/phy/dsi_phy.o \
Hai Lid5af49c2015-03-26 19:25:17 -0400[diff] [blame]80 mdp/mdp5/mdp5_cmd_encoder.o
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]81
Hai Li1bf4d7c2015-08-13 17:45:53 -0400[diff] [blame]82msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
83msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
Archit Taneja225380b2015-10-14 12:00:34 +0530[diff] [blame]84msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
Archit Tanejaf079f6d2017-01-03 19:45:43 +0530[diff] [blame]85msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
Archit Taneja973e02d2018-01-17 11:35:25 +0530[diff] [blame^]86msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
Hai Li1bf4d7c2015-08-13 17:45:53 -0400[diff] [blame]87
88ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
89msm-y += dsi/pll/dsi_pll.o
90msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
Archit Tanejac6538de2015-10-14 12:03:44 +0530[diff] [blame]91msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
Archit Tanejaf079f6d2017-01-03 19:45:43 +0530[diff] [blame]92msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
Archit Taneja973e02d2018-01-17 11:35:25 +0530[diff] [blame^]93msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
Hai Li1bf4d7c2015-08-13 17:45:53 -0400[diff] [blame]94endif
Hai Li825637b2015-05-15 13:04:04 -0400[diff] [blame]95
Rob Clarkc8afe682013-06-26 12:44:06 -0400[diff] [blame]96obj-$(CONFIG_DRM_MSM) += msm.o