blob: 720904a43c00d93f61e5be340792caa5e3dcaab6 [file] [log] [blame]
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +09001/*
2 * Trusted Foundations support for ARM CPUs
3 *
4 * Copyright (c) 2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of.h>
20#include <asm/firmware.h>
Dmitry Osipenkoebca2a62019-03-18 01:52:04 +030021#include <asm/hardware/cache-l2x0.h>
22#include <asm/outercache.h>
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090023#include <asm/trusted_foundations.h>
24
Dmitry Osipenkoebca2a62019-03-18 01:52:04 +030025#define TF_CACHE_MAINT 0xfffff100
26
27#define TF_CACHE_ENABLE 1
28#define TF_CACHE_DISABLE 2
29
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090030#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
31
Alexandre Courbotb77b6e82014-02-07 13:35:05 +090032#define TF_CPU_PM 0xfffffffc
33#define TF_CPU_PM_S3 0xffffffe3
34#define TF_CPU_PM_S2 0xffffffe6
35#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
36#define TF_CPU_PM_S1 0xffffffe4
37#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
38
39static unsigned long cpu_boot_addr;
40
Stefan Agner4ea7bdc2018-03-25 20:09:56 +020041static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090042{
Stefan Agner4ea7bdc2018-03-25 20:09:56 +020043 register u32 r0 asm("r0") = type;
44 register u32 r1 asm("r1") = arg1;
45 register u32 r2 asm("r2") = arg2;
46
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090047 asm volatile(
48 ".arch_extension sec\n\t"
Stefan Agner4ea7bdc2018-03-25 20:09:56 +020049 "stmfd sp!, {r4 - r11}\n\t"
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090050 __asmeq("%0", "r0")
51 __asmeq("%1", "r1")
52 __asmeq("%2", "r2")
53 "mov r3, #0\n\t"
54 "mov r4, #0\n\t"
55 "smc #0\n\t"
Stefan Agner4ea7bdc2018-03-25 20:09:56 +020056 "ldmfd sp!, {r4 - r11}\n\t"
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090057 :
Stefan Agner4ea7bdc2018-03-25 20:09:56 +020058 : "r" (r0), "r" (r1), "r" (r2)
59 : "memory", "r3", "r12", "lr");
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090060}
61
62static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
63{
Alexandre Courbotb77b6e82014-02-07 13:35:05 +090064 cpu_boot_addr = boot_addr;
65 tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
66
67 return 0;
68}
69
Dmitry Osipenko96446e22019-03-18 01:52:05 +030070static int tf_prepare_idle(unsigned long mode)
Alexandre Courbotb77b6e82014-02-07 13:35:05 +090071{
Dmitry Osipenko96446e22019-03-18 01:52:05 +030072 switch (mode) {
73 case TF_PM_MODE_LP0:
74 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
75 break;
76
77 case TF_PM_MODE_LP1:
78 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
79 break;
80
81 case TF_PM_MODE_LP1_NO_MC_CLK:
82 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
83 cpu_boot_addr);
84 break;
85
86 case TF_PM_MODE_LP2:
87 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
88 break;
89
90 case TF_PM_MODE_LP2_NOFLUSH_L2:
91 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
92 cpu_boot_addr);
93 break;
94
95 default:
96 return -EINVAL;
97 }
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +090098
99 return 0;
100}
101
Dmitry Osipenkoebca2a62019-03-18 01:52:04 +0300102#ifdef CONFIG_CACHE_L2X0
103static void tf_cache_write_sec(unsigned long val, unsigned int reg)
104{
105 u32 l2x0_way_mask = 0xff;
106
107 switch (reg) {
108 case L2X0_CTRL:
109 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
110 l2x0_way_mask = 0xffff;
111
112 if (val == L2X0_CTRL_EN)
113 tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
114 l2x0_saved_regs.aux_ctrl);
115 else
116 tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
117 l2x0_way_mask);
118 break;
119
120 default:
121 break;
122 }
123}
124
125static int tf_init_cache(void)
126{
127 outer_cache.write_sec = tf_cache_write_sec;
128
129 return 0;
130}
131#endif /* CONFIG_CACHE_L2X0 */
132
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +0900133static const struct firmware_ops trusted_foundations_ops = {
134 .set_cpu_boot_addr = tf_set_cpu_boot_addr,
Alexandre Courbotb77b6e82014-02-07 13:35:05 +0900135 .prepare_idle = tf_prepare_idle,
Dmitry Osipenkoebca2a62019-03-18 01:52:04 +0300136#ifdef CONFIG_CACHE_L2X0
137 .l2x0_init = tf_init_cache,
138#endif
Alexandre Courbotd9a1bea2013-11-24 15:30:46 +0900139};
140
141void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
142{
143 /*
144 * we are not using version information for now since currently
145 * supported SMCs are compatible with all TF releases
146 */
147 register_firmware_ops(&trusted_foundations_ops);
148}
149
150void of_register_trusted_foundations(void)
151{
152 struct device_node *node;
153 struct trusted_foundations_platform_data pdata;
154 int err;
155
156 node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
157 if (!node)
158 return;
159
160 err = of_property_read_u32(node, "tlm,version-major",
161 &pdata.version_major);
162 if (err != 0)
163 panic("Trusted Foundation: missing version-major property\n");
164 err = of_property_read_u32(node, "tlm,version-minor",
165 &pdata.version_minor);
166 if (err != 0)
167 panic("Trusted Foundation: missing version-minor property\n");
168 register_trusted_foundations(&pdata);
169}