blob: ee3fbf941e79871190fbe26c4796b9c33afc7a7f [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Peter De Schrijveradd29e62011-10-12 14:53:05 +03002/dts-v1/;
3
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05304#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06005#include "tegra20.dtsi"
Peter De Schrijveradd29e62011-10-12 14:53:05 +03006
7/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00008 model = "NVIDIA Tegra20 Ventana evaluation board";
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 compatible = "nvidia,ventana", "nvidia,tegra20";
10
Stephen Warren553c0a22013-12-09 14:43:59 -070011 aliases {
12 rtc0 = "/i2c@7000d000/tps6586x@34";
13 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080014 serial0 = &uartd;
Stephen Warren553c0a22013-12-09 14:43:59 -070015 };
16
Jon Hunterf5bbb322016-02-09 13:51:59 +000017 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
Peter De Schrijveradd29e62011-10-12 14:53:05 +030021 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060022 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030023 };
24
Stephen Warren58ecb232013-11-25 17:53:16 -070025 host1x@50000000 {
Stephen Warren1771a252014-01-07 16:33:31 -070026 dc@54200000 {
27 rgb {
28 status = "okay";
29
30 nvidia,panel = <&panel>;
31 };
32 };
33
Stephen Warren58ecb232013-11-25 17:53:16 -070034 hdmi@54280000 {
Stephen Warren97d55202013-01-02 14:53:21 -070035 status = "okay";
36
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39
40 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070041 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
42 GPIO_ACTIVE_HIGH>;
Stephen Warren97d55202013-01-02 14:53:21 -070043 };
44 };
45
Stephen Warren58ecb232013-11-25 17:53:16 -070046 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060047 pinctrl-names = "default";
48 pinctrl-0 = <&state_default>;
49
50 state_default: pinmux {
51 ata {
52 nvidia,pins = "ata";
53 nvidia,function = "ide";
54 };
55 atb {
56 nvidia,pins = "atb", "gma", "gme";
57 nvidia,function = "sdio4";
58 };
59 atc {
60 nvidia,pins = "atc";
61 nvidia,function = "nand";
62 };
63 atd {
64 nvidia,pins = "atd", "ate", "gmb", "spia",
65 "spib", "spic";
66 nvidia,function = "gmi";
67 };
68 cdev1 {
69 nvidia,pins = "cdev1";
70 nvidia,function = "plla_out";
71 };
72 cdev2 {
73 nvidia,pins = "cdev2";
74 nvidia,function = "pllp_out4";
75 };
76 crtp {
77 nvidia,pins = "crtp", "lm1";
78 nvidia,function = "crt";
79 };
80 csus {
81 nvidia,pins = "csus";
82 nvidia,function = "vi_sensor_clk";
83 };
84 dap1 {
85 nvidia,pins = "dap1";
86 nvidia,function = "dap1";
87 };
88 dap2 {
89 nvidia,pins = "dap2";
90 nvidia,function = "dap2";
91 };
92 dap3 {
93 nvidia,pins = "dap3";
94 nvidia,function = "dap3";
95 };
96 dap4 {
97 nvidia,pins = "dap4";
98 nvidia,function = "dap4";
99 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600100 dta {
101 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
102 nvidia,function = "vi";
103 };
104 dtf {
105 nvidia,pins = "dtf";
106 nvidia,function = "i2c3";
107 };
108 gmc {
109 nvidia,pins = "gmc";
110 nvidia,function = "uartd";
111 };
112 gmd {
113 nvidia,pins = "gmd";
114 nvidia,function = "sflash";
115 };
116 gpu {
117 nvidia,pins = "gpu";
118 nvidia,function = "pwm";
119 };
120 gpu7 {
121 nvidia,pins = "gpu7";
122 nvidia,function = "rtck";
123 };
124 gpv {
125 nvidia,pins = "gpv", "slxa", "slxk";
126 nvidia,function = "pcie";
127 };
128 hdint {
Mark Zhangcf6334642012-10-25 14:52:30 +0800129 nvidia,pins = "hdint";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600130 nvidia,function = "hdmi";
131 };
132 i2cp {
133 nvidia,pins = "i2cp";
134 nvidia,function = "i2cp";
135 };
136 irrx {
137 nvidia,pins = "irrx", "irtx";
138 nvidia,function = "uartb";
139 };
140 kbca {
141 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
142 "kbce", "kbcf";
143 nvidia,function = "kbc";
144 };
145 lcsn {
146 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
147 "lsdi", "lvp0";
148 nvidia,function = "rsvd4";
149 };
150 ld0 {
151 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
152 "ld5", "ld6", "ld7", "ld8", "ld9",
153 "ld10", "ld11", "ld12", "ld13", "ld14",
154 "ld15", "ld16", "ld17", "ldi", "lhp0",
155 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
156 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
157 "lspi", "lvp1", "lvs";
158 nvidia,function = "displaya";
159 };
Mark Zhangcf6334642012-10-25 14:52:30 +0800160 owc {
161 nvidia,pins = "owc", "spdi", "spdo", "uac";
162 nvidia,function = "rsvd2";
163 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600164 pmc {
165 nvidia,pins = "pmc";
166 nvidia,function = "pwr_on";
167 };
168 rm {
169 nvidia,pins = "rm";
170 nvidia,function = "i2c1";
171 };
172 sdb {
173 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
174 nvidia,function = "sdio3";
175 };
176 sdio1 {
177 nvidia,pins = "sdio1";
178 nvidia,function = "sdio1";
179 };
180 slxd {
181 nvidia,pins = "slxd";
182 nvidia,function = "spdif";
183 };
184 spid {
185 nvidia,pins = "spid", "spie", "spif";
186 nvidia,function = "spi1";
187 };
188 spig {
189 nvidia,pins = "spig", "spih";
190 nvidia,function = "spi2_alt";
191 };
192 uaa {
193 nvidia,pins = "uaa", "uab", "uda";
194 nvidia,function = "ulpi";
195 };
196 uad {
197 nvidia,pins = "uad";
198 nvidia,function = "irda";
199 };
200 uca {
201 nvidia,pins = "uca", "ucb";
202 nvidia,function = "uartc";
203 };
204 conf_ata {
205 nvidia,pins = "ata", "atb", "atc", "atd",
206 "cdev1", "cdev2", "dap1", "dap2",
207 "dap4", "ddc", "dtf", "gma", "gmc",
208 "gme", "gpu", "gpu7", "i2cp", "irrx",
209 "irtx", "pta", "rm", "sdc", "sdd",
210 "slxc", "slxd", "slxk", "spdi", "spdo",
211 "uac", "uad", "uca", "ucb", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530212 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600214 };
215 conf_ate {
216 nvidia,pins = "ate", "csus", "dap3", "gmd",
217 "gpv", "owc", "spia", "spib", "spic",
218 "spid", "spie", "spig";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600221 };
222 conf_ck32 {
223 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
224 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600226 };
227 conf_crtp {
228 nvidia,pins = "crtp", "gmb", "slxa", "spih";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530229 nvidia,pull = <TEGRA_PIN_PULL_UP>;
230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600231 };
232 conf_dta {
233 nvidia,pins = "dta", "dtb", "dtc", "dtd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530234 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
235 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600236 };
237 conf_dte {
238 nvidia,pins = "dte", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530239 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600241 };
242 conf_hdint {
243 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
244 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530245 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600246 };
247 conf_kbca {
248 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
249 "kbce", "kbcf", "sdio1", "uaa", "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530250 nvidia,pull = <TEGRA_PIN_PULL_UP>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600252 };
253 conf_lc {
254 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530255 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600256 };
257 conf_ld0 {
258 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
259 "ld5", "ld6", "ld7", "ld8", "ld9",
260 "ld10", "ld11", "ld12", "ld13", "ld14",
261 "ld15", "ld16", "ld17", "ldi", "lhp0",
262 "lhp1", "lhp2", "lhs", "lm0", "lpp",
263 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
264 "lvp1", "lvs", "pmc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600266 };
267 conf_ld17_0 {
268 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
269 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530270 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600271 };
Wei Nic7294292012-09-21 16:54:58 +0800272 drive_sdio1 {
273 nvidia,pins = "drive_sdio1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530274 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
275 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
276 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
Wei Nic7294292012-09-21 16:54:58 +0800277 nvidia,pull-down-strength = <31>;
278 nvidia,pull-up-strength = <31>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530279 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
280 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
Wei Nic7294292012-09-21 16:54:58 +0800281 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600282 };
Mark Zhangcf6334642012-10-25 14:52:30 +0800283
284 state_i2cmux_ddc: pinmux_i2cmux_ddc {
285 ddc {
286 nvidia,pins = "ddc";
287 nvidia,function = "i2c2";
288 };
289 pta {
290 nvidia,pins = "pta";
291 nvidia,function = "rsvd4";
292 };
293 };
294
295 state_i2cmux_pta: pinmux_i2cmux_pta {
296 ddc {
297 nvidia,pins = "ddc";
298 nvidia,function = "rsvd4";
299 };
300 pta {
301 nvidia,pins = "pta";
302 nvidia,function = "i2c2";
303 };
304 };
305
306 state_i2cmux_idle: pinmux_i2cmux_idle {
307 ddc {
308 nvidia,pins = "ddc";
309 nvidia,function = "rsvd4";
310 };
311 pta {
312 nvidia,pins = "pta";
313 nvidia,function = "rsvd4";
314 };
315 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600316 };
317
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600318 i2s@70002800 {
319 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600320 };
321
322 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600323 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600324 };
325
Stephen Warren1771a252014-01-07 16:33:31 -0700326 pwm: pwm@7000a000 {
327 status = "okay";
328 };
329
Stephen Warren88950f3b2011-11-21 14:44:09 -0700330 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600331 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700332 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700333
334 wm8903: wm8903@1a {
335 compatible = "wlf,wm8903";
336 reg = <0x1a>;
337 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700338 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700339
340 gpio-controller;
341 #gpio-cells = <2>;
342
343 micdet-cfg = <0>;
344 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600345 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700346 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530347
348 /* ALS and proximity sensor */
349 isl29018@44 {
350 compatible = "isil,isl29018";
351 reg = <0x44>;
352 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700353 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530354 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700355 };
356
357 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600358 status = "okay";
Stephen Warren97d55202013-01-02 14:53:21 -0700359 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700360 };
361
Mark Zhangcf6334642012-10-25 14:52:30 +0800362 i2cmux {
363 compatible = "i2c-mux-pinctrl";
364 #address-cells = <1>;
365 #size-cells = <0>;
366
367 i2c-parent = <&{/i2c@7000c400}>;
368
369 pinctrl-names = "ddc", "pta", "idle";
370 pinctrl-0 = <&state_i2cmux_ddc>;
371 pinctrl-1 = <&state_i2cmux_pta>;
372 pinctrl-2 = <&state_i2cmux_idle>;
373
Stephen Warren97d55202013-01-02 14:53:21 -0700374 hdmi_ddc: i2c@0 {
Mark Zhangcf6334642012-10-25 14:52:30 +0800375 reg = <0>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 };
379
Stephen Warren1771a252014-01-07 16:33:31 -0700380 lvds_ddc: i2c@1 {
Mark Zhangcf6334642012-10-25 14:52:30 +0800381 reg = <1>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 };
385 };
386
Stephen Warren88950f3b2011-11-21 14:44:09 -0700387 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600388 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700389 clock-frequency = <400000>;
390 };
391
392 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600393 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700394 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600395
396 pmic: tps6586x@34 {
397 compatible = "ti,tps6586x";
398 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700399 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600400
Stephen Warren44b12ef2012-09-11 11:42:26 -0600401 ti,system-power-controller;
402
Stephen Warren017a0102012-06-20 16:53:41 -0600403 #gpio-cells = <2>;
404 gpio-controller;
405
406 sys-supply = <&vdd_5v0_reg>;
407 vin-sm0-supply = <&sys_reg>;
408 vin-sm1-supply = <&sys_reg>;
409 vin-sm2-supply = <&sys_reg>;
410 vinldo01-supply = <&sm2_reg>;
411 vinldo23-supply = <&sm2_reg>;
412 vinldo4-supply = <&sm2_reg>;
413 vinldo678-supply = <&sm2_reg>;
414 vinldo9-supply = <&sm2_reg>;
415
416 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600417 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600418 regulator-name = "vdd_sys";
419 regulator-always-on;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600423 regulator-name = "vdd_sm0,vdd_core";
424 regulator-min-microvolt = <1200000>;
425 regulator-max-microvolt = <1200000>;
426 regulator-always-on;
427 };
428
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600429 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600430 regulator-name = "vdd_sm1,vdd_cpu";
431 regulator-min-microvolt = <1000000>;
432 regulator-max-microvolt = <1000000>;
433 regulator-always-on;
434 };
435
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600436 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600437 regulator-name = "vdd_sm2,vin_ldo*";
438 regulator-min-microvolt = <3700000>;
439 regulator-max-microvolt = <3700000>;
440 regulator-always-on;
441 };
442
443 /* LDO0 is not connected to anything */
444
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600445 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600446 regulator-name = "vdd_ldo1,avdd_pll*";
447 regulator-min-microvolt = <1100000>;
448 regulator-max-microvolt = <1100000>;
449 regulator-always-on;
450 };
451
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600452 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600453 regulator-name = "vdd_ldo2,vdd_rtc";
454 regulator-min-microvolt = <1200000>;
455 regulator-max-microvolt = <1200000>;
456 };
457
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600458 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600459 regulator-name = "vdd_ldo3,avdd_usb*";
460 regulator-min-microvolt = <3300000>;
461 regulator-max-microvolt = <3300000>;
462 regulator-always-on;
463 };
464
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600465 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600466 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>;
469 regulator-always-on;
470 };
471
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600472 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600473 regulator-name = "vdd_ldo5,vcore_mmc";
474 regulator-min-microvolt = <2850000>;
475 regulator-max-microvolt = <2850000>;
476 regulator-always-on;
477 };
478
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600479 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600480 regulator-name = "vdd_ldo6,avdd_vdac";
481 regulator-min-microvolt = <1800000>;
482 regulator-max-microvolt = <1800000>;
483 };
484
Stephen Warren97d55202013-01-02 14:53:21 -0700485 hdmi_vdd_reg: ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600486 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
487 regulator-min-microvolt = <3300000>;
488 regulator-max-microvolt = <3300000>;
489 };
490
Stephen Warren97d55202013-01-02 14:53:21 -0700491 hdmi_pll_reg: ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600492 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
493 regulator-min-microvolt = <1800000>;
494 regulator-max-microvolt = <1800000>;
495 };
496
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600497 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600498 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
499 regulator-min-microvolt = <2850000>;
500 regulator-max-microvolt = <2850000>;
501 regulator-always-on;
502 };
503
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600504 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600505 regulator-name = "vdd_rtc_out,vdd_cell";
506 regulator-min-microvolt = <3300000>;
507 regulator-max-microvolt = <3300000>;
508 regulator-always-on;
509 };
510 };
511 };
Thierry Redingee9f7262012-11-09 23:01:21 +0100512
513 temperature-sensor@4c {
514 compatible = "onnn,nct1008";
515 reg = <0x4c>;
516 };
Stephen Warren017a0102012-06-20 16:53:41 -0600517 };
518
Stephen Warren58ecb232013-11-25 17:53:16 -0700519 pmc@7000e400 {
Stephen Warren017a0102012-06-20 16:53:41 -0600520 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800521 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800522 nvidia,cpu-pwr-good-time = <2000>;
523 nvidia,cpu-pwr-off-time = <100>;
524 nvidia,core-pwr-good-time = <3845 3845>;
525 nvidia,core-pwr-off-time = <458>;
526 nvidia,sys-clock-req-active-high;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700527 };
528
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600529 usb@c5000000 {
530 status = "okay";
531 };
532
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530533 usb-phy@c5000000 {
534 status = "okay";
535 };
536
Stephen Warrenc04abb32012-05-11 17:03:26 -0600537 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600538 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700539 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
540 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530541 };
542
543 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530544 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700545 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
546 GPIO_ACTIVE_LOW>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600547 };
548
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600549 usb@c5008000 {
550 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600551 };
552
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530553 usb-phy@c5008000 {
554 status = "okay";
555 };
556
Wei Nic7294292012-09-21 16:54:58 +0800557 sdhci@c8000000 {
558 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700559 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
Wei Nic7294292012-09-21 16:54:58 +0800560 bus-width = <4>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600561 keep-power-in-suspend;
Wei Nic7294292012-09-21 16:54:58 +0800562 };
563
Stephen Warrenc04abb32012-05-11 17:03:26 -0600564 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600565 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700566 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
567 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
568 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200569 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600570 };
571
572 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600573 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200574 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600575 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600576 };
577
Stephen Warren1771a252014-01-07 16:33:31 -0700578 backlight: backlight {
579 compatible = "pwm-backlight";
580
581 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
582 power-supply = <&vdd_bl_reg>;
583 pwms = <&pwm 2 5000000>;
584
585 brightness-levels = <0 4 8 16 32 64 128 255>;
586 default-brightness-level = <6>;
587 };
588
Joseph Lo7021d122013-04-03 19:31:27 +0800589 clocks {
590 compatible = "simple-bus";
591 #address-cells = <1>;
592 #size-cells = <0>;
593
Stephen Warren58ecb232013-11-25 17:53:16 -0700594 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800595 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200596 reg = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800597 #clock-cells = <0>;
598 clock-frequency = <32768>;
599 };
600 };
601
Joseph Lo5741a252013-04-03 19:31:48 +0800602 gpio-keys {
603 compatible = "gpio-keys";
604
605 power {
606 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700607 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530608 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000609 wakeup-source;
Joseph Lo5741a252013-04-03 19:31:48 +0800610 };
611 };
612
Stephen Warren1771a252014-01-07 16:33:31 -0700613 panel: panel {
614 compatible = "chunghwa,claa101wa01a", "simple-panel";
615
616 power-supply = <&vdd_pnl_reg>;
617 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
618
619 backlight = <&backlight>;
620 ddc-i2c-bus = <&lvds_ddc>;
621 };
622
Stephen Warren017a0102012-06-20 16:53:41 -0600623 regulators {
624 compatible = "simple-bus";
625 #address-cells = <1>;
626 #size-cells = <0>;
627
628 vdd_5v0_reg: regulator@0 {
629 compatible = "regulator-fixed";
630 reg = <0>;
631 regulator-name = "vdd_5v0";
632 regulator-min-microvolt = <5000000>;
633 regulator-max-microvolt = <5000000>;
634 regulator-always-on;
635 };
636
637 regulator@1 {
638 compatible = "regulator-fixed";
639 reg = <1>;
640 regulator-name = "vdd_1v5";
641 regulator-min-microvolt = <1500000>;
642 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700643 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600644 };
645
646 regulator@2 {
647 compatible = "regulator-fixed";
648 reg = <2>;
649 regulator-name = "vdd_1v2";
650 regulator-min-microvolt = <1200000>;
651 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700652 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600653 enable-active-high;
654 };
655
Stephen Warren1771a252014-01-07 16:33:31 -0700656 vdd_pnl_reg: regulator@3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600657 compatible = "regulator-fixed";
658 reg = <3>;
659 regulator-name = "vdd_pnl";
660 regulator-min-microvolt = <2800000>;
661 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700662 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600663 enable-active-high;
664 };
665
Stephen Warren1771a252014-01-07 16:33:31 -0700666 vdd_bl_reg: regulator@4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600667 compatible = "regulator-fixed";
668 reg = <4>;
669 regulator-name = "vdd_bl";
670 regulator-min-microvolt = <2800000>;
671 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700672 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600673 enable-active-high;
674 };
675 };
676
Stephen Warren797acf72012-01-11 16:09:57 -0700677 sound {
678 compatible = "nvidia,tegra-audio-wm8903-ventana",
679 "nvidia,tegra-audio-wm8903";
680 nvidia,model = "NVIDIA Tegra Ventana";
681
682 nvidia,audio-routing =
683 "Headphone Jack", "HPOUTR",
684 "Headphone Jack", "HPOUTL",
685 "Int Spk", "ROP",
686 "Int Spk", "RON",
687 "Int Spk", "LOP",
688 "Int Spk", "LON",
689 "Mic Jack", "MICBIAS",
690 "IN1L", "Mic Jack";
691
692 nvidia,i2s-controller = <&tegra_i2s1>;
693 nvidia,audio-codec = <&wm8903>;
694
Stephen Warren3325f1b2013-02-12 17:25:15 -0700695 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
696 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
697 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
698 GPIO_ACTIVE_HIGH>;
699 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
700 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600701
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300702 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
703 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
704 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600705 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren797acf72012-01-11 16:09:57 -0700706 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300707};