blob: 72ca887feb0d56bafb47334b28eafe660efc418d [file] [log] [blame]
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001/*
2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __MV88E6XXX_H
12#define __MV88E6XXX_H
13
Vivien Didelot194fea72015-08-10 09:09:47 -040014#include <linux/if_vlan.h>
15
Andrew Lunn80c46272015-06-20 18:42:30 +020016#ifndef UINT64_MAX
17#define UINT64_MAX (u64)(~((u64)0))
18#endif
19
Andrew Lunncca8b132015-04-02 04:06:39 +020020#define SMI_CMD 0x00
21#define SMI_CMD_BUSY BIT(15)
22#define SMI_CMD_CLAUSE_22 BIT(12)
23#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
24#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
25#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
26#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
27#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
28#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
29#define SMI_DATA 0x01
Guenter Roeckb2eb0662015-04-02 04:06:30 +020030
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000031#define REG_PORT(p) (0x10 + (p))
Andrew Lunncca8b132015-04-02 04:06:39 +020032#define PORT_STATUS 0x00
33#define PORT_STATUS_PAUSE_EN BIT(15)
34#define PORT_STATUS_MY_PAUSE BIT(14)
35#define PORT_STATUS_HD_FLOW BIT(13)
36#define PORT_STATUS_PHY_DETECT BIT(12)
37#define PORT_STATUS_LINK BIT(11)
38#define PORT_STATUS_DUPLEX BIT(10)
39#define PORT_STATUS_SPEED_MASK 0x0300
40#define PORT_STATUS_SPEED_10 0x0000
41#define PORT_STATUS_SPEED_100 0x0100
42#define PORT_STATUS_SPEED_1000 0x0200
43#define PORT_STATUS_EEE BIT(6) /* 6352 */
44#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
45#define PORT_STATUS_MGMII BIT(6) /* 6185 */
46#define PORT_STATUS_TX_PAUSED BIT(5)
47#define PORT_STATUS_FLOW_CTRL BIT(4)
48#define PORT_PCS_CTRL 0x01
Andrew Lunn54d792f2015-05-06 01:09:47 +020049#define PORT_PCS_CTRL_FC BIT(7)
50#define PORT_PCS_CTRL_FORCE_FC BIT(6)
51#define PORT_PCS_CTRL_LINK_UP BIT(5)
52#define PORT_PCS_CTRL_FORCE_LINK BIT(4)
53#define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
54#define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
55#define PORT_PCS_CTRL_10 0x00
56#define PORT_PCS_CTRL_100 0x01
57#define PORT_PCS_CTRL_1000 0x02
58#define PORT_PCS_CTRL_UNFORCED 0x03
59#define PORT_PAUSE_CTRL 0x02
Andrew Lunncca8b132015-04-02 04:06:39 +020060#define PORT_SWITCH_ID 0x03
Andrew Lunn54d792f2015-05-06 01:09:47 +020061#define PORT_SWITCH_ID_6031 0x0310
62#define PORT_SWITCH_ID_6035 0x0350
63#define PORT_SWITCH_ID_6046 0x0480
64#define PORT_SWITCH_ID_6061 0x0610
65#define PORT_SWITCH_ID_6065 0x0650
Andrew Lunncca8b132015-04-02 04:06:39 +020066#define PORT_SWITCH_ID_6085 0x04a0
Andrew Lunn54d792f2015-05-06 01:09:47 +020067#define PORT_SWITCH_ID_6092 0x0970
Andrew Lunncca8b132015-04-02 04:06:39 +020068#define PORT_SWITCH_ID_6095 0x0950
Andrew Lunn54d792f2015-05-06 01:09:47 +020069#define PORT_SWITCH_ID_6096 0x0980
70#define PORT_SWITCH_ID_6097 0x0990
71#define PORT_SWITCH_ID_6108 0x1070
72#define PORT_SWITCH_ID_6121 0x1040
73#define PORT_SWITCH_ID_6122 0x1050
Andrew Lunncca8b132015-04-02 04:06:39 +020074#define PORT_SWITCH_ID_6123 0x1210
75#define PORT_SWITCH_ID_6123_A1 0x1212
76#define PORT_SWITCH_ID_6123_A2 0x1213
77#define PORT_SWITCH_ID_6131 0x1060
78#define PORT_SWITCH_ID_6131_B2 0x1066
79#define PORT_SWITCH_ID_6152 0x1a40
80#define PORT_SWITCH_ID_6155 0x1a50
81#define PORT_SWITCH_ID_6161 0x1610
82#define PORT_SWITCH_ID_6161_A1 0x1612
83#define PORT_SWITCH_ID_6161_A2 0x1613
84#define PORT_SWITCH_ID_6165 0x1650
85#define PORT_SWITCH_ID_6165_A1 0x1652
86#define PORT_SWITCH_ID_6165_A2 0x1653
87#define PORT_SWITCH_ID_6171 0x1710
88#define PORT_SWITCH_ID_6172 0x1720
Andrew Lunn54d792f2015-05-06 01:09:47 +020089#define PORT_SWITCH_ID_6175 0x1750
Andrew Lunncca8b132015-04-02 04:06:39 +020090#define PORT_SWITCH_ID_6176 0x1760
91#define PORT_SWITCH_ID_6182 0x1a60
92#define PORT_SWITCH_ID_6185 0x1a70
Andrew Lunn54d792f2015-05-06 01:09:47 +020093#define PORT_SWITCH_ID_6240 0x2400
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -070094#define PORT_SWITCH_ID_6320 0x1150
95#define PORT_SWITCH_ID_6320_A1 0x1151
96#define PORT_SWITCH_ID_6320_A2 0x1152
97#define PORT_SWITCH_ID_6321 0x3100
98#define PORT_SWITCH_ID_6321_A1 0x3101
99#define PORT_SWITCH_ID_6321_A2 0x3102
Andrew Lunn54d792f2015-05-06 01:09:47 +0200100#define PORT_SWITCH_ID_6350 0x3710
101#define PORT_SWITCH_ID_6351 0x3750
Andrew Lunncca8b132015-04-02 04:06:39 +0200102#define PORT_SWITCH_ID_6352 0x3520
103#define PORT_SWITCH_ID_6352_A0 0x3521
104#define PORT_SWITCH_ID_6352_A1 0x3522
105#define PORT_CONTROL 0x04
Andrew Lunn54d792f2015-05-06 01:09:47 +0200106#define PORT_CONTROL_USE_CORE_TAG BIT(15)
107#define PORT_CONTROL_DROP_ON_LOCK BIT(14)
108#define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
109#define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
110#define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
111#define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
112#define PORT_CONTROL_HEADER BIT(11)
113#define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
114#define PORT_CONTROL_DOUBLE_TAG BIT(9)
115#define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
116#define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
117#define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
118#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
119#define PORT_CONTROL_DSA_TAG BIT(8)
120#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
121#define PORT_CONTROL_TAG_IF_BOTH BIT(6)
122#define PORT_CONTROL_USE_IP BIT(5)
123#define PORT_CONTROL_USE_TAG BIT(4)
124#define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
125#define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
Andrew Lunncca8b132015-04-02 04:06:39 +0200126#define PORT_CONTROL_STATE_MASK 0x03
127#define PORT_CONTROL_STATE_DISABLED 0x00
128#define PORT_CONTROL_STATE_BLOCKING 0x01
129#define PORT_CONTROL_STATE_LEARNING 0x02
130#define PORT_CONTROL_STATE_FORWARDING 0x03
131#define PORT_CONTROL_1 0x05
132#define PORT_BASE_VLAN 0x06
133#define PORT_DEFAULT_VLAN 0x07
Vivien Didelotb8fee952015-08-13 12:52:19 -0400134#define PORT_DEFAULT_VLAN_MASK 0xfff
Andrew Lunncca8b132015-04-02 04:06:39 +0200135#define PORT_CONTROL_2 0x08
Andrew Lunn54d792f2015-05-06 01:09:47 +0200136#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
137#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
138#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
139#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
140#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
141#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
142#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
Vivien Didelot8efdda42015-08-13 12:52:23 -0400143#define PORT_CONTROL_2_8021Q_MASK (0x03 << 10)
144#define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10)
145#define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10)
146#define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10)
147#define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200148#define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
149#define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
150#define PORT_CONTROL_2_MAP_DA BIT(7)
151#define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
152#define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
153#define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
154#define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
Andrew Lunncca8b132015-04-02 04:06:39 +0200155#define PORT_RATE_CONTROL 0x09
156#define PORT_RATE_CONTROL_2 0x0a
157#define PORT_ASSOC_VECTOR 0x0b
Andrew Lunn54d792f2015-05-06 01:09:47 +0200158#define PORT_ATU_CONTROL 0x0c
159#define PORT_PRI_OVERRIDE 0x0d
160#define PORT_ETH_TYPE 0x0f
Andrew Lunncca8b132015-04-02 04:06:39 +0200161#define PORT_IN_DISCARD_LO 0x10
162#define PORT_IN_DISCARD_HI 0x11
163#define PORT_IN_FILTERED 0x12
164#define PORT_OUT_FILTERED 0x13
Andrew Lunn54d792f2015-05-06 01:09:47 +0200165#define PORT_TAG_REGMAP_0123 0x18
166#define PORT_TAG_REGMAP_4567 0x19
Andrew Lunncca8b132015-04-02 04:06:39 +0200167
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000168#define REG_GLOBAL 0x1b
Andrew Lunncca8b132015-04-02 04:06:39 +0200169#define GLOBAL_STATUS 0x00
170#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
171/* Two bits for 6165, 6185 etc */
172#define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
173#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
174#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
175#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
176#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
177#define GLOBAL_MAC_01 0x01
178#define GLOBAL_MAC_23 0x02
179#define GLOBAL_MAC_45 0x03
Vivien Didelota08df0f2015-08-10 09:09:46 -0400180#define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */
Vivien Didelotb8fee952015-08-13 12:52:19 -0400181#define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */
182#define GLOBAL_VTU_FID_MASK 0xfff
183#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
184#define GLOBAL_VTU_SID_MASK 0x3f
Andrew Lunncca8b132015-04-02 04:06:39 +0200185#define GLOBAL_CONTROL 0x04
186#define GLOBAL_CONTROL_SW_RESET BIT(15)
187#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
188#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
189#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
190#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
Andrew Lunn54d792f2015-05-06 01:09:47 +0200191#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
Andrew Lunncca8b132015-04-02 04:06:39 +0200192#define GLOBAL_CONTROL_DEVICE_EN BIT(7)
193#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
194#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
195#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
196#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
197#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
198#define GLOBAL_CONTROL_TCAM_EN BIT(1)
199#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
200#define GLOBAL_VTU_OP 0x05
Vivien Didelot6b17e862015-08-13 12:52:18 -0400201#define GLOBAL_VTU_OP_BUSY BIT(15)
202#define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
Vivien Didelot7dad08d2015-08-13 12:52:21 -0400203#define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
Vivien Didelotb8fee952015-08-13 12:52:19 -0400204#define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -0400205#define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
206#define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
Andrew Lunncca8b132015-04-02 04:06:39 +0200207#define GLOBAL_VTU_VID 0x06
Vivien Didelotb8fee952015-08-13 12:52:19 -0400208#define GLOBAL_VTU_VID_MASK 0xfff
209#define GLOBAL_VTU_VID_VALID BIT(12)
Andrew Lunncca8b132015-04-02 04:06:39 +0200210#define GLOBAL_VTU_DATA_0_3 0x07
211#define GLOBAL_VTU_DATA_4_7 0x08
212#define GLOBAL_VTU_DATA_8_11 0x09
Vivien Didelotb8fee952015-08-13 12:52:19 -0400213#define GLOBAL_VTU_STU_DATA_MASK 0x03
214#define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00
215#define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01
216#define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02
217#define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03
Vivien Didelot0d3b33e2015-08-13 12:52:22 -0400218#define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00
219#define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
220#define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
221#define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
Andrew Lunncca8b132015-04-02 04:06:39 +0200222#define GLOBAL_ATU_CONTROL 0x0a
Andrew Lunn54d792f2015-05-06 01:09:47 +0200223#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
Andrew Lunncca8b132015-04-02 04:06:39 +0200224#define GLOBAL_ATU_OP 0x0b
225#define GLOBAL_ATU_OP_BUSY BIT(15)
226#define GLOBAL_ATU_OP_NOP (0 << 12)
227#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
228#define GLOBAL_ATU_OP_FLUSH_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
229#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
230#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
231#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
232#define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
233#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
234#define GLOBAL_ATU_DATA 0x0c
Andrew Lunn8a0a2652015-06-20 18:42:29 +0200235#define GLOBAL_ATU_DATA_TRUNK BIT(15)
Vivien Didelotfd231c82015-08-10 09:09:50 -0400236#define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0
237#define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4
Andrew Lunn8a0a2652015-06-20 18:42:29 +0200238#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
239#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
Andrew Lunncca8b132015-04-02 04:06:39 +0200240#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
241#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
242#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
243#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
244#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
245#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
246#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
247#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
248#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
249#define GLOBAL_ATU_MAC_01 0x0d
250#define GLOBAL_ATU_MAC_23 0x0e
251#define GLOBAL_ATU_MAC_45 0x0f
252#define GLOBAL_IP_PRI_0 0x10
253#define GLOBAL_IP_PRI_1 0x11
254#define GLOBAL_IP_PRI_2 0x12
255#define GLOBAL_IP_PRI_3 0x13
256#define GLOBAL_IP_PRI_4 0x14
257#define GLOBAL_IP_PRI_5 0x15
258#define GLOBAL_IP_PRI_6 0x16
259#define GLOBAL_IP_PRI_7 0x17
260#define GLOBAL_IEEE_PRI 0x18
261#define GLOBAL_CORE_TAG_TYPE 0x19
262#define GLOBAL_MONITOR_CONTROL 0x1a
Andrew Lunn15966a22015-05-06 01:09:49 +0200263#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
264#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
265#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
266#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
267#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
Andrew Lunncca8b132015-04-02 04:06:39 +0200268#define GLOBAL_CONTROL_2 0x1c
Andrew Lunn15966a22015-05-06 01:09:49 +0200269#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
270#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
271
Andrew Lunncca8b132015-04-02 04:06:39 +0200272#define GLOBAL_STATS_OP 0x1d
273#define GLOBAL_STATS_OP_BUSY BIT(15)
274#define GLOBAL_STATS_OP_NOP (0 << 12)
275#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
276#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
277#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
278#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
279#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
280#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
281#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
282#define GLOBAL_STATS_COUNTER_32 0x1e
283#define GLOBAL_STATS_COUNTER_01 0x1f
284
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000285#define REG_GLOBAL2 0x1c
Andrew Lunncca8b132015-04-02 04:06:39 +0200286#define GLOBAL2_INT_SOURCE 0x00
287#define GLOBAL2_INT_MASK 0x01
288#define GLOBAL2_MGMT_EN_2X 0x02
289#define GLOBAL2_MGMT_EN_0X 0x03
290#define GLOBAL2_FLOW_CONTROL 0x04
291#define GLOBAL2_SWITCH_MGMT 0x05
Andrew Lunn54d792f2015-05-06 01:09:47 +0200292#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
293#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
294#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
295#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
296#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
Andrew Lunncca8b132015-04-02 04:06:39 +0200297#define GLOBAL2_DEVICE_MAPPING 0x06
Andrew Lunn54d792f2015-05-06 01:09:47 +0200298#define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
299#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
Andrew Lunnd35bd872015-06-20 18:42:32 +0200300#define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
Andrew Lunncca8b132015-04-02 04:06:39 +0200301#define GLOBAL2_TRUNK_MASK 0x07
Andrew Lunn54d792f2015-05-06 01:09:47 +0200302#define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
303#define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
Andrew Lunncca8b132015-04-02 04:06:39 +0200304#define GLOBAL2_TRUNK_MAPPING 0x08
Andrew Lunn54d792f2015-05-06 01:09:47 +0200305#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
306#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
Andrew Lunncca8b132015-04-02 04:06:39 +0200307#define GLOBAL2_INGRESS_OP 0x09
308#define GLOBAL2_INGRESS_DATA 0x0a
309#define GLOBAL2_PVT_ADDR 0x0b
310#define GLOBAL2_PVT_DATA 0x0c
311#define GLOBAL2_SWITCH_MAC 0x0d
312#define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
313#define GLOBAL2_ATU_STATS 0x0e
314#define GLOBAL2_PRIO_OVERRIDE 0x0f
Andrew Lunn15966a22015-05-06 01:09:49 +0200315#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
316#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
317#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
318#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
Andrew Lunncca8b132015-04-02 04:06:39 +0200319#define GLOBAL2_EEPROM_OP 0x14
Andrew Lunn966bce32015-08-08 17:04:50 +0200320#define GLOBAL2_EEPROM_OP_BUSY BIT(15)
321#define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY)
322#define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY)
323#define GLOBAL2_EEPROM_OP_LOAD BIT(11)
324#define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10)
325#define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff
Andrew Lunncca8b132015-04-02 04:06:39 +0200326#define GLOBAL2_EEPROM_DATA 0x15
327#define GLOBAL2_PTP_AVB_OP 0x16
328#define GLOBAL2_PTP_AVB_DATA 0x17
329#define GLOBAL2_SMI_OP 0x18
330#define GLOBAL2_SMI_OP_BUSY BIT(15)
331#define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
332#define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
333 GLOBAL2_SMI_OP_CLAUSE_22)
334#define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
335 GLOBAL2_SMI_OP_CLAUSE_22)
336#define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
337#define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
338#define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
339#define GLOBAL2_SMI_DATA 0x19
340#define GLOBAL2_SCRATCH_MISC 0x1a
Andrew Lunn56d95e22015-06-20 18:42:33 +0200341#define GLOBAL2_SCRATCH_BUSY BIT(15)
342#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
343#define GLOBAL2_SCRATCH_VALUE_MASK 0xff
Andrew Lunncca8b132015-04-02 04:06:39 +0200344#define GLOBAL2_WDOG_CONTROL 0x1b
345#define GLOBAL2_QOS_WEIGHT 0x1c
346#define GLOBAL2_MISC 0x1d
Guenter Roeckdefb05b2015-03-26 18:36:38 -0700347
Vivien Didelotfd231c82015-08-10 09:09:50 -0400348struct mv88e6xxx_atu_entry {
349 u16 fid;
350 u8 state;
351 bool trunk;
352 u16 portv_trunkid;
353 u8 mac[ETH_ALEN];
354};
355
Vivien Didelotb8fee952015-08-13 12:52:19 -0400356struct mv88e6xxx_vtu_stu_entry {
357 /* VTU only */
358 u16 vid;
359 u16 fid;
360
361 /* VTU and STU */
362 u8 sid;
363 bool valid;
364 u8 data[DSA_MAX_PORTS];
365};
366
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000367struct mv88e6xxx_priv_state {
Barry Grussling3675c8d2013-01-08 16:05:53 +0000368 /* When using multi-chip addressing, this mutex protects
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000369 * access to the indirect access registers. (In single-chip
370 * mode, this mutex is effectively useless.)
371 */
372 struct mutex smi_mutex;
373
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000374#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
Barry Grussling3675c8d2013-01-08 16:05:53 +0000375 /* Handles automatic disabling and re-enabling of the PHY
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000376 * polling unit.
377 */
378 struct mutex ppu_mutex;
379 int ppu_disabled;
380 struct work_struct ppu_work;
381 struct timer_list ppu_timer;
382#endif
383
Barry Grussling3675c8d2013-01-08 16:05:53 +0000384 /* This mutex serialises access to the statistics unit.
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000385 * Hold this mutex over snapshot + dump sequences.
386 */
387 struct mutex stats_mutex;
Peter Korsgaardec80bfc2011-04-05 03:03:56 +0000388
Guenter Roeck3ad50cc2014-10-29 10:44:56 -0700389 /* This mutex serializes phy access for chips with
390 * indirect phy addressing. It is unused for chips
391 * with direct phy access.
392 */
393 struct mutex phy_mutex;
394
Guenter Roeck33b43df2014-10-29 10:45:03 -0700395 /* This mutex serializes eeprom access for chips with
396 * eeprom support.
397 */
398 struct mutex eeprom_mutex;
399
Peter Korsgaardec80bfc2011-04-05 03:03:56 +0000400 int id; /* switch product id */
Guenter Roeckd1988932015-04-02 04:06:31 +0200401 int num_ports; /* number of switch ports */
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700402
403 /* hw bridging */
404
Vivien Didelot194fea72015-08-10 09:09:47 -0400405 DECLARE_BITMAP(fid_bitmap, VLAN_N_VID); /* FIDs 1 to 4095 available */
406 u16 fid[DSA_MAX_PORTS]; /* per (non-bridged) port FID */
407 u16 bridge_mask[DSA_MAX_PORTS]; /* br groups (indexed by FID) */
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700408
409 unsigned long port_state_update_mask;
410 u8 port_state[DSA_MAX_PORTS];
411
412 struct work_struct bridge_work;
Andrew Lunn87c8cef2015-06-20 18:42:28 +0200413
414 struct dentry *dbgfs;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000415};
416
417struct mv88e6xxx_hw_stat {
418 char string[ETH_GSTRING_LEN];
419 int sizeof_stat;
420 int reg;
421};
422
Andrew Lunn143a8302015-04-02 04:06:34 +0200423int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
Andrew Lunndbde9e62015-05-06 01:09:48 +0200424int mv88e6xxx_setup_ports(struct dsa_switch *ds);
Guenter Roeckacdaffc2015-03-26 18:36:28 -0700425int mv88e6xxx_setup_common(struct dsa_switch *ds);
Andrew Lunn54d792f2015-05-06 01:09:47 +0200426int mv88e6xxx_setup_global(struct dsa_switch *ds);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000427int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
428int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
429int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
Barry Grussling85686582013-01-08 16:05:56 +0000430 int reg, u16 val);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000431int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000432int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000433int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +0200434int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
435int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
436int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
437int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
438 u16 val);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000439void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
440int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
441int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
442 int regnum, u16 val);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000443void mv88e6xxx_poll_link(struct dsa_switch *ds);
Andrew Lunne413e7e2015-04-02 04:06:38 +0200444void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
445void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
446 uint64_t *data);
447int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
448int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700449int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
450void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
451 struct ethtool_regs *regs, void *_p);
Guenter Roeckc22995c2015-07-25 09:42:28 -0700452int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
453int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp);
454int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp);
455int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm);
Andrew Lunnf3044682015-02-14 19:17:50 +0100456int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
457int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
458int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
459int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
460 u16 val);
Guenter Roeck11b3b452015-03-06 22:23:51 -0800461int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
462int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
463 struct phy_device *phydev, struct ethtool_eee *e);
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700464int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
465int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
466int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
Vivien Didelotb8fee952015-08-13 12:52:19 -0400467int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *vid);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -0400468int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 vid);
469int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
470 bool untagged);
Vivien Didelot7dad08d2015-08-13 12:52:21 -0400471int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid);
Vivien Didelotb8fee952015-08-13 12:52:19 -0400472int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
473 unsigned long *ports, unsigned long *untagged);
David S. Millercdf09692015-08-11 12:00:37 -0700474int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
475 const unsigned char *addr, u16 vid);
476int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
477 const unsigned char *addr, u16 vid);
478int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
Vivien Didelot2a778e12015-08-10 09:09:49 -0400479 unsigned char *addr, u16 *vid, bool *is_static);
Andrew Lunn491435852015-04-02 04:06:35 +0200480int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
481int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
482 int reg, int val);
Guenter Roeckc22995c2015-07-25 09:42:28 -0700483
Ben Hutchings98e67302011-11-25 14:36:19 +0000484extern struct dsa_switch_driver mv88e6131_switch_driver;
485extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
Guenter Roeck3ad50cc2014-10-29 10:44:56 -0700486extern struct dsa_switch_driver mv88e6352_switch_driver;
Andrew Lunn42f27252014-09-12 23:58:44 +0200487extern struct dsa_switch_driver mv88e6171_switch_driver;
Ben Hutchings98e67302011-11-25 14:36:19 +0000488
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000489#define REG_READ(addr, reg) \
490 ({ \
491 int __ret; \
492 \
493 __ret = mv88e6xxx_reg_read(ds, addr, reg); \
494 if (__ret < 0) \
495 return __ret; \
496 __ret; \
497 })
498
499#define REG_WRITE(addr, reg, val) \
500 ({ \
501 int __ret; \
502 \
503 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
504 if (__ret < 0) \
505 return __ret; \
506 })
507
508
509
510#endif