| Arnd Bergmann | a734bbf | 2020-10-30 15:26:23 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 1993 Hamish Macdonald |
| 4 | * Copyright (C) 1999 D. Jeff Dionne |
| 5 | * Copyright (C) 2001 Georges Menie, Ken Desmet |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file COPYING in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
| 11 | #include <linux/init.h> |
| 12 | #include <asm/machdep.h> |
| 13 | #include <asm/MC68VZ328.h> |
| Greg Ungerer | 3f605ee | 2021-04-27 23:49:31 +1000 | [diff] [blame] | 14 | #include "screen.h" |
| Arnd Bergmann | a734bbf | 2020-10-30 15:26:23 +0100 | [diff] [blame] | 15 | |
| 16 | /***************************************************************************/ |
| 17 | /* Init Drangon Engine hardware */ |
| 18 | /***************************************************************************/ |
| 19 | |
| 20 | static void dragen2_reset(void) |
| 21 | { |
| 22 | local_irq_disable(); |
| 23 | |
| 24 | #ifdef CONFIG_INIT_LCD |
| 25 | PBDATA |= 0x20; /* disable CCFL light */ |
| 26 | PKDATA |= 0x4; /* disable LCD controller */ |
| 27 | LCKCON = 0; |
| 28 | #endif |
| 29 | |
| 30 | __asm__ __volatile__( |
| 31 | "reset\n\t" |
| 32 | "moveal #0x04000000, %a0\n\t" |
| 33 | "moveal 0(%a0), %sp\n\t" |
| 34 | "moveal 4(%a0), %a0\n\t" |
| 35 | "jmp (%a0)" |
| 36 | ); |
| 37 | } |
| 38 | |
| 39 | void __init init_dragen2(char *command, int size) |
| 40 | { |
| 41 | mach_reset = dragen2_reset; |
| 42 | |
| 43 | #ifdef CONFIG_DIRECT_IO_ACCESS |
| 44 | SCR = 0x10; /* allow user access to internal registers */ |
| 45 | #endif |
| 46 | |
| 47 | /* CSGB Init */ |
| 48 | CSGBB = 0x4000; |
| 49 | CSB = 0x1a1; |
| 50 | |
| 51 | /* CS8900 init */ |
| 52 | /* PK3: hardware sleep function pin, active low */ |
| 53 | PKSEL |= PK(3); /* select pin as I/O */ |
| 54 | PKDIR |= PK(3); /* select pin as output */ |
| 55 | PKDATA |= PK(3); /* set pin high */ |
| 56 | |
| 57 | /* PF5: hardware reset function pin, active high */ |
| 58 | PFSEL |= PF(5); /* select pin as I/O */ |
| 59 | PFDIR |= PF(5); /* select pin as output */ |
| 60 | PFDATA &= ~PF(5); /* set pin low */ |
| 61 | |
| 62 | /* cs8900 hardware reset */ |
| 63 | PFDATA |= PF(5); |
| 64 | { int i; for (i = 0; i < 32000; ++i); } |
| 65 | PFDATA &= ~PF(5); |
| 66 | |
| 67 | /* INT1 enable (cs8900 IRQ) */ |
| 68 | PDPOL &= ~PD(1); /* active high signal */ |
| 69 | PDIQEG &= ~PD(1); |
| 70 | PDIRQEN |= PD(1); /* IRQ enabled */ |
| 71 | |
| 72 | #ifdef CONFIG_INIT_LCD |
| 73 | /* initialize LCD controller */ |
| 74 | LSSA = (long) screen_bits; |
| 75 | LVPW = 0x14; |
| 76 | LXMAX = 0x140; |
| 77 | LYMAX = 0xef; |
| 78 | LRRA = 0; |
| 79 | LPXCD = 3; |
| 80 | LPICF = 0x08; |
| 81 | LPOLCF = 0; |
| 82 | LCKCON = 0x80; |
| 83 | PCPDEN = 0xff; |
| 84 | PCSEL = 0; |
| 85 | |
| 86 | /* Enable LCD controller */ |
| 87 | PKDIR |= 0x4; |
| 88 | PKSEL |= 0x4; |
| 89 | PKDATA &= ~0x4; |
| 90 | |
| 91 | /* Enable CCFL backlighting circuit */ |
| 92 | PBDIR |= 0x20; |
| 93 | PBSEL |= 0x20; |
| 94 | PBDATA &= ~0x20; |
| 95 | |
| 96 | /* contrast control register */ |
| 97 | PFDIR |= 0x1; |
| 98 | PFSEL &= ~0x1; |
| 99 | PWMR = 0x037F; |
| 100 | #endif |
| 101 | } |