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Serge Semin657a06d2020-03-23 22:53:56 +03001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare APB GPIO controller
8
9description: |
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
11 each of which are intended to be represented as child nodes with the generic
12 GPIO-controller properties as desribed in this bindings file.
13
14maintainers:
15 - Hoan Tran <hoan@os.amperecomputing.com>
Serge Seminc55812a2020-03-23 22:53:58 +030016 - Serge Semin <fancer.lancer@gmail.com>
Serge Semin657a06d2020-03-23 22:53:56 +030017
18properties:
19 $nodename:
20 pattern: "^gpio@[0-9a-f]+$"
21
22 compatible:
23 const: snps,dw-apb-gpio
24
25 "#address-cells":
26 const: 1
27
28 "#size-cells":
29 const: 0
30
31 reg:
32 maxItems: 1
33
34 clocks:
Serge Semin4f180932020-03-23 22:53:57 +030035 minItems: 1
Serge Semin657a06d2020-03-23 22:53:56 +030036 items:
37 - description: APB interface clock source
Serge Semin4f180932020-03-23 22:53:57 +030038 - description: DW GPIO debounce reference clock source
Serge Semin657a06d2020-03-23 22:53:56 +030039
40 clock-names:
Serge Semin4f180932020-03-23 22:53:57 +030041 minItems: 1
Serge Semin657a06d2020-03-23 22:53:56 +030042 items:
43 - const: bus
Serge Semin4f180932020-03-23 22:53:57 +030044 - const: db
Serge Semin657a06d2020-03-23 22:53:56 +030045
46 resets:
47 maxItems: 1
48
49patternProperties:
50 "^gpio-(port|controller)@[0-9a-f]+$":
51 type: object
52 properties:
53 compatible:
54 const: snps,dw-apb-gpio-port
55
56 reg:
57 maxItems: 1
58
59 gpio-controller: true
60
61 '#gpio-cells':
62 const: 2
63
64 snps,nr-gpios:
65 description: The number of GPIO pins exported by the port.
Rob Herring086e9072020-06-10 15:49:12 -060066 $ref: /schemas/types.yaml#/definitions/uint32
Serge Semin657a06d2020-03-23 22:53:56 +030067 default: 32
Rob Herring086e9072020-06-10 15:49:12 -060068 minimum: 1
69 maximum: 32
Serge Semin657a06d2020-03-23 22:53:56 +030070
71 interrupts:
72 description: |
73 The interrupts to the parent controller raised when GPIOs generate
74 the interrupts. If the controller provides one combined interrupt
75 for all GPIOs, specify a single interrupt. If the controller provides
76 one interrupt for each GPIO, provide a list of interrupts that
77 correspond to each of the GPIO pins.
78 minItems: 1
79 maxItems: 32
80
81 interrupt-controller: true
82
83 '#interrupt-cells':
84 const: 2
85
86 required:
87 - compatible
88 - reg
89 - gpio-controller
90 - '#gpio-cells'
91
92 dependencies:
93 interrupt-controller: [ interrupts ]
94
95 additionalProperties: false
96
97additionalProperties: false
98
99required:
100 - compatible
101 - reg
102 - "#address-cells"
103 - "#size-cells"
104
105examples:
106 - |
107 gpio: gpio@20000 {
108 compatible = "snps,dw-apb-gpio";
109 reg = <0x20000 0x1000>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 porta: gpio-port@0 {
114 compatible = "snps,dw-apb-gpio-port";
115 reg = <0>;
116 gpio-controller;
117 #gpio-cells = <2>;
118 snps,nr-gpios = <8>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 interrupt-parent = <&vic1>;
122 interrupts = <0>;
123 };
124
125 portb: gpio-port@1 {
126 compatible = "snps,dw-apb-gpio-port";
127 reg = <1>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 snps,nr-gpios = <8>;
131 };
132 };
133...