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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 8b6836d824702cacf68190982181f8ca3aff9c3e / . / drivers / net / dsa / mv88e6xxx / port.h
blob: 03382b66f80037dbf731178b3f6e1ee6c122db2a [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Vivien Didelot18abed22016-11-04 03:23:26 +0100[diff] [blame]2/*
3 * Marvell 88E6xxx Switch Port Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
Vivien Didelot4333d612017-03-28 15:10:36 -0400[diff] [blame]7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Vivien Didelot18abed22016-11-04 03:23:26 +0100[diff] [blame]9 */
10
11#ifndef _MV88E6XXX_PORT_H
12#define _MV88E6XXX_PORT_H
13
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -0400[diff] [blame]14#include "chip.h"
Vivien Didelot18abed22016-11-04 03:23:26 +0100[diff] [blame]15
Vivien Didelot5f83dc92017-06-12 12:37:33 -0400[diff] [blame]16/* Offset 0x00: Port Status Register */
17#define MV88E6XXX_PORT_STS 0x00
18#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
Rasmus Villemoesce91c452019-06-04 07:34:30 +0000[diff] [blame]22#define MV88E6250_PORT_STS_LINK 0x1000
23#define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
26#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00
27#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00
28#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00
29#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00
30#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00
31#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00
Vivien Didelot5f83dc92017-06-12 12:37:33 -0400[diff] [blame]32#define MV88E6XXX_PORT_STS_LINK 0x0800
33#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
34#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300
35#define MV88E6XXX_PORT_STS_SPEED_10 0x0000
36#define MV88E6XXX_PORT_STS_SPEED_100 0x0100
37#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200
Russell Kingc9a23562018-05-10 13:17:35 -0700[diff] [blame]38#define MV88E6XXX_PORT_STS_SPEED_10000 0x0300
Vivien Didelot5f83dc92017-06-12 12:37:33 -0400[diff] [blame]39#define MV88E6352_PORT_STS_EEE 0x0040
40#define MV88E6165_PORT_STS_AM_DIS 0x0040
41#define MV88E6185_PORT_STS_MGMII 0x0040
42#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020
43#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010
44#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f
Marek Behún927441a2019-08-14 16:40:24 +0200[diff] [blame]45#define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007
Marek Behún3bbb8862019-08-26 23:31:54 +0200[diff] [blame]46#define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008
47#define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009
Vivien Didelot5f83dc92017-06-12 12:37:33 -0400[diff] [blame]48#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a
49#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b
50#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c
51#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]52#define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c
53#define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d
54#define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e
Russell King6c422e32018-08-09 15:38:39 +0200[diff] [blame]55#define MV88E6185_PORT_STS_CDUPLEX 0x0008
56#define MV88E6185_PORT_STS_CMODE_MASK 0x0007
57#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000
58#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001
59#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002
60#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003
61#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004
62#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005
63#define MV88E6185_PORT_STS_CMODE_PHY 0x0006
64#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007
Vivien Didelot5f83dc92017-06-12 12:37:33 -0400[diff] [blame]65
Vivien Didelot5ee55572017-06-12 12:37:34 -0400[diff] [blame]66/* Offset 0x01: MAC (or PCS or Physical) Control Register */
67#define MV88E6XXX_PORT_MAC_CTL 0x01
68#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000
69#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000
Russell King6c422e32018-08-09 15:38:39 +0200[diff] [blame]70#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000
Vivien Didelot5ee55572017-06-12 12:37:34 -0400[diff] [blame]71#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000
72#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000
73#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]74#define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200
75#define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100
Russell King6c422e32018-08-09 15:38:39 +0200[diff] [blame]76#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400
77#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200
78#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100
Vivien Didelot5ee55572017-06-12 12:37:34 -0400[diff] [blame]79#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080
80#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040
81#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020
82#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010
83#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008
84#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004
85#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003
86#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000
87#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001
88#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002
89#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002
90#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003
91#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003
92
Vivien Didelot6c96bbf2017-06-12 12:37:35 -0400[diff] [blame]93/* Offset 0x02: Jamming Control Register */
94#define MV88E6097_PORT_JAM_CTL 0x02
95#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00
96#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff
97
98/* Offset 0x02: Flow Control Register */
99#define MV88E6390_PORT_FLOW_CTL 0x02
100#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000
101#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00
102#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000
103#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100
104#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff
105
Vivien Didelot107fcc12017-06-12 12:37:36 -0400[diff] [blame]106/* Offset 0x03: Switch Identifier Register */
107#define MV88E6XXX_PORT_SWITCH_ID 0x03
108#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0
109#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0
110#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950
111#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990
112#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00
113#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10
114#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060
115#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150
116#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210
117#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610
118#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650
119#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710
120#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720
121#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750
122#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760
123#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900
124#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]125#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920
126#define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930
Vivien Didelot107fcc12017-06-12 12:37:36 -0400[diff] [blame]127#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70
Hubert Feurstein49022642019-07-31 10:23:46 +0200[diff] [blame]128#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
Vivien Didelot107fcc12017-06-12 12:37:36 -0400[diff] [blame]129#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000[diff] [blame]130#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
Vivien Didelot107fcc12017-06-12 12:37:36 -0400[diff] [blame]131#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
132#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
133#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400
134#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410
135#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520
136#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710
137#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750
138#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]139#define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930
Vivien Didelot107fcc12017-06-12 12:37:36 -0400[diff] [blame]140#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f
141
Vivien Didelota89b433be2017-06-12 12:37:37 -0400[diff] [blame]142/* Offset 0x04: Port Control Register */
143#define MV88E6XXX_PORT_CTL0 0x04
144#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000
145#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000
146#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000
147#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000
148#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000
149#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000
150#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000
151#define MV88E6XXX_PORT_CTL0_HEADER 0x0800
152#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400
153#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200
154#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300
155#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000
156#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100
157#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200
158#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300
159#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100
160#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080
161#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040
162#define MV88E6185_PORT_CTL0_USE_IP 0x0020
163#define MV88E6185_PORT_CTL0_USE_TAG 0x0010
164#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004
Vladimir Olteana8b659e2021-02-12 17:15:56 +0200[diff] [blame]165#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004
166#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008
Vivien Didelota89b433be2017-06-12 12:37:37 -0400[diff] [blame]167#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003
168#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000
169#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001
170#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
171#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
172
Vivien Didelotcd985bb2017-06-12 12:37:38 -0400[diff] [blame]173/* Offset 0x05: Port Control 1 */
174#define MV88E6XXX_PORT_CTL1 0x05
175#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
Tobias Waldekranz57e661a2021-01-13 09:42:54 +0100[diff] [blame]176#define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000
177#define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00
178#define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8
Vivien Didelotcd985bb2017-06-12 12:37:38 -0400[diff] [blame]179#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
180
Vivien Didelot7e5cc5f2017-06-12 12:37:39 -0400[diff] [blame]181/* Offset 0x06: Port Based VLAN Map */
182#define MV88E6XXX_PORT_BASE_VLAN 0x06
183#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
184
Vivien Didelotb7929fb2017-06-12 12:37:40 -0400[diff] [blame]185/* Offset 0x07: Default Port VLAN ID & Priority */
186#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
187#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
188
Vivien Didelot81c6edb2017-06-12 12:37:41 -0400[diff] [blame]189/* Offset 0x08: Port Control 2 Register */
190#define MV88E6XXX_PORT_CTL2 0x08
191#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000
192#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000
193#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000
194#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000
195#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000
196#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000
197#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000
198#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000
199#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00
200#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000
201#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400
202#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800
203#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00
204#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200
205#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100
206#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080
207#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040
208#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020
209#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
210#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
211
Vivien Didelot2cb8cb12017-06-12 12:37:42 -0400[diff] [blame]212/* Offset 0x09: Egress Rate Control */
213#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09
214
215/* Offset 0x0A: Egress Rate Control 2 */
216#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
217
Vivien Didelot2a4614e2017-06-12 12:37:43 -0400[diff] [blame]218/* Offset 0x0B: Port Association Vector */
219#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
220#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000
221#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000
222#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000
223#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000
224#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800
225
Vivien Didelotb8109592017-06-12 12:37:45 -0400[diff] [blame]226/* Offset 0x0C: Port ATU Control */
227#define MV88E6XXX_PORT_ATU_CTL 0x0c
228
229/* Offset 0x0D: Priority Override Register */
230#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d
231
232/* Offset 0x0E: Policy Control Register */
Vivien Didelotf3a2cd32019-09-07 16:00:48 -0400[diff] [blame]233#define MV88E6XXX_PORT_POLICY_CTL 0x0e
234#define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000
235#define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000
236#define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00
237#define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300
238#define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0
239#define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030
240#define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c
241#define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003
242#define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000
243#define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001
244#define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002
245#define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003
Vivien Didelotb8109592017-06-12 12:37:45 -0400[diff] [blame]246
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]247/* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */
248#define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e
249#define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000
250#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00
251#define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff
252#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000
253#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100
254#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400
255#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500
256#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000
257#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800
258#define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0
259
Vivien Didelotb8109592017-06-12 12:37:45 -0400[diff] [blame]260/* Offset 0x0F: Port Special Ether Type */
261#define MV88E6XXX_PORT_ETH_TYPE 0x0f
262#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
263
264/* Offset 0x10: InDiscards Low Counter */
265#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10
266
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]267/* Offset 0x10: Extended Port Control Command */
268#define MV88E6393X_PORT_EPC_CMD 0x10
269#define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000
270#define MV88E6393X_PORT_EPC_CMD_WRITE 0x0300
271#define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02
272
273/* Offset 0x11: Extended Port Control Data */
274#define MV88E6393X_PORT_EPC_DATA 0x11
275
Vivien Didelotb8109592017-06-12 12:37:45 -0400[diff] [blame]276/* Offset 0x11: InDiscards High Counter */
277#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11
278
279/* Offset 0x12: InFiltered Counter */
280#define MV88E6XXX_PORT_IN_FILTERED 0x12
281
282/* Offset 0x13: OutFiltered Counter */
283#define MV88E6XXX_PORT_OUT_FILTERED 0x13
284
Vivien Didelot8009df92017-06-12 12:37:44 -0400[diff] [blame]285/* Offset 0x18: IEEE Priority Mapping Table */
286#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18
287#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000
Vivien Didelotddcbabf2017-06-17 23:07:14 -0400[diff] [blame]288#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000
Vivien Didelot8009df92017-06-12 12:37:44 -0400[diff] [blame]289#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000
290#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000
291#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000
292#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000
293#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000
294#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000
295#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000
Vivien Didelotddcbabf2017-06-17 23:07:14 -0400[diff] [blame]296#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00
297#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff
Vivien Didelot8009df92017-06-12 12:37:44 -0400[diff] [blame]298
299/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
300#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18
301
302/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
303#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19
Vivien Didelotd2a160b2017-06-02 17:06:17 -0400[diff] [blame]304
Andrew Lunnea890982019-01-09 00:24:03 +0100[diff] [blame]305/* Offset 0x1a: Magic undocumented errata register */
Marek Behún60907012019-08-26 23:31:51 +0200[diff] [blame]306#define MV88E6XXX_PORT_RESERVED_1A 0x1a
307#define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000
308#define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000
309#define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000
310#define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5
311#define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10
312#define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04
313#define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05
Marek Behún7a3007d2019-08-26 23:31:55 +0200[diff] [blame]314#define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000
315#define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000
Andrew Lunnea890982019-01-09 00:24:03 +0100[diff] [blame]316
Vivien Didelot18abed22016-11-04 03:23:26 +0100[diff] [blame]317int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
318 u16 *val);
319int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
320 u16 val);
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]321int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
322 int bit, int val);
Vivien Didelot18abed22016-11-04 03:23:26 +0100[diff] [blame]323
Andrew Lunn54186b92018-08-09 15:38:37 +0200[diff] [blame]324int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
325 int pause);
Vivien Didelota0a0f622016-11-04 03:23:34 +0100[diff] [blame]326int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
327 phy_interface_t mode);
328int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
329 phy_interface_t mode);
330
Vivien Didelot08ef7f12016-11-04 03:23:32 +0100[diff] [blame]331int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
332
Chris Packham4efe76622020-11-24 17:34:37 +1300[diff] [blame]333int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
334int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
335
Russell Kingf365c6f2020-03-14 10:15:53 +0000[diff] [blame]336int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
337 int speed, int duplex);
338int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
339 int speed, int duplex);
340int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
341 int speed, int duplex);
342int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
343 int speed, int duplex);
344int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
345 int speed, int duplex);
346int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
347 int speed, int duplex);
348int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
349 int speed, int duplex);
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]350int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
351 int speed, int duplex);
Vivien Didelot96a2b402016-11-04 03:23:35 +0100[diff] [blame]352
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100[diff] [blame]353phy_interface_t mv88e6341_port_max_speed_mode(int port);
354phy_interface_t mv88e6390_port_max_speed_mode(int port);
355phy_interface_t mv88e6390x_port_max_speed_mode(int port);
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]356phy_interface_t mv88e6393x_port_max_speed_mode(int port);
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100[diff] [blame]357
Vivien Didelote28def332016-11-04 03:23:27 +0100[diff] [blame]358int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
359
Vivien Didelot5a7921f2016-11-04 03:23:28 +0100[diff] [blame]360int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
361
Vivien Didelotb4e48c52016-11-04 03:23:29 +0100[diff] [blame]362int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
363int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
364
Vivien Didelot77064f32016-11-04 03:23:30 +0100[diff] [blame]365int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
366int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
367
Vivien Didelot385a0992016-11-04 03:23:31 +0100[diff] [blame]368int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
369 u16 mode);
Andrew Lunnef0a7312016-12-03 04:35:16 +0100[diff] [blame]370int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
371int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn56995cb2016-12-03 04:35:19 +0100[diff] [blame]372int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
Vivien Didelot31bef4e2017-06-08 18:34:09 -0400[diff] [blame]373 enum mv88e6xxx_egress_mode mode);
Andrew Lunn56995cb2016-12-03 04:35:19 +0100[diff] [blame]374int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
375 enum mv88e6xxx_frame_mode mode);
376int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
377 enum mv88e6xxx_frame_mode mode);
Vladimir Olteana8b659e2021-02-12 17:15:56 +0200[diff] [blame]378int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
379 int port, bool unicast);
380int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
381 int port, bool multicast);
382int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
383 bool unicast);
384int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
385 bool multicast);
Vivien Didelotf3a2cd32019-09-07 16:00:48 -0400[diff] [blame]386int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
387 enum mv88e6xxx_policy_mapping mapping,
388 enum mv88e6xxx_policy_action action);
Marek Behún6584b262021-03-17 14:46:43 +0100[diff] [blame]389int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
390 enum mv88e6xxx_policy_mapping mapping,
391 enum mv88e6xxx_policy_action action);
Andrew Lunn56995cb2016-12-03 04:35:19 +0100[diff] [blame]392int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
393 u16 etype);
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]394int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
395 enum mv88e6xxx_egress_direction direction,
396 int port);
397int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
398 int upstream_port);
399int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
400int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
401 u16 etype);
Vivien Didelotea698f42017-03-11 16:12:50 -0500[diff] [blame]402int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
403 bool message_port);
Tobias Waldekranz57e661a2021-01-13 09:42:54 +0100[diff] [blame]404int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
405 bool trunk, u8 id);
Vivien Didelotcd782652017-06-08 18:34:13 -0400[diff] [blame]406int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
407 size_t size);
Andrew Lunnef70b112016-12-03 04:45:18 +0100[diff] [blame]408int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
409int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
Tobias Waldekranz041bd542021-03-18 20:25:39 +0100[diff] [blame]410int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
411 u16 pav);
Vivien Didelot08984322017-06-08 18:34:12 -0400[diff] [blame]412int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
413 u8 out);
414int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
415 u8 out);
Marek Behún7a3007d2019-08-26 23:31:55 +0200[diff] [blame]416int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
417 phy_interface_t mode);
Andrew Lunnfdc71ee2018-11-11 00:32:15 +0100[diff] [blame]418int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
419 phy_interface_t mode);
Andrew Lunnf39908d2017-02-04 20:02:50 +0100[diff] [blame]420int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
421 phy_interface_t mode);
Pavana Sharmade776d02021-03-17 14:46:42 +0100[diff] [blame]422int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
423 phy_interface_t mode);
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +0200[diff] [blame]424int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
425int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +0300[diff] [blame^]426int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
427 bool drop_untagged);
Andrew Lunna23b2962017-02-04 20:15:28 +0100[diff] [blame]428int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
429int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
430 int upstream_port);
Iwan R Timmerf0942e02019-11-07 22:11:14 +0100[diff] [blame]431int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
432 enum mv88e6xxx_egress_direction direction,
433 bool mirror);
Vivien Didelotc8c94892017-03-11 16:13:01 -0500[diff] [blame]434
435int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -0500[diff] [blame]436int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
Vivien Didelotc8c94892017-03-11 16:13:01 -0500[diff] [blame]437
Marek Behún60907012019-08-26 23:31:51 +0200[diff] [blame]438int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block,
439 int port, int reg, u16 val);
440int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip);
441int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,
442 int reg, u16 *val);
443
Vivien Didelot18abed22016-11-04 03:23:26 +0100[diff] [blame]444#endif /* _MV88E6XXX_PORT_H */