Zhiwu Song | 301c5d2 | 2015-05-20 08:50:33 +0000 | [diff] [blame] | 1 | * Clock and reset bindings for CSR atlas7 |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: Should be "sirf,atlas7-car" |
| 5 | - reg: Address and length of the register set |
| 6 | - #clock-cells: Should be <1> |
| 7 | - #reset-cells: Should be <1> |
| 8 | |
| 9 | The clock consumer should specify the desired clock by having the clock |
| 10 | ID in its "clocks" phandle cell. |
| 11 | The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c |
| 12 | |
| 13 | The reset consumer should specify the desired reset by having the reset |
| 14 | ID in its "reset" phandle cell. |
| 15 | The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c |
| 16 | |
| 17 | Examples: Clock and reset controller node: |
| 18 | |
| 19 | car: clock-controller@18620000 { |
| 20 | compatible = "sirf,atlas7-car"; |
| 21 | reg = <0x18620000 0x1000>; |
| 22 | #clock-cells = <1>; |
| 23 | #reset-cells = <1>; |
| 24 | }; |
| 25 | |
| 26 | Examples: Consumers using clock or reset: |
| 27 | |
| 28 | timer@10dc0000 { |
| 29 | compatible = "sirf,macro-tick"; |
| 30 | reg = <0x10dc0000 0x1000>; |
| 31 | clocks = <&car 54>; |
| 32 | interrupts = <0 0 0>, |
| 33 | <0 1 0>, |
| 34 | <0 2 0>, |
| 35 | <0 49 0>, |
| 36 | <0 50 0>, |
| 37 | <0 51 0>; |
| 38 | }; |
| 39 | |
| 40 | uart1: uart@18020000 { |
| 41 | cell-index = <1>; |
| 42 | compatible = "sirf,macro-uart"; |
| 43 | reg = <0x18020000 0x1000>; |
| 44 | clocks = <&clks 95>; |
| 45 | interrupts = <0 18 0>; |
| 46 | fifosize = <32>; |
| 47 | }; |
| 48 | |
| 49 | vpp@13110000 { |
| 50 | compatible = "sirf,prima2-vpp"; |
| 51 | reg = <0x13110000 0x10000>; |
| 52 | interrupts = <0 31 0>; |
| 53 | clocks = <&car 85>; |
| 54 | resets = <&car 29>; |
| 55 | }; |