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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 8837d9216f99048636fbb2c11347358e99e06181 / . / include / asm-powerpc / spu.h
blob: 6b2aea0f6f20331738a5ac82d653cceb3346c618 [file] [log] [blame]
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
Arnd Bergmann88ced032005-12-16 22:43:46 +0100[diff] [blame]25#ifdef __KERNEL__
26
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]27#include <linux/config.h>
28#include <linux/kref.h>
29#include <linux/workqueue.h>
30
31#define LS_ORDER (6) /* 256 kb */
32
33#define LS_SIZE (PAGE_SIZE << LS_ORDER)
Mark Nutter5473af02005-11-15 15:53:49 -0500[diff] [blame]34#define LS_ADDR_MASK (LS_SIZE - 1)
35
36#define MFC_PUT_CMD 0x20
37#define MFC_PUTS_CMD 0x28
38#define MFC_PUTR_CMD 0x30
39#define MFC_PUTF_CMD 0x22
40#define MFC_PUTB_CMD 0x21
41#define MFC_PUTFS_CMD 0x2A
42#define MFC_PUTBS_CMD 0x29
43#define MFC_PUTRF_CMD 0x32
44#define MFC_PUTRB_CMD 0x31
45#define MFC_PUTL_CMD 0x24
46#define MFC_PUTRL_CMD 0x34
47#define MFC_PUTLF_CMD 0x26
48#define MFC_PUTLB_CMD 0x25
49#define MFC_PUTRLF_CMD 0x36
50#define MFC_PUTRLB_CMD 0x35
51
52#define MFC_GET_CMD 0x40
53#define MFC_GETS_CMD 0x48
54#define MFC_GETF_CMD 0x42
55#define MFC_GETB_CMD 0x41
56#define MFC_GETFS_CMD 0x4A
57#define MFC_GETBS_CMD 0x49
58#define MFC_GETL_CMD 0x44
59#define MFC_GETLF_CMD 0x46
60#define MFC_GETLB_CMD 0x45
61
62#define MFC_SDCRT_CMD 0x80
63#define MFC_SDCRTST_CMD 0x81
64#define MFC_SDCRZ_CMD 0x89
65#define MFC_SDCRS_CMD 0x8D
66#define MFC_SDCRF_CMD 0x8F
67
68#define MFC_GETLLAR_CMD 0xD0
69#define MFC_PUTLLC_CMD 0xB4
70#define MFC_PUTLLUC_CMD 0xB0
71#define MFC_PUTQLLUC_CMD 0xB8
72#define MFC_SNDSIG_CMD 0xA0
73#define MFC_SNDSIGB_CMD 0xA1
74#define MFC_SNDSIGF_CMD 0xA2
75#define MFC_BARRIER_CMD 0xC0
76#define MFC_EIEIO_CMD 0xC8
77#define MFC_SYNC_CMD 0xCC
78
79#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
80#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
81#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
82#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
83#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
84#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
85#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
86#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
87
88#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
89
90/* Events for Channels 0-2 */
91#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
92#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
93#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
94#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
95#define MFC_DECREMENTER_EVENT 0x00000020
96#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
97#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
98#define MFC_SIGNAL_2_EVENT 0x00000100
99#define MFC_SIGNAL_1_EVENT 0x00000200
100#define MFC_LLR_LOST_EVENT 0x00000400
101#define MFC_PRIV_ATTN_EVENT 0x00000800
102#define MFC_MULTI_SRC_EVENT 0x00001000
103
104/* Flags indicating progress during context switch. */
Arnd Bergmann8837d922006-01-04 20:31:28 +0100[diff] [blame^]105#define SPU_CONTEXT_SWITCH_PENDING 0UL
106#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]107
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500[diff] [blame]108struct spu_context;
109struct spu_runqueue;
110
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]111struct spu {
112 char *name;
113 unsigned long local_store_phys;
114 u8 *local_store;
115 struct spu_problem __iomem *problem;
116 struct spu_priv1 __iomem *priv1;
117 struct spu_priv2 __iomem *priv2;
118 struct list_head list;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500[diff] [blame]119 struct list_head sched_list;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]120 int number;
121 u32 isrc;
122 u32 node;
Mark Nutter5473af02005-11-15 15:53:49 -0500[diff] [blame]123 u64 flags;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500[diff] [blame]124 u64 dar;
125 u64 dsisr;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]126 struct kref kref;
127 size_t ls_size;
128 unsigned int slb_replace;
129 struct mm_struct *mm;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500[diff] [blame]130 struct spu_context *ctx;
131 struct spu_runqueue *rq;
Arnd Bergmann2a911f02005-12-05 22:52:26 -0500[diff] [blame]132 unsigned long long timestamp;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500[diff] [blame]133 pid_t pid;
134 int prio;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]135 int class_0_pending;
136 spinlock_t register_lock;
137
138 u32 stop_code;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500[diff] [blame]139 void (* wbox_callback)(struct spu *spu);
140 void (* ibox_callback)(struct spu *spu);
Arnd Bergmann51104592005-12-05 22:52:25 -0500[diff] [blame]141 void (* stop_callback)(struct spu *spu);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]142
143 char irq_c0[8];
144 char irq_c1[8];
145 char irq_c2[8];
146};
147
148struct spu *spu_alloc(void);
149void spu_free(struct spu *spu);
Arnd Bergmann51104592005-12-05 22:52:25 -0500[diff] [blame]150int spu_irq_class_0_bottom(struct spu *spu);
151int spu_irq_class_1_bottom(struct spu *spu);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]152
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]153extern struct spufs_calls {
154 asmlinkage long (*create_thread)(const char __user *name,
155 unsigned int flags, mode_t mode);
156 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
157 __u32 __user *ustatus);
158 struct module *owner;
159} spufs_calls;
160
161#ifdef CONFIG_SPU_FS_MODULE
162int register_spu_syscalls(struct spufs_calls *calls);
163void unregister_spu_syscalls(struct spufs_calls *calls);
164#else
165static inline int register_spu_syscalls(struct spufs_calls *calls)
166{
167 return 0;
168}
169static inline void unregister_spu_syscalls(struct spufs_calls *calls)
170{
171}
172#endif /* MODULE */
173
174
175/*
176 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
177 */
178
179union mfc_tag_size_class_cmd {
180 struct {
181 u16 mfc_size;
182 u16 mfc_tag;
183 u8 pad;
184 u8 mfc_rclassid;
185 u16 mfc_cmd;
186 } u;
187 struct {
188 u32 mfc_size_tag32;
189 u32 mfc_class_cmd32;
190 } by32;
191 u64 all64;
192};
193
194struct mfc_cq_sr {
195 u64 mfc_cq_data0_RW;
196 u64 mfc_cq_data1_RW;
197 u64 mfc_cq_data2_RW;
198 u64 mfc_cq_data3_RW;
199};
200
201struct spu_problem {
202#define MS_SYNC_PENDING 1L
203 u64 spc_mssync_RW; /* 0x0000 */
204 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
205
206 /* DMA Area */
207 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
208 u32 mfc_lsa_W; /* 0x3004 */
209 u64 mfc_ea_W; /* 0x3008 */
210 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
211 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
212 u32 dma_qstatus_R; /* 0x3104 */
213 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
214 u32 dma_querytype_RW; /* 0x3204 */
215 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
216 u32 dma_querymask_RW; /* 0x321c */
217 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
218 u32 dma_tagstatus_R; /* 0x322c */
219#define DMA_TAGSTATUS_INTR_ANY 1u
220#define DMA_TAGSTATUS_INTR_ALL 2u
221 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
222
223 /* SPU Control Area */
224 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
225 u32 pu_mb_R; /* 0x4004 */
226 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
227 u32 spu_mb_W; /* 0x400c */
228 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
229 u32 mb_stat_R; /* 0x4014 */
230 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
231 u32 spu_runcntl_RW; /* 0x401c */
232#define SPU_RUNCNTL_STOP 0L
233#define SPU_RUNCNTL_RUNNABLE 1L
234 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
235 u32 spu_status_R; /* 0x4024 */
236#define SPU_STOP_STATUS_SHIFT 16
237#define SPU_STATUS_STOPPED 0x0
238#define SPU_STATUS_RUNNING 0x1
239#define SPU_STATUS_STOPPED_BY_STOP 0x2
240#define SPU_STATUS_STOPPED_BY_HALT 0x4
241#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
242#define SPU_STATUS_SINGLE_STEP 0x10
243#define SPU_STATUS_INVALID_INSTR 0x20
244#define SPU_STATUS_INVALID_CH 0x40
245#define SPU_STATUS_ISOLATED_STATE 0x80
246#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
247#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
248 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
249 u32 spu_spe_R; /* 0x402c */
250 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
251 u32 spu_npc_RW; /* 0x4034 */
252 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
253
254 /* Signal Notification Area */
255 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
256 u32 signal_notify1; /* 0x1400c */
257 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
258 u32 signal_notify2; /* 0x1c00c */
259} __attribute__ ((aligned(0x20000)));
260
261/* SPU Privilege 2 State Area */
262struct spu_priv2 {
263 /* MFC Registers */
264 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
265
266 /* SLB Management Registers */
267 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
268 u64 slb_index_W; /* 0x1108 */
269#define SLB_INDEX_MASK 0x7L
270 u64 slb_esid_RW; /* 0x1110 */
271 u64 slb_vsid_RW; /* 0x1118 */
272#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
273#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
274#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
275#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
276#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
277#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
278#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
279#define SLB_VSID_4K_PAGE (0x0 << 8)
280#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
281#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
282#define SLB_VSID_CLASS_MASK (0x1ull << 7)
283#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
284 u64 slb_invalidate_entry_W; /* 0x1120 */
285 u64 slb_invalidate_all_W; /* 0x1128 */
286 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
287
288 /* Context Save / Restore Area */
289 struct mfc_cq_sr spuq[16]; /* 0x2000 */
290 struct mfc_cq_sr puq[8]; /* 0x2200 */
291 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
292
293 /* MFC Control */
294 u64 mfc_control_RW; /* 0x3000 */
295#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
296#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
297#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
298#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
299#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
300#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
301#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
302#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
303#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
304#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
305#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
306#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
307#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
308#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
309#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
310#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
311#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
312#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
313#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
314#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
315#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
316#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
317 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
318
319 /* Interrupt Mailbox */
320 u64 puint_mb_R; /* 0x4000 */
321 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
322
323 /* SPU Control */
324 u64 spu_privcntl_RW; /* 0x4040 */
325#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
326#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
327#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
328#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
329#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
330#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
331#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
332#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
333 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
334 u64 spu_lslr_RW; /* 0x4058 */
335 u64 spu_chnlcntptr_RW; /* 0x4060 */
336 u64 spu_chnlcnt_RW; /* 0x4068 */
337 u64 spu_chnldata_RW; /* 0x4070 */
338 u64 spu_cfg_RW; /* 0x4078 */
339 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
340
341 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
342 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
343 u64 spu_tag_status_query_RW; /* 0x5008 */
344#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
345#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
346 u64 spu_cmd_buf1_RW; /* 0x5010 */
347#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
348#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
349 u64 spu_cmd_buf2_RW; /* 0x5018 */
350#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
351#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
352#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
353 u64 spu_atomic_status_RW; /* 0x5020 */
354} __attribute__ ((aligned(0x20000)));
355
356/* SPU Privilege 1 State Area */
357struct spu_priv1 {
358 /* Control and Configuration Area */
359 u64 mfc_sr1_RW; /* 0x000 */
360#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
361#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
362#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
363#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
364#define MFC_STATE1_RELOCATE_MASK 0x10ull
365#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
366 u64 mfc_lpid_RW; /* 0x008 */
367 u64 spu_idr_RW; /* 0x010 */
368 u64 mfc_vr_RO; /* 0x018 */
369#define MFC_VERSION_BITS (0xffff << 16)
370#define MFC_REVISION_BITS (0xffff)
371#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
372#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
373 u64 spu_vr_RO; /* 0x020 */
374#define SPU_VERSION_BITS (0xffff << 16)
375#define SPU_REVISION_BITS (0xffff)
376#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
377#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
378 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
379
380
381 /* Interrupt Area */
382 u64 int_mask_class0_RW; /* 0x100 */
383#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
384#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
385#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
386#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
387 u64 int_mask_class1_RW; /* 0x108 */
388#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
389#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
390#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
391#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
392 u64 int_mask_class2_RW; /* 0x110 */
393#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
394#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
395#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
396#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
397 u8 pad_0x118_0x140[0x28]; /* 0x118 */
398 u64 int_stat_class0_RW; /* 0x140 */
399 u64 int_stat_class1_RW; /* 0x148 */
400 u64 int_stat_class2_RW; /* 0x150 */
401 u8 pad_0x158_0x180[0x28]; /* 0x158 */
402 u64 int_route_RW; /* 0x180 */
403
404 /* Interrupt Routing */
405 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
406
407 /* Atomic Unit Control Area */
408 u64 mfc_atomic_flush_RW; /* 0x200 */
409#define mfc_atomic_flush_enable 0x1L
410 u8 pad_0x208_0x280[0x78]; /* 0x208 */
411 u64 resource_allocation_groupID_RW; /* 0x280 */
412 u64 resource_allocation_enable_RW; /* 0x288 */
413 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
414
415 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
416
417 u64 smf_sbi_signal_sel; /* 0x3c8 */
418#define smf_sbi_mask_lsb 56
419#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
420#define smf_sbi_mask (0x301LL << smf_sbi_shift)
421#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
422#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
423#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
424#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
425 u64 smf_ato_signal_sel; /* 0x3d0 */
426#define smf_ato_mask_lsb 35
427#define smf_ato_shift (63 - smf_ato_mask_lsb)
428#define smf_ato_mask (0x3LL << smf_ato_shift)
429#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
430#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
431 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
432
433 /* TLB Management Registers */
434 u64 mfc_sdr_RW; /* 0x400 */
435 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
436 u64 tlb_index_hint_RO; /* 0x500 */
437 u64 tlb_index_W; /* 0x508 */
438 u64 tlb_vpn_RW; /* 0x510 */
439 u64 tlb_rpn_RW; /* 0x518 */
440 u8 pad_0x520_0x540[0x20]; /* 0x520 */
441 u64 tlb_invalidate_entry_W; /* 0x540 */
442 u64 tlb_invalidate_all_W; /* 0x548 */
443 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
444
445 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
446 u64 smm_hid; /* 0x580 */
447#define PAGE_SIZE_MASK 0xf000000000000000ull
448#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
449 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
450
451 /* MFC Status/Control Area */
452 u64 mfc_accr_RW; /* 0x600 */
453#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
454#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
455#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
456#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
457 u8 pad_0x608_0x610[0x8]; /* 0x608 */
458 u64 mfc_dsisr_RW; /* 0x610 */
459#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
460#define MFC_DSISR_ACCESS_DENIED (1 << 27)
461#define MFC_DSISR_ATOMIC (1 << 26)
462#define MFC_DSISR_ACCESS_PUT (1 << 25)
463#define MFC_DSISR_ADDR_MATCH (1 << 22)
464#define MFC_DSISR_LS (1 << 17)
465#define MFC_DSISR_L (1 << 16)
466#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
467 u8 pad_0x618_0x620[0x8]; /* 0x618 */
468 u64 mfc_dar_RW; /* 0x620 */
469 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
470
471 /* Replacement Management Table (RMT) Area */
472 u64 rmt_index_RW; /* 0x700 */
473 u8 pad_0x708_0x710[0x8]; /* 0x708 */
474 u64 rmt_data1_RW; /* 0x710 */
475 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
476
477 /* Control/Configuration Registers */
478 u64 mfc_dsir_R; /* 0x800 */
479#define MFC_DSIR_Q (1 << 31)
480#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
481 u64 mfc_lsacr_RW; /* 0x808 */
482#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
483#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
484 u64 mfc_lscrr_R; /* 0x810 */
485#define MFC_LSCRR_Q (1 << 31)
486#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
487#define MFC_LSCRR_QI_SHIFT 32
488#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
489 u8 pad_0x818_0x820[0x8]; /* 0x818 */
490 u64 mfc_tclass_id_RW; /* 0x820 */
491#define MFC_TCLASS_ID_ENABLE (1L << 0L)
492#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
493#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
494#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
495#define MFC_TCLASS_QUOTA_2_SHIFT 8L
496#define MFC_TCLASS_QUOTA_1_SHIFT 16L
497#define MFC_TCLASS_QUOTA_0_SHIFT 24L
498#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
499#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
500#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
501 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
502
503 /* Real Mode Support Registers */
504 u64 mfc_rm_boundary; /* 0x900 */
505 u8 pad_0x908_0x938[0x30]; /* 0x908 */
506 u64 smf_dma_signal_sel; /* 0x938 */
507#define mfc_dma1_mask_lsb 41
508#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
509#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
510#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
511#define mfc_dma2_mask_lsb 43
512#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
513#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
514#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
515 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
516 u64 smm_signal_sel; /* 0xa38 */
517#define smm_sig_mask_lsb 12
518#define smm_sig_shift (63 - smm_sig_mask_lsb)
519#define smm_sig_mask (0x3LL << smm_sig_shift)
520#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
521#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
522 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
523
524 /* DMA Command Error Area */
525 u64 mfc_cer_R; /* 0xc00 */
526#define MFC_CER_Q (1 << 31)
527#define MFC_CER_SPU_QUEUE MFC_CER_Q
528 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
529
530 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
531 /* DMA Command Error Area */
532 u64 spu_ecc_cntl_RW; /* 0x1000 */
533#define SPU_ECC_CNTL_E (1ull << 0ull)
534#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
535#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
536#define SPU_ECC_CNTL_S (1ull << 1ull)
537#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
538#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
539#define SPU_ECC_CNTL_B (1ull << 2ull)
540#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
541#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
542#define SPU_ECC_CNTL_I_SHIFT 3ull
543#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
544#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
545#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
546#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
547#define SPU_ECC_CNTL_D (1ull << 5ull)
548#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
549#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
550 u64 spu_ecc_stat_RW; /* 0x1008 */
551#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
552#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
553#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
554#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
555#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
556#define SPU_ECC_DATA_ERROR (1ull << 5ul)
557#define SPU_ECC_DMA_ERROR (1ull << 6ul)
558#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
559 u64 spu_ecc_addr_RW; /* 0x1010 */
560 u64 spu_err_mask_RW; /* 0x1018 */
561#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
562#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
563 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
564
565 /* SPU Debug-Trace Bus (DTB) Selection Registers */
566 u64 spu_trig0_sel; /* 0x1028 */
567 u64 spu_trig1_sel; /* 0x1030 */
568 u64 spu_trig2_sel; /* 0x1038 */
569 u64 spu_trig3_sel; /* 0x1040 */
570 u64 spu_trace_sel; /* 0x1048 */
571#define spu_trace_sel_mask 0x1f1fLL
572#define spu_trace_sel_bus0_bits 0x1000LL
573#define spu_trace_sel_bus2_bits 0x0010LL
574 u64 spu_event0_sel; /* 0x1050 */
575 u64 spu_event1_sel; /* 0x1058 */
576 u64 spu_event2_sel; /* 0x1060 */
577 u64 spu_event3_sel; /* 0x1068 */
578 u64 spu_trace_cntl; /* 0x1070 */
579} __attribute__ ((aligned(0x2000)));
580
Arnd Bergmann88ced032005-12-16 22:43:46 +0100[diff] [blame]581#endif /* __KERNEL__ */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500[diff] [blame]582#endif