blob: 7909fa12fca2cd3c71815ad470f5f1ae85144def [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Andy Shevchenkoc558e392014-08-19 19:17:35 +03002/*
3 * Intel Low Power Subsystem PWM controller driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 *
7 * Derived from the original pwm-lpss.c
Andy Shevchenkoc558e392014-08-19 19:17:35 +03008 */
9
10#ifndef __PWM_LPSS_H
11#define __PWM_LPSS_H
12
13#include <linux/device.h>
14#include <linux/pwm.h>
15
Hans de Goede9dc419b2018-10-12 12:12:26 +020016#define MAX_PWMS 4
17
18struct pwm_lpss_chip {
19 struct pwm_chip chip;
20 void __iomem *regs;
21 const struct pwm_lpss_boardinfo *info;
22 u32 saved_ctrl[MAX_PWMS];
23};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030024
25struct pwm_lpss_boardinfo {
26 unsigned long clk_rate;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030027 unsigned int npwm;
qipeng.zha883e4d02015-11-17 17:20:15 +080028 unsigned long base_unit_bits;
Hans de Goedeb997e3e2017-04-06 14:54:01 +030029 bool bypass;
Hans de Goede47437652018-10-14 17:12:01 +020030 /*
31 * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
32 * messes with the PWM0 controllers state,
33 */
34 bool other_devices_aml_touches_pwm_regs;
Andy Shevchenkoc558e392014-08-19 19:17:35 +030035};
36
Andy Shevchenkoc558e392014-08-19 19:17:35 +030037struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
38 const struct pwm_lpss_boardinfo *info);
39int pwm_lpss_remove(struct pwm_lpss_chip *lpwm);
Hans de Goede1d375b52018-04-26 14:10:23 +020040int pwm_lpss_suspend(struct device *dev);
41int pwm_lpss_resume(struct device *dev);
Andy Shevchenkoc558e392014-08-19 19:17:35 +030042
43#endif /* __PWM_LPSS_H */