Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2007 David Airlie |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * David Airlie |
| 25 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 26 | |
Sam Ravnborg | f918312 | 2019-06-08 10:02:40 +0200 | [diff] [blame] | 27 | #include <linux/module.h> |
Thomas Zimmermann | 2ef7941 | 2019-12-03 11:04:02 +0100 | [diff] [blame] | 28 | #include <linux/pci.h> |
Sam Ravnborg | f918312 | 2019-06-08 10:02:40 +0200 | [diff] [blame] | 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/vga_switcheroo.h> |
| 32 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_crtc_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drm_fb_helper.h> |
Sam Ravnborg | f918312 | 2019-06-08 10:02:40 +0200 | [diff] [blame] | 36 | #include <drm/drm_fourcc.h> |
Sam Ravnborg | f918312 | 2019-06-08 10:02:40 +0200 | [diff] [blame] | 37 | #include <drm/radeon_drm.h> |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 38 | |
Sam Ravnborg | f918312 | 2019-06-08 10:02:40 +0200 | [diff] [blame] | 39 | #include "radeon.h" |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 40 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 41 | /* object hierarchy - |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 42 | * this contains a helper + a radeon fb |
| 43 | * the helper contains a pointer to radeon framebuffer baseclass. |
| 44 | */ |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 45 | struct radeon_fbdev { |
Daniel Vetter | 19d8a4e | 2019-03-26 14:20:03 +0100 | [diff] [blame] | 46 | struct drm_fb_helper helper; /* must be first */ |
Daniel Stone | 9a0f0c9 | 2018-03-30 15:11:37 +0100 | [diff] [blame] | 47 | struct drm_framebuffer fb; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 48 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 49 | }; |
| 50 | |
Alex Deucher | 5756b15 | 2016-08-31 17:29:51 -0400 | [diff] [blame] | 51 | static int |
| 52 | radeonfb_open(struct fb_info *info, int user) |
| 53 | { |
| 54 | struct radeon_fbdev *rfbdev = info->par; |
| 55 | struct radeon_device *rdev = rfbdev->rdev; |
| 56 | int ret = pm_runtime_get_sync(rdev->ddev->dev); |
Sergio Miguéns Iglesias | b5768a7 | 2021-08-04 13:20:53 +0200 | [diff] [blame] | 57 | |
Alex Deucher | 5756b15 | 2016-08-31 17:29:51 -0400 | [diff] [blame] | 58 | if (ret < 0 && ret != -EACCES) { |
| 59 | pm_runtime_mark_last_busy(rdev->ddev->dev); |
| 60 | pm_runtime_put_autosuspend(rdev->ddev->dev); |
| 61 | return ret; |
| 62 | } |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static int |
| 67 | radeonfb_release(struct fb_info *info, int user) |
| 68 | { |
| 69 | struct radeon_fbdev *rfbdev = info->par; |
| 70 | struct radeon_device *rdev = rfbdev->rdev; |
| 71 | |
| 72 | pm_runtime_mark_last_busy(rdev->ddev->dev); |
| 73 | pm_runtime_put_autosuspend(rdev->ddev->dev); |
| 74 | return 0; |
| 75 | } |
| 76 | |
Jani Nikula | b6ff753 | 2019-12-03 18:38:48 +0200 | [diff] [blame] | 77 | static const struct fb_ops radeonfb_ops = { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 78 | .owner = THIS_MODULE, |
Stefan Christ | 13be31f | 2016-11-14 00:03:21 +0100 | [diff] [blame] | 79 | DRM_FB_HELPER_DEFAULT_OPS, |
Alex Deucher | 5756b15 | 2016-08-31 17:29:51 -0400 | [diff] [blame] | 80 | .fb_open = radeonfb_open, |
| 81 | .fb_release = radeonfb_release, |
Archit Taneja | 0045005 | 2015-07-31 16:21:54 +0530 | [diff] [blame] | 82 | .fb_fillrect = drm_fb_helper_cfb_fillrect, |
| 83 | .fb_copyarea = drm_fb_helper_cfb_copyarea, |
| 84 | .fb_imageblit = drm_fb_helper_cfb_imageblit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 85 | }; |
| 86 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 87 | |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 88 | int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | { |
| 90 | int aligned = width; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 91 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 92 | int pitch_mask = 0; |
| 93 | |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 94 | switch (cpp) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 95 | case 1: |
| 96 | pitch_mask = align_large ? 255 : 127; |
| 97 | break; |
| 98 | case 2: |
| 99 | pitch_mask = align_large ? 127 : 31; |
| 100 | break; |
| 101 | case 3: |
| 102 | case 4: |
| 103 | pitch_mask = align_large ? 63 : 15; |
| 104 | break; |
| 105 | } |
| 106 | |
| 107 | aligned += pitch_mask; |
| 108 | aligned &= ~pitch_mask; |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 109 | return aligned * cpp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | } |
| 111 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 112 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 113 | { |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 114 | struct radeon_bo *rbo = gem_to_radeon_bo(gobj); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 115 | int ret; |
| 116 | |
| 117 | ret = radeon_bo_reserve(rbo, false); |
| 118 | if (likely(ret == 0)) { |
| 119 | radeon_bo_kunmap(rbo); |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 120 | radeon_bo_unpin(rbo); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 121 | radeon_bo_unreserve(rbo); |
| 122 | } |
Emil Velikov | f11fb66 | 2020-05-15 10:51:09 +0100 | [diff] [blame] | 123 | drm_gem_object_put(gobj); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 127 | struct drm_mode_fb_cmd2 *mode_cmd, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 128 | struct drm_gem_object **gobj_p) |
| 129 | { |
Maxime Ripard | 24c478e | 2019-05-16 12:31:49 +0200 | [diff] [blame] | 130 | const struct drm_format_info *info; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 131 | struct radeon_device *rdev = rfbdev->rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 132 | struct drm_gem_object *gobj = NULL; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 133 | struct radeon_bo *rbo = NULL; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 134 | bool fb_tiled = false; /* useful for testing */ |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 135 | u32 tiling_flags = 0; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 136 | int ret; |
| 137 | int aligned_size, size; |
Dave Airlie | e40b6fc | 2011-02-18 15:51:57 +1000 | [diff] [blame] | 138 | int height = mode_cmd->height; |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 139 | u32 cpp; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 140 | |
Maxime Ripard | 24c478e | 2019-05-16 12:31:49 +0200 | [diff] [blame] | 141 | info = drm_get_format_info(rdev->ddev, mode_cmd); |
Maxime Ripard | b0f986b | 2019-05-16 12:31:52 +0200 | [diff] [blame] | 142 | cpp = info->cpp[0]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 143 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 144 | /* need to align pitch with crtc limits */ |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 145 | mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, cpp, |
| 146 | fb_tiled); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 147 | |
Dave Airlie | e40b6fc | 2011-02-18 15:51:57 +1000 | [diff] [blame] | 148 | if (rdev->family >= CHIP_R600) |
| 149 | height = ALIGN(mode_cmd->height, 8); |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 150 | size = mode_cmd->pitches[0] * height; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | aligned_size = ALIGN(size, PAGE_SIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 152 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 153 | RADEON_GEM_DOMAIN_VRAM, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 154 | 0, true, &gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 155 | if (ret) { |
Joe Perches | 7ca8529 | 2017-02-28 04:55:52 -0800 | [diff] [blame] | 156 | pr_err("failed to allocate framebuffer (%d)\n", aligned_size); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 157 | return -ENOMEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 158 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 159 | rbo = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 161 | if (fb_tiled) |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 162 | tiling_flags = RADEON_TILING_MACRO; |
| 163 | |
| 164 | #ifdef __BIG_ENDIAN |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 165 | switch (cpp) { |
| 166 | case 4: |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 167 | tiling_flags |= RADEON_TILING_SWAP_32BIT; |
| 168 | break; |
Laurent Pinchart | 802aaf7 | 2016-10-18 01:41:18 +0300 | [diff] [blame] | 169 | case 2: |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 170 | tiling_flags |= RADEON_TILING_SWAP_16BIT; |
Nathan Chancellor | 3a6e410 | 2021-08-15 12:29:59 -0700 | [diff] [blame] | 171 | break; |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 172 | default: |
| 173 | break; |
| 174 | } |
| 175 | #endif |
| 176 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 177 | if (tiling_flags) { |
| 178 | ret = radeon_bo_set_tiling_flags(rbo, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 179 | tiling_flags | RADEON_TILING_SURFACE, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 180 | mode_cmd->pitches[0]); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 181 | if (ret) |
| 182 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); |
| 183 | } |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 184 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 185 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 186 | ret = radeon_bo_reserve(rbo, false); |
| 187 | if (unlikely(ret != 0)) |
| 188 | goto out_unref; |
Michel Dänzer | 0349af7 | 2012-03-14 17:12:42 +0100 | [diff] [blame] | 189 | /* Only 27 bit offset for legacy CRTC */ |
| 190 | ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, |
| 191 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, |
| 192 | NULL); |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 193 | if (ret) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 194 | radeon_bo_unreserve(rbo); |
| 195 | goto out_unref; |
| 196 | } |
| 197 | if (fb_tiled) |
| 198 | radeon_bo_check_tiling(rbo, 0, 0); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 199 | ret = radeon_bo_kmap(rbo, NULL); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 200 | radeon_bo_unreserve(rbo); |
Sergio Miguéns Iglesias | b5768a7 | 2021-08-04 13:20:53 +0200 | [diff] [blame] | 201 | if (ret) |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 202 | goto out_unref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 204 | *gobj_p = gobj; |
| 205 | return 0; |
| 206 | out_unref: |
| 207 | radeonfb_destroy_pinned_object(gobj); |
| 208 | *gobj_p = NULL; |
| 209 | return ret; |
| 210 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | |
Daniel Vetter | cd5428a | 2013-01-21 23:42:49 +0100 | [diff] [blame] | 212 | static int radeonfb_create(struct drm_fb_helper *helper, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 213 | struct drm_fb_helper_surface_size *sizes) |
| 214 | { |
Fabian Frederick | a1d0280 | 2014-09-14 18:40:16 +0200 | [diff] [blame] | 215 | struct radeon_fbdev *rfbdev = |
| 216 | container_of(helper, struct radeon_fbdev, helper); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 217 | struct radeon_device *rdev = rfbdev->rdev; |
| 218 | struct fb_info *info; |
| 219 | struct drm_framebuffer *fb = NULL; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 220 | struct drm_mode_fb_cmd2 mode_cmd; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 221 | struct drm_gem_object *gobj = NULL; |
| 222 | struct radeon_bo *rbo = NULL; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 223 | int ret; |
| 224 | unsigned long tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 226 | mode_cmd.width = sizes->surface_width; |
| 227 | mode_cmd.height = sizes->surface_height; |
| 228 | |
| 229 | /* avivo can't scanout real 24bpp */ |
| 230 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) |
| 231 | sizes->surface_bpp = 32; |
| 232 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 233 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, |
| 234 | sizes->surface_depth); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 235 | |
| 236 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 237 | if (ret) { |
| 238 | DRM_ERROR("failed to create fbcon object %d\n", ret); |
| 239 | return ret; |
| 240 | } |
| 241 | |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 242 | rbo = gem_to_radeon_bo(gobj); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 243 | |
| 244 | /* okay we have an object now allocate the framebuffer */ |
Archit Taneja | 0045005 | 2015-07-31 16:21:54 +0530 | [diff] [blame] | 245 | info = drm_fb_helper_alloc_fbi(helper); |
| 246 | if (IS_ERR(info)) { |
| 247 | ret = PTR_ERR(info); |
Daniel Vetter | da7bdda | 2017-02-07 17:16:03 +0100 | [diff] [blame] | 248 | goto out; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 249 | } |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 250 | |
Daniel Vetter | 8782c64 | 2018-11-27 18:34:24 +0100 | [diff] [blame] | 251 | /* radeon resume is fragile and needs a vt switch to help it along */ |
| 252 | info->skip_vt_switch = false; |
| 253 | |
Daniel Stone | 9a0f0c9 | 2018-03-30 15:11:37 +0100 | [diff] [blame] | 254 | ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->fb, &mode_cmd, gobj); |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 255 | if (ret) { |
Masanari Iida | 8b513d0 | 2013-05-21 23:13:12 +0900 | [diff] [blame] | 256 | DRM_ERROR("failed to initialize framebuffer %d\n", ret); |
Daniel Vetter | da7bdda | 2017-02-07 17:16:03 +0100 | [diff] [blame] | 257 | goto out; |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 258 | } |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 259 | |
Daniel Stone | 9a0f0c9 | 2018-03-30 15:11:37 +0100 | [diff] [blame] | 260 | fb = &rfbdev->fb; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 261 | |
| 262 | /* setup helper */ |
| 263 | rfbdev->helper.fb = fb; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 264 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 265 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
Dave Airlie | bf8e828 | 2009-08-17 10:20:47 +1000 | [diff] [blame] | 266 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 267 | info->fbops = &radeonfb_ops; |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 268 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 269 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 270 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 271 | info->fix.smem_len = radeon_bo_size(rbo); |
| 272 | info->screen_base = rbo->kptr; |
| 273 | info->screen_size = radeon_bo_size(rbo); |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 274 | |
Daniel Vetter | 19d8a4e | 2019-03-26 14:20:03 +0100 | [diff] [blame] | 275 | drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); |
Dave Airlie | ed8f0d9 | 2009-07-29 17:07:38 +1000 | [diff] [blame] | 276 | |
| 277 | /* setup aperture base/size for vesafb takeover */ |
Marcin Slusarz | 1471ca9 | 2010-05-16 17:27:03 +0200 | [diff] [blame] | 278 | info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; |
Dave Airlie | 68d3059 | 2010-12-20 10:54:48 +1000 | [diff] [blame] | 279 | info->apertures->ranges[0].size = rdev->mc.aper_size; |
Dave Airlie | ed8f0d9 | 2009-07-29 17:07:38 +1000 | [diff] [blame] | 280 | |
Sascha Hauer | fb2a99e | 2012-02-06 10:58:19 +0100 | [diff] [blame] | 281 | /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 282 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 283 | if (info->screen_base == NULL) { |
| 284 | ret = -ENOSPC; |
Daniel Vetter | da7bdda | 2017-02-07 17:16:03 +0100 | [diff] [blame] | 285 | goto out; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 286 | } |
| 287 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 288 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); |
| 289 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 290 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
Ville Syrjälä | b00c600 | 2016-12-14 23:31:35 +0200 | [diff] [blame] | 291 | DRM_INFO("fb depth is %d\n", fb->format->depth); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 292 | DRM_INFO(" pitch is %d\n", fb->pitches[0]); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 293 | |
Thomas Zimmermann | d86a412 | 2020-12-01 11:35:38 +0100 | [diff] [blame] | 294 | vga_switcheroo_client_fb_set(rdev->pdev, info); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 295 | return 0; |
| 296 | |
Daniel Vetter | da7bdda | 2017-02-07 17:16:03 +0100 | [diff] [blame] | 297 | out: |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 298 | if (fb && ret) { |
Emil Velikov | f11fb66 | 2020-05-15 10:51:09 +0100 | [diff] [blame] | 299 | drm_gem_object_put(gobj); |
Daniel Vetter | 3620636 | 2012-12-10 20:42:17 +0100 | [diff] [blame] | 300 | drm_framebuffer_unregister_private(fb); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 301 | drm_framebuffer_cleanup(fb); |
| 302 | kfree(fb); |
| 303 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 304 | return ret; |
| 305 | } |
| 306 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 307 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 308 | { |
Daniel Stone | 9a0f0c9 | 2018-03-30 15:11:37 +0100 | [diff] [blame] | 309 | struct drm_framebuffer *fb = &rfbdev->fb; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | |
Archit Taneja | 0045005 | 2015-07-31 16:21:54 +0530 | [diff] [blame] | 311 | drm_fb_helper_unregister_fbi(&rfbdev->helper); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 312 | |
Daniel Stone | 9a0f0c9 | 2018-03-30 15:11:37 +0100 | [diff] [blame] | 313 | if (fb->obj[0]) { |
| 314 | radeonfb_destroy_pinned_object(fb->obj[0]); |
| 315 | fb->obj[0] = NULL; |
| 316 | drm_framebuffer_unregister_private(fb); |
| 317 | drm_framebuffer_cleanup(fb); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 318 | } |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 319 | drm_fb_helper_fini(&rfbdev->helper); |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 320 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | return 0; |
| 322 | } |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 323 | |
Thierry Reding | 3a49387 | 2014-06-27 17:19:23 +0200 | [diff] [blame] | 324 | static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
Daniel Vetter | cd5428a | 2013-01-21 23:42:49 +0100 | [diff] [blame] | 325 | .fb_probe = radeonfb_create, |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 326 | }; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 327 | |
| 328 | int radeon_fbdev_init(struct radeon_device *rdev) |
| 329 | { |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 330 | struct radeon_fbdev *rfbdev; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 331 | int bpp_sel = 32; |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 332 | int ret; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 333 | |
Alex Deucher | e5f243b | 2016-03-10 15:55:26 -0500 | [diff] [blame] | 334 | /* don't enable fbdev if no connectors */ |
| 335 | if (list_empty(&rdev->ddev->mode_config.connector_list)) |
| 336 | return 0; |
| 337 | |
Egbert Eich | 7b8bd6b | 2017-07-18 17:20:53 +0200 | [diff] [blame] | 338 | /* select 8 bpp console on 8MB cards, or 16 bpp on RN50 or 32MB */ |
| 339 | if (rdev->mc.real_vram_size <= (8*1024*1024)) |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 340 | bpp_sel = 8; |
Egbert Eich | 7b8bd6b | 2017-07-18 17:20:53 +0200 | [diff] [blame] | 341 | else if (ASIC_IS_RN50(rdev) || |
| 342 | rdev->mc.real_vram_size <= (32*1024*1024)) |
| 343 | bpp_sel = 16; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 344 | |
| 345 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); |
| 346 | if (!rfbdev) |
| 347 | return -ENOMEM; |
| 348 | |
| 349 | rfbdev->rdev = rdev; |
| 350 | rdev->mode_info.rfbdev = rfbdev; |
Thierry Reding | 10a2310 | 2014-06-27 17:19:24 +0200 | [diff] [blame] | 351 | |
| 352 | drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper, |
| 353 | &radeon_fb_helper_funcs); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 354 | |
Pankaj Bharadiya | 2dea2d1 | 2020-03-05 17:34:28 +0530 | [diff] [blame] | 355 | ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper); |
Thierry Reding | 01934c2 | 2014-12-19 11:21:32 +0100 | [diff] [blame] | 356 | if (ret) |
| 357 | goto free; |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 358 | |
Daniel Vetter | 76a39db | 2013-01-20 23:12:54 +0100 | [diff] [blame] | 359 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
| 360 | drm_helper_disable_unused_functions(rdev->ddev); |
| 361 | |
Thierry Reding | 01934c2 | 2014-12-19 11:21:32 +0100 | [diff] [blame] | 362 | ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); |
| 363 | if (ret) |
| 364 | goto fini; |
| 365 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 366 | return 0; |
Thierry Reding | 01934c2 | 2014-12-19 11:21:32 +0100 | [diff] [blame] | 367 | |
| 368 | fini: |
| 369 | drm_fb_helper_fini(&rfbdev->helper); |
| 370 | free: |
| 371 | kfree(rfbdev); |
| 372 | return ret; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | void radeon_fbdev_fini(struct radeon_device *rdev) |
| 376 | { |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 377 | if (!rdev->mode_info.rfbdev) |
| 378 | return; |
| 379 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 380 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 381 | kfree(rdev->mode_info.rfbdev); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 382 | rdev->mode_info.rfbdev = NULL; |
| 383 | } |
| 384 | |
| 385 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) |
| 386 | { |
Alex Deucher | e5f243b | 2016-03-10 15:55:26 -0500 | [diff] [blame] | 387 | if (rdev->mode_info.rfbdev) |
Daniel Vetter | 9db7d2b | 2016-08-10 18:52:37 +0200 | [diff] [blame] | 388 | drm_fb_helper_set_suspend(&rdev->mode_info.rfbdev->helper, state); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 389 | } |
| 390 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 391 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) |
| 392 | { |
Alex Deucher | e5f243b | 2016-03-10 15:55:26 -0500 | [diff] [blame] | 393 | if (!rdev->mode_info.rfbdev) |
| 394 | return false; |
| 395 | |
Daniel Stone | 9a0f0c9 | 2018-03-30 15:11:37 +0100 | [diff] [blame] | 396 | if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->fb.obj[0])) |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 397 | return true; |
| 398 | return false; |
| 399 | } |