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Srujana Challa5e8ce832021-01-15 19:22:19 +05301/* SPDX-License-Identifier: GPL-2.0-only
2 * Copyright (C) 2020 Marvell.
3 */
4
5#ifndef __OTX2_CPTPF_H
6#define __OTX2_CPTPF_H
7
Srujana Challa83ffcf72021-01-15 19:22:20 +05308#include "otx2_cpt_common.h"
9
Srujana Challa5e8ce832021-01-15 19:22:19 +053010struct otx2_cptpf_dev {
11 void __iomem *reg_base; /* CPT PF registers start address */
Srujana Challa83ffcf72021-01-15 19:22:20 +053012 void __iomem *afpf_mbox_base; /* PF-AF mbox start address */
Srujana Challa5e8ce832021-01-15 19:22:19 +053013 struct pci_dev *pdev; /* PCI device handle */
Srujana Challa83ffcf72021-01-15 19:22:20 +053014 /* AF <=> PF mbox */
15 struct otx2_mbox afpf_mbox;
16 struct work_struct afpf_mbox_work;
17 struct workqueue_struct *afpf_mbox_wq;
18
19 u8 pf_id; /* RVU PF number */
Srujana Challa5e8ce832021-01-15 19:22:19 +053020};
21
Srujana Challa83ffcf72021-01-15 19:22:20 +053022irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);
23void otx2_cptpf_afpf_mbox_handler(struct work_struct *work);
24
Srujana Challa5e8ce832021-01-15 19:22:19 +053025#endif /* __OTX2_CPTPF_H */