Srujana Challa | 5e8ce83 | 2021-01-15 19:22:19 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only |
| 2 | * Copyright (C) 2020 Marvell. |
| 3 | */ |
| 4 | |
| 5 | #ifndef __OTX2_CPTPF_H |
| 6 | #define __OTX2_CPTPF_H |
| 7 | |
Srujana Challa | 83ffcf7 | 2021-01-15 19:22:20 +0530 | [diff] [blame^] | 8 | #include "otx2_cpt_common.h" |
| 9 | |
Srujana Challa | 5e8ce83 | 2021-01-15 19:22:19 +0530 | [diff] [blame] | 10 | struct otx2_cptpf_dev { |
| 11 | void __iomem *reg_base; /* CPT PF registers start address */ |
Srujana Challa | 83ffcf7 | 2021-01-15 19:22:20 +0530 | [diff] [blame^] | 12 | void __iomem *afpf_mbox_base; /* PF-AF mbox start address */ |
Srujana Challa | 5e8ce83 | 2021-01-15 19:22:19 +0530 | [diff] [blame] | 13 | struct pci_dev *pdev; /* PCI device handle */ |
Srujana Challa | 83ffcf7 | 2021-01-15 19:22:20 +0530 | [diff] [blame^] | 14 | /* AF <=> PF mbox */ |
| 15 | struct otx2_mbox afpf_mbox; |
| 16 | struct work_struct afpf_mbox_work; |
| 17 | struct workqueue_struct *afpf_mbox_wq; |
| 18 | |
| 19 | u8 pf_id; /* RVU PF number */ |
Srujana Challa | 5e8ce83 | 2021-01-15 19:22:19 +0530 | [diff] [blame] | 20 | }; |
| 21 | |
Srujana Challa | 83ffcf7 | 2021-01-15 19:22:20 +0530 | [diff] [blame^] | 22 | irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg); |
| 23 | void otx2_cptpf_afpf_mbox_handler(struct work_struct *work); |
| 24 | |
Srujana Challa | 5e8ce83 | 2021-01-15 19:22:19 +0530 | [diff] [blame] | 25 | #endif /* __OTX2_CPTPF_H */ |