Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Watchdog driver for Renesas WDT watchdog |
| 3 | * |
| 4 | * Copyright (C) 2015-16 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> |
| 5 | * Copyright (C) 2015-16 Renesas Electronics Corporation |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | */ |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/clk.h> |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/pm_runtime.h> |
| 19 | #include <linux/watchdog.h> |
| 20 | |
| 21 | #define RWTCNT 0 |
| 22 | #define RWTCSRA 4 |
| 23 | #define RWTCSRA_WOVF BIT(4) |
| 24 | #define RWTCSRA_WRFLG BIT(5) |
| 25 | #define RWTCSRA_TME BIT(7) |
| 26 | |
| 27 | #define RWDT_DEFAULT_TIMEOUT 60U |
| 28 | |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 29 | /* |
| 30 | * In probe, clk_rate is checked to be not more than 16 bit * biggest clock |
| 31 | * divider (10 bits). d is only a factor to fully utilize the WDT counter and |
| 32 | * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits. |
| 33 | */ |
| 34 | #define MUL_BY_CLKS_PER_SEC(p, d) \ |
| 35 | DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks]) |
| 36 | |
| 37 | /* d is 16 bit, clk_divs 10 bit -> no 32 bit overflow */ |
| 38 | #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate) |
| 39 | |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 40 | static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024 }; |
| 41 | |
| 42 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 43 | module_param(nowayout, bool, 0); |
| 44 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
| 45 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 46 | |
| 47 | struct rwdt_priv { |
| 48 | void __iomem *base; |
| 49 | struct watchdog_device wdev; |
| 50 | struct clk *clk; |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 51 | unsigned long clk_rate; |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 52 | u8 cks; |
| 53 | }; |
| 54 | |
| 55 | static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg) |
| 56 | { |
| 57 | if (reg == RWTCNT) |
| 58 | val |= 0x5a5a0000; |
| 59 | else |
| 60 | val |= 0xa5a5a500; |
| 61 | |
| 62 | writel_relaxed(val, priv->base + reg); |
| 63 | } |
| 64 | |
| 65 | static int rwdt_init_timeout(struct watchdog_device *wdev) |
| 66 | { |
| 67 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
| 68 | |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 69 | rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int rwdt_start(struct watchdog_device *wdev) |
| 75 | { |
| 76 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
| 77 | |
| 78 | clk_prepare_enable(priv->clk); |
| 79 | |
| 80 | rwdt_write(priv, priv->cks, RWTCSRA); |
| 81 | rwdt_init_timeout(wdev); |
| 82 | |
| 83 | while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) |
| 84 | cpu_relax(); |
| 85 | |
| 86 | rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA); |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static int rwdt_stop(struct watchdog_device *wdev) |
| 92 | { |
| 93 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
| 94 | |
| 95 | rwdt_write(priv, priv->cks, RWTCSRA); |
| 96 | clk_disable_unprepare(priv->clk); |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev) |
| 102 | { |
| 103 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
| 104 | u16 val = readw_relaxed(priv->base + RWTCNT); |
| 105 | |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 106 | return DIV_BY_CLKS_PER_SEC(priv, 65536 - val); |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | static const struct watchdog_info rwdt_ident = { |
| 110 | .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, |
| 111 | .identity = "Renesas WDT Watchdog", |
| 112 | }; |
| 113 | |
| 114 | static const struct watchdog_ops rwdt_ops = { |
| 115 | .owner = THIS_MODULE, |
| 116 | .start = rwdt_start, |
| 117 | .stop = rwdt_stop, |
| 118 | .ping = rwdt_init_timeout, |
| 119 | .get_timeleft = rwdt_get_timeleft, |
| 120 | }; |
| 121 | |
| 122 | static int rwdt_probe(struct platform_device *pdev) |
| 123 | { |
| 124 | struct rwdt_priv *priv; |
| 125 | struct resource *res; |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 126 | unsigned long clks_per_sec; |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 127 | int ret, i; |
| 128 | |
| 129 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 130 | if (!priv) |
| 131 | return -ENOMEM; |
| 132 | |
| 133 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 134 | priv->base = devm_ioremap_resource(&pdev->dev, res); |
| 135 | if (IS_ERR(priv->base)) |
| 136 | return PTR_ERR(priv->base); |
| 137 | |
| 138 | priv->clk = devm_clk_get(&pdev->dev, NULL); |
| 139 | if (IS_ERR(priv->clk)) |
| 140 | return PTR_ERR(priv->clk); |
| 141 | |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 142 | priv->clk_rate = clk_get_rate(priv->clk); |
| 143 | if (!priv->clk_rate) |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 144 | return -ENOENT; |
| 145 | |
| 146 | for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) { |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 147 | clks_per_sec = priv->clk_rate / clk_divs[i]; |
Wolfram Sang | b51247c | 2017-07-19 10:27:52 +0200 | [diff] [blame] | 148 | if (clks_per_sec && clks_per_sec < 65536) { |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 149 | priv->cks = i; |
| 150 | break; |
| 151 | } |
| 152 | } |
| 153 | |
Wolfram Sang | b51247c | 2017-07-19 10:27:52 +0200 | [diff] [blame] | 154 | if (i < 0) { |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 155 | dev_err(&pdev->dev, "Can't find suitable clock divider\n"); |
| 156 | return -ERANGE; |
| 157 | } |
| 158 | |
| 159 | pm_runtime_enable(&pdev->dev); |
| 160 | pm_runtime_get_sync(&pdev->dev); |
| 161 | |
| 162 | priv->wdev.info = &rwdt_ident, |
| 163 | priv->wdev.ops = &rwdt_ops, |
| 164 | priv->wdev.parent = &pdev->dev; |
| 165 | priv->wdev.min_timeout = 1; |
Wolfram Sang | 82f64cd | 2017-07-19 10:27:54 +0200 | [diff] [blame^] | 166 | priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536); |
Wolfram Sang | bd99b68 | 2016-04-01 13:56:23 +0200 | [diff] [blame] | 167 | priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT); |
| 168 | |
| 169 | platform_set_drvdata(pdev, priv); |
| 170 | watchdog_set_drvdata(&priv->wdev, priv); |
| 171 | watchdog_set_nowayout(&priv->wdev, nowayout); |
| 172 | |
| 173 | /* This overrides the default timeout only if DT configuration was found */ |
| 174 | ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev); |
| 175 | if (ret) |
| 176 | dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n"); |
| 177 | |
| 178 | ret = watchdog_register_device(&priv->wdev); |
| 179 | if (ret < 0) { |
| 180 | pm_runtime_put(&pdev->dev); |
| 181 | pm_runtime_disable(&pdev->dev); |
| 182 | return ret; |
| 183 | } |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | static int rwdt_remove(struct platform_device *pdev) |
| 189 | { |
| 190 | struct rwdt_priv *priv = platform_get_drvdata(pdev); |
| 191 | |
| 192 | watchdog_unregister_device(&priv->wdev); |
| 193 | pm_runtime_put(&pdev->dev); |
| 194 | pm_runtime_disable(&pdev->dev); |
| 195 | |
| 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP |
| 201 | * to work there, one also needs a RESET (RST) driver which does not exist yet |
| 202 | * due to HW issues. This needs to be solved before adding compatibles here. |
| 203 | */ |
| 204 | static const struct of_device_id rwdt_ids[] = { |
| 205 | { .compatible = "renesas,rcar-gen3-wdt", }, |
| 206 | { /* sentinel */ } |
| 207 | }; |
| 208 | MODULE_DEVICE_TABLE(of, rwdt_ids); |
| 209 | |
| 210 | static struct platform_driver rwdt_driver = { |
| 211 | .driver = { |
| 212 | .name = "renesas_wdt", |
| 213 | .of_match_table = rwdt_ids, |
| 214 | }, |
| 215 | .probe = rwdt_probe, |
| 216 | .remove = rwdt_remove, |
| 217 | }; |
| 218 | module_platform_driver(rwdt_driver); |
| 219 | |
| 220 | MODULE_DESCRIPTION("Renesas WDT Watchdog Driver"); |
| 221 | MODULE_LICENSE("GPL v2"); |
| 222 | MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>"); |