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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 82925e76db19112cad62066828c1db0bbb3f77e3 / . / include / asm-powerpc / immap_86xx.h
blob: c83d7ad16606a83ae8ffe4de8ee2cb07c1e27e20 [file] [log] [blame]
Timur Tabi82925e72007-07-25 12:30:33 -0500[diff] [blame^]1/**
Jon Loeliger6b543402006-06-17 17:52:51 -0500[diff] [blame]2 * MPC86xx Internal Memory Map
3 *
Timur Tabi82925e72007-07-25 12:30:33 -0500[diff] [blame^]4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
Jon Loeliger6b543402006-06-17 17:52:51 -0500[diff] [blame]6 *
Timur Tabi82925e72007-07-25 12:30:33 -0500[diff] [blame^]7 * Copyright 2004,2007 Freescale Semiconductor, Inc
Jon Loeliger6b543402006-06-17 17:52:51 -0500[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
Timur Tabi82925e72007-07-25 12:30:33 -0500[diff] [blame^]14 * This header file defines structures for various 86xx SOC devices that are
15 * used by multiple source files.
Jon Loeliger6b543402006-06-17 17:52:51 -0500[diff] [blame]16 */
17
18#ifndef __ASM_POWERPC_IMMAP_86XX_H__
19#define __ASM_POWERPC_IMMAP_86XX_H__
20#ifdef __KERNEL__
21
Jon Loeliger6b543402006-06-17 17:52:51 -0500[diff] [blame]22/* Global Utility Registers */
Timur Tabi82925e72007-07-25 12:30:33 -0500[diff] [blame^]23struct ccsr_guts {
24 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
25 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
26 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
27 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
28 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
29 u8 res1[0x20 - 0x14];
30 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
31 u8 res2[0x30 - 0x24];
32 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
33 u8 res3[0x40 - 0x34];
34 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
35 u8 res4[0x50 - 0x44];
36 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
37 u8 res5[0x60 - 0x54];
38 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
39 u8 res6[0x70 - 0x64];
40 __be32 devdisr; /* 0x.0070 - Device Disable Control */
41 u8 res7[0x80 - 0x74];
42 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
43 u8 res8[0x90 - 0x84];
44 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
45 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
46 u8 res9[0xA0 - 0x98];
47 __be32 pvr; /* 0x.00a0 - Processor Version Register */
48 __be32 svr; /* 0x.00a4 - System Version Register */
49 u8 res10[0xB0 - 0xA8];
50 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
51 u8 res11[0xB20 - 0xB4];
52 __be32 ddr1clkdr; /* 0x.0b20 - DDRC1 Clock Disable Register */
53 __be32 ddr2clkdr; /* 0x.0b24 - DDRC2 Clock Disable Register */
54 u8 res12[0xE00 - 0xB28];
55 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
56 u8 res13[0xF04 - 0xE04];
57 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
58 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
59 u8 res14[0xF40 - 0xF0C];
60 __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */
61 __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */
62};
Jon Loeliger6b543402006-06-17 17:52:51 -0500[diff] [blame]63
64#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
65#endif /* __KERNEL__ */