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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 816cabd8d472d2e1b7daad2838eb4ce5046f03bb / . / sound / soc / codecs / rt1305.c
blob: 84043068c0b7078c8db0896e94a8e24b28af6687 [file] [log] [blame]
Shuming Fan29bc6432018-03-29 20:05:14 +0800[diff] [blame]1/*
2 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
3 *
4 * Copyright 2018 Realtek Semiconductor Corp.
5 * Author: Shuming Fan <shumingf@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
Shuming Fan816cabd2018-04-17 10:08:02 +0800[diff] [blame^]17#include <linux/acpi.h>
Shuming Fan29bc6432018-03-29 20:05:14 +0800[diff] [blame]18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/regmap.h>
21#include <linux/of_gpio.h>
22#include <linux/platform_device.h>
23#include <linux/firmware.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include "rl6231.h"
33#include "rt1305.h"
34
35
36#define RT1305_PR_RANGE_BASE (0xff + 1)
37#define RT1305_PR_SPACING 0x100
38
39#define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
40
41
42static const struct regmap_range_cfg rt1305_ranges[] = {
43 {
44 .name = "PR",
45 .range_min = RT1305_PR_BASE,
46 .range_max = RT1305_PR_BASE + 0xff,
47 .selector_reg = RT1305_PRIV_INDEX,
48 .selector_mask = 0xff,
49 .selector_shift = 0x0,
50 .window_start = RT1305_PRIV_DATA,
51 .window_len = 0x1,
52 },
53};
54
55
56static const struct reg_sequence init_list[] = {
57
58 { RT1305_PR_BASE + 0xcf, 0x5548 },
59 { RT1305_PR_BASE + 0x5d, 0x0442 },
60 { RT1305_PR_BASE + 0xc1, 0x0320 },
61
62 { RT1305_POWER_STATUS, 0x0000 },
63
64 { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
65 { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
66 { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
67
68 { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
69 { RT1305_ADC_SET_3, 0x0219 },
70 { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
71
72};
73#define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
74
75struct rt1305_priv {
76 struct snd_soc_component *component;
77 struct regmap *regmap;
78
79 int sysclk;
80 int sysclk_src;
81 int lrck;
82 int bclk;
83 int master;
84
85 int pll_src;
86 int pll_in;
87 int pll_out;
88};
89
90static const struct reg_default rt1305_reg[] = {
91
92 { 0x04, 0x0400 },
93 { 0x05, 0x0880 },
94 { 0x06, 0x0000 },
95 { 0x07, 0x3100 },
96 { 0x08, 0x8000 },
97 { 0x09, 0x0000 },
98 { 0x0a, 0x087e },
99 { 0x0b, 0x0020 },
100 { 0x0c, 0x0802 },
101 { 0x0d, 0x0020 },
102 { 0x10, 0x1d1d },
103 { 0x11, 0x1d1d },
104 { 0x12, 0xffff },
105 { 0x14, 0x000c },
106 { 0x16, 0x1717 },
107 { 0x17, 0x4000 },
108 { 0x18, 0x0019 },
109 { 0x20, 0x0000 },
110 { 0x22, 0x0000 },
111 { 0x24, 0x0000 },
112 { 0x26, 0x0000 },
113 { 0x28, 0x0000 },
114 { 0x2a, 0x4000 },
115 { 0x2b, 0x3000 },
116 { 0x2d, 0x6000 },
117 { 0x2e, 0x0000 },
118 { 0x2f, 0x8000 },
119 { 0x32, 0x0000 },
120 { 0x39, 0x0001 },
121 { 0x3a, 0x0000 },
122 { 0x3b, 0x1020 },
123 { 0x3c, 0x0000 },
124 { 0x3d, 0x0000 },
125 { 0x3e, 0x4c00 },
126 { 0x3f, 0x3000 },
127 { 0x40, 0x000c },
128 { 0x42, 0x0400 },
129 { 0x46, 0xc22c },
130 { 0x47, 0x0000 },
131 { 0x4b, 0x0000 },
132 { 0x4c, 0x0300 },
133 { 0x4f, 0xf000 },
134 { 0x50, 0xc200 },
135 { 0x51, 0x1f1f },
136 { 0x52, 0x01f0 },
137 { 0x53, 0x407f },
138 { 0x54, 0xffff },
139 { 0x58, 0x4005 },
140 { 0x5e, 0x0000 },
141 { 0x5f, 0x0000 },
142 { 0x60, 0xee13 },
143 { 0x62, 0x0000 },
144 { 0x63, 0x5f5f },
145 { 0x64, 0x0040 },
146 { 0x65, 0x4000 },
147 { 0x66, 0x4004 },
148 { 0x67, 0x0306 },
149 { 0x68, 0x8c04 },
150 { 0x69, 0xe021 },
151 { 0x6a, 0x0000 },
152 { 0x6c, 0xaaaa },
153 { 0x70, 0x0333 },
154 { 0x71, 0x3330 },
155 { 0x72, 0x3333 },
156 { 0x73, 0x3300 },
157 { 0x74, 0x0000 },
158 { 0x75, 0x0000 },
159 { 0x76, 0x0000 },
160 { 0x7a, 0x0003 },
161 { 0x7c, 0x10ec },
162 { 0x7e, 0x6251 },
163 { 0x80, 0x0800 },
164 { 0x81, 0x4000 },
165 { 0x82, 0x0000 },
166 { 0x90, 0x7a01 },
167 { 0x91, 0x8431 },
168 { 0x92, 0x0180 },
169 { 0x93, 0x0000 },
170 { 0x94, 0x0000 },
171 { 0x95, 0x0000 },
172 { 0x96, 0x0000 },
173 { 0x97, 0x0000 },
174 { 0x98, 0x0000 },
175 { 0x99, 0x0000 },
176 { 0x9a, 0x0000 },
177 { 0x9b, 0x0000 },
178 { 0x9c, 0x0000 },
179 { 0x9d, 0x0000 },
180 { 0x9e, 0x0000 },
181 { 0x9f, 0x0000 },
182 { 0xa0, 0x0000 },
183 { 0xb0, 0x8200 },
184 { 0xb1, 0x00ff },
185 { 0xb2, 0x0008 },
186 { 0xc0, 0x0200 },
187 { 0xc1, 0x0000 },
188 { 0xc2, 0x0000 },
189 { 0xc3, 0x0000 },
190 { 0xc4, 0x0000 },
191 { 0xc5, 0x0000 },
192 { 0xc6, 0x0000 },
193 { 0xc7, 0x0000 },
194 { 0xc8, 0x0000 },
195 { 0xc9, 0x0000 },
196 { 0xca, 0x0200 },
197 { 0xcb, 0x0000 },
198 { 0xcc, 0x0000 },
199 { 0xcd, 0x0000 },
200 { 0xce, 0x0000 },
201 { 0xcf, 0x0000 },
202 { 0xd0, 0x0000 },
203 { 0xd1, 0x0000 },
204 { 0xd2, 0x0000 },
205 { 0xd3, 0x0000 },
206 { 0xd4, 0x0200 },
207 { 0xd5, 0x0000 },
208 { 0xd6, 0x0000 },
209 { 0xd7, 0x0000 },
210 { 0xd8, 0x0000 },
211 { 0xd9, 0x0000 },
212 { 0xda, 0x0000 },
213 { 0xdb, 0x0000 },
214 { 0xdc, 0x0000 },
215 { 0xdd, 0x0000 },
216 { 0xde, 0x0200 },
217 { 0xdf, 0x0000 },
218 { 0xe0, 0x0000 },
219 { 0xe1, 0x0000 },
220 { 0xe2, 0x0000 },
221 { 0xe3, 0x0000 },
222 { 0xe4, 0x0000 },
223 { 0xe5, 0x0000 },
224 { 0xe6, 0x0000 },
225 { 0xe7, 0x0000 },
226 { 0xe8, 0x0200 },
227 { 0xe9, 0x0000 },
228 { 0xea, 0x0000 },
229 { 0xeb, 0x0000 },
230 { 0xec, 0x0000 },
231 { 0xed, 0x0000 },
232 { 0xee, 0x0000 },
233 { 0xef, 0x0000 },
234 { 0xf0, 0x0000 },
235 { 0xf1, 0x0000 },
236 { 0xf2, 0x0200 },
237 { 0xf3, 0x0000 },
238 { 0xf4, 0x0000 },
239 { 0xf5, 0x0000 },
240 { 0xf6, 0x0000 },
241 { 0xf7, 0x0000 },
242 { 0xf8, 0x0000 },
243 { 0xf9, 0x0000 },
244 { 0xfa, 0x0000 },
245 { 0xfb, 0x0000 },
246};
247
248static int rt1305_reg_init(struct snd_soc_component *component)
249{
250 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
251
252 regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
253 return 0;
254}
255
256static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
257{
258 int i;
259
260 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
261 if (reg >= rt1305_ranges[i].range_min &&
262 reg <= rt1305_ranges[i].range_max) {
263 return true;
264 }
265 }
266
267 switch (reg) {
268 case RT1305_RESET:
269 case RT1305_SPDIF_IN_SET_1:
270 case RT1305_SPDIF_IN_SET_2:
271 case RT1305_SPDIF_IN_SET_3:
272 case RT1305_POWER_CTRL_2:
273 case RT1305_CLOCK_DETECT:
274 case RT1305_BIQUAD_SET_1:
275 case RT1305_BIQUAD_SET_2:
276 case RT1305_EQ_SET_2:
277 case RT1305_SPK_TEMP_PROTECTION_0:
278 case RT1305_SPK_TEMP_PROTECTION_2:
279 case RT1305_SPK_DC_DETECT_1:
280 case RT1305_SILENCE_DETECT:
281 case RT1305_VERSION_ID:
282 case RT1305_VENDOR_ID:
283 case RT1305_DEVICE_ID:
284 case RT1305_EFUSE_1:
285 case RT1305_EFUSE_3:
286 case RT1305_DC_CALIB_1:
287 case RT1305_DC_CALIB_3:
288 case RT1305_DAC_OFFSET_1:
289 case RT1305_DAC_OFFSET_2:
290 case RT1305_DAC_OFFSET_3:
291 case RT1305_DAC_OFFSET_4:
292 case RT1305_DAC_OFFSET_5:
293 case RT1305_DAC_OFFSET_6:
294 case RT1305_DAC_OFFSET_7:
295 case RT1305_DAC_OFFSET_8:
296 case RT1305_DAC_OFFSET_9:
297 case RT1305_DAC_OFFSET_10:
298 case RT1305_DAC_OFFSET_11:
299 case RT1305_TRIM_1:
300 case RT1305_TRIM_2:
301 return true;
302
303 default:
304 return false;
305 }
306}
307
308static bool rt1305_readable_register(struct device *dev, unsigned int reg)
309{
310 int i;
311
312 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
313 if (reg >= rt1305_ranges[i].range_min &&
314 reg <= rt1305_ranges[i].range_max) {
315 return true;
316 }
317 }
318
319 switch (reg) {
320 case RT1305_RESET:
321 case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
322 case RT1305_PLL0_1 ... RT1305_PLL1_2:
323 case RT1305_MIXER_CTRL_1:
324 case RT1305_MIXER_CTRL_2:
325 case RT1305_DAC_SET_1:
326 case RT1305_DAC_SET_2:
327 case RT1305_ADC_SET_1:
328 case RT1305_ADC_SET_2:
329 case RT1305_ADC_SET_3:
330 case RT1305_PATH_SET:
331 case RT1305_SPDIF_IN_SET_1:
332 case RT1305_SPDIF_IN_SET_2:
333 case RT1305_SPDIF_IN_SET_3:
334 case RT1305_SPDIF_OUT_SET_1:
335 case RT1305_SPDIF_OUT_SET_2:
336 case RT1305_SPDIF_OUT_SET_3:
337 case RT1305_I2S_SET_1:
338 case RT1305_I2S_SET_2:
339 case RT1305_PBTL_MONO_MODE_SRC:
340 case RT1305_MANUALLY_I2C_DEVICE:
341 case RT1305_POWER_STATUS:
342 case RT1305_POWER_CTRL_1:
343 case RT1305_POWER_CTRL_2:
344 case RT1305_POWER_CTRL_3:
345 case RT1305_POWER_CTRL_4:
346 case RT1305_POWER_CTRL_5:
347 case RT1305_CLOCK_DETECT:
348 case RT1305_BIQUAD_SET_1:
349 case RT1305_BIQUAD_SET_2:
350 case RT1305_ADJUSTED_HPF_1:
351 case RT1305_ADJUSTED_HPF_2:
352 case RT1305_EQ_SET_1:
353 case RT1305_EQ_SET_2:
354 case RT1305_SPK_TEMP_PROTECTION_0:
355 case RT1305_SPK_TEMP_PROTECTION_1:
356 case RT1305_SPK_TEMP_PROTECTION_2:
357 case RT1305_SPK_TEMP_PROTECTION_3:
358 case RT1305_SPK_DC_DETECT_1:
359 case RT1305_SPK_DC_DETECT_2:
360 case RT1305_LOUDNESS:
361 case RT1305_THERMAL_FOLD_BACK_1:
362 case RT1305_THERMAL_FOLD_BACK_2:
363 case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
364 case RT1305_VERSION_ID:
365 case RT1305_VENDOR_ID:
366 case RT1305_DEVICE_ID:
367 case RT1305_EFUSE_1:
368 case RT1305_EFUSE_2:
369 case RT1305_EFUSE_3:
370 case RT1305_DC_CALIB_1:
371 case RT1305_DC_CALIB_2:
372 case RT1305_DC_CALIB_3:
373 case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
374 case RT1305_TRIM_1:
375 case RT1305_TRIM_2:
376 case RT1305_TUNE_INTERNAL_OSC:
377 case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
378 return true;
379 default:
380 return false;
381 }
382}
383
384static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
385
386static const char * const rt1305_rx_data_ch_select[] = {
387 "LR",
388 "RL",
389 "Copy L",
390 "Copy R",
391};
392
393static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
394 rt1305_rx_data_ch_select);
395
396static void rt1305_reset(struct regmap *regmap)
397{
398 regmap_write(regmap, RT1305_RESET, 0);
399}
400
401static const struct snd_kcontrol_new rt1305_snd_controls[] = {
402 SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
403 8, 0, 0xff, 0, dac_vol_tlv),
404
405 /* I2S Data Channel Selection */
406 SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
407};
408
409static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
410 struct snd_soc_dapm_widget *sink)
411{
412 struct snd_soc_component *component =
413 snd_soc_dapm_to_component(source->dapm);
414 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
415 unsigned int val;
416
417 snd_soc_component_read(component, RT1305_CLK_1, &val);
418
419 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
420 (val & RT1305_SEL_PLL_SRC_2_RCCLK))
421 return 1;
422 else
423 return 0;
424}
425
426static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
427 struct snd_soc_dapm_widget *sink)
428{
429 struct snd_soc_component *component =
430 snd_soc_dapm_to_component(source->dapm);
431 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
432
433 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
434 return 1;
435 else
436 return 0;
437}
438
439static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
440 struct snd_kcontrol *kcontrol, int event)
441{
442 struct snd_soc_component *component =
443 snd_soc_dapm_to_component(w->dapm);
444
445 switch (event) {
446 case SND_SOC_DAPM_POST_PMU:
447 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
448 RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
449 break;
450 case SND_SOC_DAPM_PRE_PMD:
451 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
452 RT1305_POW_PDB_JD_MASK, 0);
453 usleep_range(150000, 200000);
454 break;
455
456 default:
457 return 0;
458 }
459
460 return 0;
461}
462
463static const struct snd_kcontrol_new rt1305_sto_dac_l =
464 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
465 RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
466
467static const struct snd_kcontrol_new rt1305_sto_dac_r =
468 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
469 RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
470
471static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
472 SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
473 RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
474 SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
475 RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
476 SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
477 RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
478 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
479 RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
480 SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
481 RT1305_POW_LDO2_BIT, 0, NULL, 0),
482 SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
483 RT1305_POW_BG2_BIT, 0, NULL, 0),
484 SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
485 RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
486 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
487 RT1305_POW_VREF_BIT, 0, NULL, 0),
488 SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
489 RT1305_POW_VREF1_BIT, 0, NULL, 0),
490 SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
491 RT1305_POW_VREF2_BIT, 0, NULL, 0),
492
493
494 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
495 RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
496 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
497 RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
498 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
499 RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
500 SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
501 RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
502 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
503 RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
504 SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
505 RT1305_POW_CLAMP_BIT, 0, NULL, 0),
506 SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
507 RT1305_POW_BUFL_BIT, 0, NULL, 0),
508 SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
509 RT1305_POW_BUFR_BIT, 0, NULL, 0),
510 SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
511 RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
512 SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
513 RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
514 SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
515 RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
516 SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
517 RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
518 SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
519 RT1305_POR_AVDD1_BIT, 0, NULL, 0),
520 SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
521 RT1305_POR_AVDD2_BIT, 0, NULL, 0),
522
523
524 SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
525 RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
526 SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
527 RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
528 SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
529 RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
530 SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
531 RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
532 SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
533 RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
534 SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
535 RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
536 SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
537 RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
538
539
540 /* Audio Interface */
541 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
542
543 /* Digital Interface */
544 SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
545 RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
546 SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
547 RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
548 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
549 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
550 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
551
552 /* Output Lines */
553 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
554 rt1305_classd_event,
555 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
556 SND_SOC_DAPM_OUTPUT("SPOL"),
557 SND_SOC_DAPM_OUTPUT("SPOR"),
558};
559
560static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
561
562 { "DAC", NULL, "AIF1RX" },
563
564 { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
565 { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
566
567 { "DAC", NULL, "MBIAS" },
568 { "DAC", NULL, "BG MBIAS" },
569 { "DAC", NULL, "LDO2" },
570 { "DAC", NULL, "BG2" },
571 { "DAC", NULL, "LDO2 IB2" },
572 { "DAC", NULL, "VREF" },
573 { "DAC", NULL, "VREF1" },
574 { "DAC", NULL, "VREF2" },
575
576 { "DAC", NULL, "DISC VREF" },
577 { "DAC", NULL, "FASTB VREF" },
578 { "DAC", NULL, "ULTRA FAST VREF" },
579 { "DAC", NULL, "CHOP DAC" },
580 { "DAC", NULL, "CKGEN DAC" },
581 { "DAC", NULL, "CLAMP" },
582 { "DAC", NULL, "CKGEN ADC" },
583 { "DAC", NULL, "TRIOSC" },
584 { "DAC", NULL, "AVDD1" },
585 { "DAC", NULL, "AVDD2" },
586
587 { "DAC", NULL, "POR AVDD1" },
588 { "DAC", NULL, "POR AVDD2" },
589 { "DAC", NULL, "VCM 6172" },
590
591 { "DAC L", "Switch", "DAC" },
592 { "DAC R", "Switch", "DAC" },
593
594 { "DAC R", NULL, "VSENSE R" },
595 { "DAC L", NULL, "VSENSE L" },
596 { "DAC R", NULL, "ISENSE R" },
597 { "DAC L", NULL, "ISENSE L" },
598 { "DAC L", NULL, "ADC3 L" },
599 { "DAC R", NULL, "ADC3 R" },
600 { "DAC L", NULL, "BUFL" },
601 { "DAC R", NULL, "BUFR" },
602 { "DAC L", NULL, "DAC L Power" },
603 { "DAC R", NULL, "DAC R Power" },
604
605 { "CLASS D", NULL, "DAC L" },
606 { "CLASS D", NULL, "DAC R" },
607
608 { "SPOL", NULL, "CLASS D" },
609 { "SPOR", NULL, "CLASS D" },
610};
611
612static int rt1305_get_clk_info(int sclk, int rate)
613{
614 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
615
616 if (sclk <= 0 || rate <= 0)
617 return -EINVAL;
618
619 rate = rate << 8;
620 for (i = 0; i < ARRAY_SIZE(pd); i++)
621 if (sclk == rate * pd[i])
622 return i;
623
624 return -EINVAL;
625}
626
627static int rt1305_hw_params(struct snd_pcm_substream *substream,
628 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
629{
630 struct snd_soc_component *component = dai->component;
631 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
632 unsigned int val_len = 0, val_clk, mask_clk;
633 int pre_div, bclk_ms, frame_size;
634
635 rt1305->lrck = params_rate(params);
636 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
637 if (pre_div < 0) {
638 dev_warn(component->dev, "Force using PLL ");
639 snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
640 rt1305->lrck * 64, rt1305->lrck * 256);
641 snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
642 rt1305->lrck * 256, SND_SOC_CLOCK_IN);
643 pre_div = 0;
644 }
645 frame_size = snd_soc_params_to_frame_size(params);
646 if (frame_size < 0) {
647 dev_err(component->dev, "Unsupported frame size: %d\n",
648 frame_size);
649 return -EINVAL;
650 }
651
652 bclk_ms = frame_size > 32;
653 rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
654
655 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
656 bclk_ms, pre_div, dai->id);
657
658 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
659 rt1305->lrck, pre_div, dai->id);
660
661 switch (params_width(params)) {
662 case 16:
663 val_len |= RT1305_I2S_DL_SEL_16B;
664 break;
665 case 20:
666 val_len |= RT1305_I2S_DL_SEL_20B;
667 break;
668 case 24:
669 val_len |= RT1305_I2S_DL_SEL_24B;
670 break;
671 case 8:
672 val_len |= RT1305_I2S_DL_SEL_8B;
673 break;
674 default:
675 return -EINVAL;
676 }
677
678 switch (dai->id) {
679 case RT1305_AIF1:
680 mask_clk = RT1305_DIV_FS_SYS_MASK;
681 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
682 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
683 RT1305_I2S_DL_SEL_MASK,
684 val_len);
685 break;
686 default:
687 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
688 return -EINVAL;
689 }
690
691 snd_soc_component_update_bits(component, RT1305_CLK_2,
692 mask_clk, val_clk);
693
694 return 0;
695}
696
697static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
698{
699 struct snd_soc_component *component = dai->component;
700 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
701 unsigned int reg_val = 0, reg1_val = 0;
702
703 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
704 case SND_SOC_DAIFMT_CBM_CFM:
705 reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
706 rt1305->master = 1;
707 break;
708 case SND_SOC_DAIFMT_CBS_CFS:
709 reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
710 rt1305->master = 0;
711 break;
712 default:
713 return -EINVAL;
714 }
715
716 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
717 case SND_SOC_DAIFMT_NB_NF:
718 break;
719 case SND_SOC_DAIFMT_IB_NF:
720 reg1_val |= RT1305_I2S_BCLK_INV;
721 break;
722 default:
723 return -EINVAL;
724 }
725
726 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
727 case SND_SOC_DAIFMT_I2S:
728 break;
729 case SND_SOC_DAIFMT_LEFT_J:
730 reg1_val |= RT1305_I2S_DF_SEL_LEFT;
731 break;
732 case SND_SOC_DAIFMT_DSP_A:
733 reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
734 break;
735 case SND_SOC_DAIFMT_DSP_B:
736 reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
737 break;
738 default:
739 return -EINVAL;
740 }
741
742 switch (dai->id) {
743 case RT1305_AIF1:
744 snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
745 RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
746 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
747 RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
748 reg1_val);
749 break;
750 default:
751 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
752 return -EINVAL;
753 }
754 return 0;
755}
756
757static int rt1305_set_component_sysclk(struct snd_soc_component *component,
758 int clk_id, int source, unsigned int freq, int dir)
759{
760 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
761 unsigned int reg_val = 0;
762
763 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
764 return 0;
765
766 switch (clk_id) {
767 case RT1305_FS_SYS_PRE_S_MCLK:
768 reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
769 snd_soc_component_update_bits(component,
770 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
771 RT1305_SEL_CLK_DET_SRC_MCLK);
772 break;
773 case RT1305_FS_SYS_PRE_S_PLL1:
774 reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
775 break;
776 case RT1305_FS_SYS_PRE_S_RCCLK:
777 reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
778 break;
779 default:
780 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
781 return -EINVAL;
782 }
783 snd_soc_component_update_bits(component, RT1305_CLK_1,
784 RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
785 rt1305->sysclk = freq;
786 rt1305->sysclk_src = clk_id;
787
788 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
789 freq, clk_id);
790
791 return 0;
792}
793
794static int rt1305_set_component_pll(struct snd_soc_component *component,
795 int pll_id, int source, unsigned int freq_in,
796 unsigned int freq_out)
797{
798 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
799 struct rl6231_pll_code pll_code;
800 int ret;
801
802 if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
803 freq_out == rt1305->pll_out)
804 return 0;
805
806 if (!freq_in || !freq_out) {
807 dev_dbg(component->dev, "PLL disabled\n");
808
809 rt1305->pll_in = 0;
810 rt1305->pll_out = 0;
811 snd_soc_component_update_bits(component, RT1305_CLK_1,
812 RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
813 RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
814 return 0;
815 }
816
817 switch (source) {
818 case RT1305_PLL2_S_MCLK:
819 snd_soc_component_update_bits(component, RT1305_CLK_1,
820 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
821 RT1305_DIV_PLL_SRC_2_MASK,
822 RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
823 snd_soc_component_update_bits(component,
824 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
825 RT1305_SEL_CLK_DET_SRC_MCLK);
826 break;
827 case RT1305_PLL1_S_BCLK:
828 snd_soc_component_update_bits(component,
829 RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
830 RT1305_SEL_PLL_SRC_1_BCLK);
831 break;
832 case RT1305_PLL2_S_RCCLK:
833 snd_soc_component_update_bits(component, RT1305_CLK_1,
834 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
835 RT1305_DIV_PLL_SRC_2_MASK,
836 RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
837 freq_in = 98304000;
838 break;
839 default:
840 dev_err(component->dev, "Unknown PLL Source %d\n", source);
841 return -EINVAL;
842 }
843
844 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
845 if (ret < 0) {
846 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
847 return ret;
848 }
849
850 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
851 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
852 pll_code.n_code, pll_code.k_code);
853
854 snd_soc_component_write(component, RT1305_PLL1_1,
855 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT |
856 pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT |
857 pll_code.n_code);
858 snd_soc_component_write(component, RT1305_PLL1_2,
859 pll_code.k_code);
860
861 rt1305->pll_in = freq_in;
862 rt1305->pll_out = freq_out;
863 rt1305->pll_src = source;
864
865 return 0;
866}
867
868static int rt1305_probe(struct snd_soc_component *component)
869{
870 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
871
872 rt1305->component = component;
873
874 /* initial settings */
875 rt1305_reg_init(component);
876
877 return 0;
878}
879
880static void rt1305_remove(struct snd_soc_component *component)
881{
882 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
883
884 rt1305_reset(rt1305->regmap);
885}
886
887#ifdef CONFIG_PM
888static int rt1305_suspend(struct snd_soc_component *component)
889{
890 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
891
892 regcache_cache_only(rt1305->regmap, true);
893 regcache_mark_dirty(rt1305->regmap);
894
895 return 0;
896}
897
898static int rt1305_resume(struct snd_soc_component *component)
899{
900 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
901
902 regcache_cache_only(rt1305->regmap, false);
903 regcache_sync(rt1305->regmap);
904
905 return 0;
906}
907#else
908#define rt1305_suspend NULL
909#define rt1305_resume NULL
910#endif
911
912#define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
913#define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
914 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
915 SNDRV_PCM_FMTBIT_S24_LE)
916
917static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
918 .hw_params = rt1305_hw_params,
919 .set_fmt = rt1305_set_dai_fmt,
920};
921
922static struct snd_soc_dai_driver rt1305_dai[] = {
923 {
924 .name = "rt1305-aif",
925 .playback = {
926 .stream_name = "AIF1 Playback",
927 .channels_min = 1,
928 .channels_max = 2,
929 .rates = RT1305_STEREO_RATES,
930 .formats = RT1305_FORMATS,
931 },
932 .ops = &rt1305_aif_dai_ops,
933 },
934};
935
936static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
937 .probe = rt1305_probe,
938 .remove = rt1305_remove,
939 .suspend = rt1305_suspend,
940 .resume = rt1305_resume,
941 .controls = rt1305_snd_controls,
942 .num_controls = ARRAY_SIZE(rt1305_snd_controls),
943 .dapm_widgets = rt1305_dapm_widgets,
944 .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
945 .dapm_routes = rt1305_dapm_routes,
946 .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
947 .set_sysclk = rt1305_set_component_sysclk,
948 .set_pll = rt1305_set_component_pll,
949 .use_pmdown_time = 1,
950 .endianness = 1,
951 .non_legacy_dai_naming = 1,
952};
953
954static const struct regmap_config rt1305_regmap = {
955 .reg_bits = 8,
956 .val_bits = 16,
957 .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
958 RT1305_PR_SPACING),
959 .volatile_reg = rt1305_volatile_register,
960 .readable_reg = rt1305_readable_register,
961 .cache_type = REGCACHE_RBTREE,
962 .reg_defaults = rt1305_reg,
963 .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
964 .ranges = rt1305_ranges,
965 .num_ranges = ARRAY_SIZE(rt1305_ranges),
966 .use_single_rw = true,
967};
968
969#if defined(CONFIG_OF)
970static const struct of_device_id rt1305_of_match[] = {
971 { .compatible = "realtek,rt1305", },
972 { .compatible = "realtek,rt1306", },
973 {},
974};
975MODULE_DEVICE_TABLE(of, rt1305_of_match);
976#endif
977
978#ifdef CONFIG_ACPI
979static struct acpi_device_id rt1305_acpi_match[] = {
980 {"10EC1305", 0,},
981 {"10EC1306", 0,},
982 {},
983};
984MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
985#endif
986
987static const struct i2c_device_id rt1305_i2c_id[] = {
988 { "rt1305", 0 },
989 { "rt1306", 0 },
990 { }
991};
992MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
993
994static void rt1305_calibrate(struct rt1305_priv *rt1305)
995{
996 unsigned int valmsb, vallsb, offsetl, offsetr;
997 unsigned int rh, rl, rhl, r0ohm;
998 u64 r0l, r0r;
999
1000 regcache_cache_bypass(rt1305->regmap, true);
1001
1002 rt1305_reset(rt1305->regmap);
1003 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1004 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1005 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1006 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1007 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1008 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1009 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1010 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1011 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1012
1013 /* Sin Gen */
1014 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1015
1016 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
1017 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
1018 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
1019 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1020 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
1021 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1022 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1023 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
1024 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1025 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1026 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1027
1028 /* EFUSE read */
1029 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1030 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1031 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1032 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1033 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1034 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1035 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
1036 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
1037
1038 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
1039 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
1040 offsetl = valmsb << 16 | vallsb;
1041 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
1042 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
1043 offsetr = valmsb << 16 | vallsb;
1044 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1045
1046 /* R0 calibration */
1047 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
1048 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1049 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1050 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
1051 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
1052 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
1053
1054 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
1055 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
1056 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
1057 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
1058 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1059 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1060 msleep(2000);
1061 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1062 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1063 rhl = (rh << 16) | rl;
1064 r0ohm = (rhl*10) / 33554432;
1065
1066 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1067 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1068
1069 r0l = 562949953421312;
1070 if (rhl != 0)
1071 do_div(r0l, rhl);
1072 pr_debug("Left_r0 = 0x%llx\n", r0l);
1073
1074 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
1075 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1076 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1077 msleep(2000);
1078 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1079 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1080 rhl = (rh << 16) | rl;
1081 r0ohm = (rhl*10) / 33554432;
1082
1083 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1084 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1085
1086 r0r = 562949953421312;
1087 if (rhl != 0)
1088 do_div(r0r, rhl);
1089 pr_debug("Right_r0 = 0x%llx\n", r0r);
1090
1091 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
1092
1093 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1094 (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1095 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
1096 (r0l >> 16) & 0xffff);
1097 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
1098 r0l & 0xffff);
1099 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
1100 ((r0r >> 16) & 0xffff) | 0xf800);
1101 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
1102 r0r & 0xffff);
1103 } else {
1104 pr_err("R0 calibration failed\n");
1105 }
1106
1107 /* restore some registers */
1108 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1109 usleep_range(200000, 400000);
1110 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1111 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
1112 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
1113 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
1114 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
1115 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
1116 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
1117
1118 regcache_cache_bypass(rt1305->regmap, false);
1119}
1120
1121static int rt1305_i2c_probe(struct i2c_client *i2c,
1122 const struct i2c_device_id *id)
1123{
1124 struct rt1305_priv *rt1305;
1125 int ret;
1126 unsigned int val;
1127
1128 rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
1129 GFP_KERNEL);
1130 if (rt1305 == NULL)
1131 return -ENOMEM;
1132
1133 i2c_set_clientdata(i2c, rt1305);
1134
1135 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1136 if (IS_ERR(rt1305->regmap)) {
1137 ret = PTR_ERR(rt1305->regmap);
1138 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1139 ret);
1140 return ret;
1141 }
1142
1143 regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
1144 if (val != RT1305_DEVICE_ID_NUM) {
1145 dev_err(&i2c->dev,
1146 "Device with ID register %x is not rt1305\n", val);
1147 return -ENODEV;
1148 }
1149
1150 rt1305_reset(rt1305->regmap);
1151 rt1305_calibrate(rt1305);
1152
1153 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt1305,
1154 rt1305_dai, ARRAY_SIZE(rt1305_dai));
1155}
1156
1157static int rt1305_i2c_remove(struct i2c_client *i2c)
1158{
1159 snd_soc_unregister_component(&i2c->dev);
1160
1161 return 0;
1162}
1163
1164static void rt1305_i2c_shutdown(struct i2c_client *client)
1165{
1166 struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1167
1168 rt1305_reset(rt1305->regmap);
1169}
1170
1171
1172static struct i2c_driver rt1305_i2c_driver = {
1173 .driver = {
1174 .name = "rt1305",
1175 .owner = THIS_MODULE,
1176#if defined(CONFIG_OF)
1177 .of_match_table = rt1305_of_match,
1178#endif
1179#if defined(CONFIG_ACPI)
1180 .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1181#endif
1182 },
1183 .probe = rt1305_i2c_probe,
1184 .remove = rt1305_i2c_remove,
1185 .shutdown = rt1305_i2c_shutdown,
1186 .id_table = rt1305_i2c_id,
1187};
1188module_i2c_driver(rt1305_i2c_driver);
1189
1190MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1191MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1192MODULE_LICENSE("GPL v2");