| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf561/bf561.h |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: |
| 7 | * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 |
| 8 | * |
| 9 | * Modified: |
| 10 | * Copyright 2004-2006 Analog Devices Inc. |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, see the file COPYING, or write |
| 26 | * to the Free Software Foundation, Inc., |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | |
| 30 | #ifndef __MACH_BF561_H__ |
| 31 | #define __MACH_BF561_H__ |
| 32 | |
| 33 | #define SUPPORTED_REVID 0x3 |
| 34 | |
| 35 | #define OFFSET_(x) ((x) & 0x0000FFFF) |
| 36 | #define L1_ISRAM 0xFFA00000 |
| 37 | #define L1_ISRAM_END 0xFFA04000 |
| 38 | #define DATA_BANKA_SRAM 0xFF800000 |
| 39 | #define DATA_BANKA_SRAM_END 0xFF804000 |
| 40 | #define DATA_BANKB_SRAM 0xFF900000 |
| 41 | #define DATA_BANKB_SRAM_END 0xFF904000 |
| 42 | #define L1_DSRAMA 0xFF800000 |
| 43 | #define L1_DSRAMA_END 0xFF804000 |
| 44 | #define L1_DSRAMB 0xFF900000 |
| 45 | #define L1_DSRAMB_END 0xFF904000 |
| 46 | #define L2_SRAM 0xFEB00000 |
| 47 | #define L2_SRAM_END 0xFEB20000 |
| 48 | #define AMB_FLASH 0x20000000 |
| 49 | #define AMB_FLASH_END 0x21000000 |
| 50 | #define AMB_FLASH_LENGTH 0x01000000 |
| 51 | #define L1_ISRAM_LENGTH 0x4000 |
| 52 | #define L1_DSRAMA_LENGTH 0x4000 |
| 53 | #define L1_DSRAMB_LENGTH 0x4000 |
| 54 | #define L2_SRAM_LENGTH 0x20000 |
| 55 | |
| 56 | /*some misc defines*/ |
| 57 | #define IMASK_IVG15 0x8000 |
| 58 | #define IMASK_IVG14 0x4000 |
| 59 | #define IMASK_IVG13 0x2000 |
| 60 | #define IMASK_IVG12 0x1000 |
| 61 | |
| 62 | #define IMASK_IVG11 0x0800 |
| 63 | #define IMASK_IVG10 0x0400 |
| 64 | #define IMASK_IVG9 0x0200 |
| 65 | #define IMASK_IVG8 0x0100 |
| 66 | |
| 67 | #define IMASK_IVG7 0x0080 |
| 68 | #define IMASK_IVGTMR 0x0040 |
| 69 | #define IMASK_IVGHW 0x0020 |
| 70 | |
| 71 | /*************************** |
| 72 | * Blackfin Cache setup |
| 73 | */ |
| 74 | |
| 75 | |
| 76 | #define BLKFIN_ISUBBANKS 4 |
| 77 | #define BLKFIN_IWAYS 4 |
| 78 | #define BLKFIN_ILINES 32 |
| 79 | |
| 80 | #define BLKFIN_DSUBBANKS 4 |
| 81 | #define BLKFIN_DWAYS 2 |
| 82 | #define BLKFIN_DLINES 64 |
| 83 | |
| 84 | #define WAY0_L 0x1 |
| 85 | #define WAY1_L 0x2 |
| 86 | #define WAY01_L 0x3 |
| 87 | #define WAY2_L 0x4 |
| 88 | #define WAY02_L 0x5 |
| 89 | #define WAY12_L 0x6 |
| 90 | #define WAY012_L 0x7 |
| 91 | |
| 92 | #define WAY3_L 0x8 |
| 93 | #define WAY03_L 0x9 |
| 94 | #define WAY13_L 0xA |
| 95 | #define WAY013_L 0xB |
| 96 | |
| 97 | #define WAY32_L 0xC |
| 98 | #define WAY320_L 0xD |
| 99 | #define WAY321_L 0xE |
| 100 | #define WAYALL_L 0xF |
| 101 | |
| 102 | #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ |
| 103 | |
| 104 | /* IAR0 BIT FIELDS */ |
| 105 | #define PLL_WAKEUP_BIT 0xFFFFFFFF |
| 106 | #define DMA1_ERROR_BIT 0xFFFFFF0F |
| 107 | #define DMA2_ERROR_BIT 0xFFFFF0FF |
| 108 | #define IMDMA_ERROR_BIT 0xFFFF0FFF |
| 109 | #define PPI1_ERROR_BIT 0xFFF0FFFF |
| 110 | #define PPI2_ERROR_BIT 0xFF0FFFFF |
| 111 | #define SPORT0_ERROR_BIT 0xF0FFFFFF |
| 112 | #define SPORT1_ERROR_BIT 0x0FFFFFFF |
| 113 | /* IAR1 BIT FIELDS */ |
| 114 | #define SPI_ERROR_BIT 0xFFFFFFFF |
| 115 | #define UART_ERROR_BIT 0xFFFFFF0F |
| 116 | #define RESERVED_ERROR_BIT 0xFFFFF0FF |
| 117 | #define DMA1_0_BIT 0xFFFF0FFF |
| 118 | #define DMA1_1_BIT 0xFFF0FFFF |
| 119 | #define DMA1_2_BIT 0xFF0FFFFF |
| 120 | #define DMA1_3_BIT 0xF0FFFFFF |
| 121 | #define DMA1_4_BIT 0x0FFFFFFF |
| 122 | /* IAR2 BIT FIELDS */ |
| 123 | #define DMA1_5_BIT 0xFFFFFFFF |
| 124 | #define DMA1_6_BIT 0xFFFFFF0F |
| 125 | #define DMA1_7_BIT 0xFFFFF0FF |
| 126 | #define DMA1_8_BIT 0xFFFF0FFF |
| 127 | #define DMA1_9_BIT 0xFFF0FFFF |
| 128 | #define DMA1_10_BIT 0xFF0FFFFF |
| 129 | #define DMA1_11_BIT 0xF0FFFFFF |
| 130 | #define DMA2_0_BIT 0x0FFFFFFF |
| 131 | /* IAR3 BIT FIELDS */ |
| 132 | #define DMA2_1_BIT 0xFFFFFFFF |
| 133 | #define DMA2_2_BIT 0xFFFFFF0F |
| 134 | #define DMA2_3_BIT 0xFFFFF0FF |
| 135 | #define DMA2_4_BIT 0xFFFF0FFF |
| 136 | #define DMA2_5_BIT 0xFFF0FFFF |
| 137 | #define DMA2_6_BIT 0xFF0FFFFF |
| 138 | #define DMA2_7_BIT 0xF0FFFFFF |
| 139 | #define DMA2_8_BIT 0x0FFFFFFF |
| 140 | /* IAR4 BIT FIELDS */ |
| 141 | #define DMA2_9_BIT 0xFFFFFFFF |
| 142 | #define DMA2_10_BIT 0xFFFFFF0F |
| 143 | #define DMA2_11_BIT 0xFFFFF0FF |
| 144 | #define TIMER0_BIT 0xFFFF0FFF |
| 145 | #define TIMER1_BIT 0xFFF0FFFF |
| 146 | #define TIMER2_BIT 0xFF0FFFFF |
| 147 | #define TIMER3_BIT 0xF0FFFFFF |
| 148 | #define TIMER4_BIT 0x0FFFFFFF |
| 149 | /* IAR5 BIT FIELDS */ |
| 150 | #define TIMER5_BIT 0xFFFFFFFF |
| 151 | #define TIMER6_BIT 0xFFFFFF0F |
| 152 | #define TIMER7_BIT 0xFFFFF0FF |
| 153 | #define TIMER8_BIT 0xFFFF0FFF |
| 154 | #define TIMER9_BIT 0xFFF0FFFF |
| 155 | #define TIMER10_BIT 0xFF0FFFFF |
| 156 | #define TIMER11_BIT 0xF0FFFFFF |
| 157 | #define PROG0_INTA_BIT 0x0FFFFFFF |
| 158 | /* IAR6 BIT FIELDS */ |
| 159 | #define PROG0_INTB_BIT 0xFFFFFFFF |
| 160 | #define PROG1_INTA_BIT 0xFFFFFF0F |
| 161 | #define PROG1_INTB_BIT 0xFFFFF0FF |
| 162 | #define PROG2_INTA_BIT 0xFFFF0FFF |
| 163 | #define PROG2_INTB_BIT 0xFFF0FFFF |
| 164 | #define DMA1_WRRD0_BIT 0xFF0FFFFF |
| 165 | #define DMA1_WRRD1_BIT 0xF0FFFFFF |
| 166 | #define DMA2_WRRD0_BIT 0x0FFFFFFF |
| 167 | /* IAR7 BIT FIELDS */ |
| 168 | #define DMA2_WRRD1_BIT 0xFFFFFFFF |
| 169 | #define IMDMA_WRRD0_BIT 0xFFFFFF0F |
| 170 | #define IMDMA_WRRD1_BIT 0xFFFFF0FF |
| 171 | #define WATCH_BIT 0xFFFF0FFF |
| 172 | #define RESERVED_1_BIT 0xFFF0FFFF |
| 173 | #define RESERVED_2_BIT 0xFF0FFFFF |
| 174 | #define SUPPLE_0_BIT 0xF0FFFFFF |
| 175 | #define SUPPLE_1_BIT 0x0FFFFFFF |
| 176 | |
| 177 | /* Miscellaneous Values */ |
| 178 | |
| 179 | /****************************** EBIU Settings ********************************/ |
| 180 | #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) |
| 181 | #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) |
| 182 | |
| 183 | #if defined(CONFIG_C_AMBEN_ALL) |
| 184 | #define V_AMBEN AMBEN_ALL |
| 185 | #elif defined(CONFIG_C_AMBEN) |
| 186 | #define V_AMBEN 0x0 |
| 187 | #elif defined(CONFIG_C_AMBEN_B0) |
| 188 | #define V_AMBEN AMBEN_B0 |
| 189 | #elif defined(CONFIG_C_AMBEN_B0_B1) |
| 190 | #define V_AMBEN AMBEN_B0_B1 |
| 191 | #elif defined(CONFIG_C_AMBEN_B0_B1_B2) |
| 192 | #define V_AMBEN AMBEN_B0_B1_B2 |
| 193 | #endif |
| 194 | |
| 195 | #ifdef CONFIG_C_AMCKEN |
| 196 | #define V_AMCKEN AMCKEN |
| 197 | #else |
| 198 | #define V_AMCKEN 0x0 |
| 199 | #endif |
| 200 | |
| 201 | #ifdef CONFIG_C_B0PEN |
| 202 | #define V_B0PEN 0x10 |
| 203 | #else |
| 204 | #define V_B0PEN 0x00 |
| 205 | #endif |
| 206 | |
| 207 | #ifdef CONFIG_C_B1PEN |
| 208 | #define V_B1PEN 0x20 |
| 209 | #else |
| 210 | #define V_B1PEN 0x00 |
| 211 | #endif |
| 212 | |
| 213 | #ifdef CONFIG_C_B2PEN |
| 214 | #define V_B2PEN 0x40 |
| 215 | #else |
| 216 | #define V_B2PEN 0x00 |
| 217 | #endif |
| 218 | |
| 219 | #ifdef CONFIG_C_B3PEN |
| 220 | #define V_B3PEN 0x80 |
| 221 | #else |
| 222 | #define V_B3PEN 0x00 |
| 223 | #endif |
| 224 | |
| 225 | #ifdef CONFIG_C_CDPRIO |
| 226 | #define V_CDPRIO 0x100 |
| 227 | #else |
| 228 | #define V_CDPRIO 0x0 |
| 229 | #endif |
| 230 | |
| 231 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) |
| 232 | |
| 233 | #define MAX_VC 600000000 |
| 234 | #define MIN_VC 50000000 |
| 235 | |
| 236 | /******************************* PLL Settings ********************************/ |
| 237 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
| 238 | #if (CONFIG_VCO_MULT < 0) |
| 239 | #error "VCO Multiplier is less than 0. Please select a different value" |
| 240 | #endif |
| 241 | |
| 242 | #if (CONFIG_VCO_MULT == 0) |
| 243 | #error "VCO Multiplier should be greater than 0. Please select a different value" |
| 244 | #endif |
| 245 | |
| 246 | #ifndef CONFIG_CLKIN_HALF |
| 247 | #define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) |
| 248 | #else |
| 249 | #define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) |
| 250 | #endif |
| 251 | |
| 252 | #ifndef CONFIG_PLL_BYPASS |
| 253 | #define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) |
| 254 | #define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) |
| 255 | #else |
| 256 | #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
| 257 | #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
| 258 | #endif |
| 259 | |
| 260 | #if (CONFIG_SCLK_DIV < 1) |
| 261 | #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" |
| 262 | #endif |
| 263 | |
| 264 | #if (CONFIG_SCLK_DIV > 15) |
| 265 | #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" |
| 266 | #endif |
| 267 | |
| 268 | #if (CONFIG_CCLK_DIV != 1) |
| 269 | #if (CONFIG_CCLK_DIV != 2) |
| 270 | #if (CONFIG_CCLK_DIV != 4) |
| 271 | #if (CONFIG_CCLK_DIV != 8) |
| 272 | #error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" |
| 273 | #endif |
| 274 | #endif |
| 275 | #endif |
| 276 | #endif |
| 277 | |
| 278 | #if (CONFIG_VCO_HZ > MAX_VC) |
| 279 | #error "VCO selected is more than maximum value. Please change the VCO multipler" |
| 280 | #endif |
| 281 | |
| 282 | #if (CONFIG_SCLK_HZ > 133000000) |
| 283 | #error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" |
| 284 | #endif |
| 285 | |
| 286 | #if (CONFIG_SCLK_HZ < 27000000) |
| 287 | #error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" |
| 288 | #endif |
| 289 | |
| 290 | #if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) |
| 291 | #if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) |
| 292 | #if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) |
| 293 | #error "Please select sclk less than cclk" |
| 294 | #endif |
| 295 | #endif |
| 296 | #endif |
| 297 | |
| 298 | #if (CONFIG_CCLK_DIV == 1) |
| 299 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV1 |
| 300 | #endif |
| 301 | #if (CONFIG_CCLK_DIV == 2) |
| 302 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV2 |
| 303 | #endif |
| 304 | #if (CONFIG_CCLK_DIV == 4) |
| 305 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV4 |
| 306 | #endif |
| 307 | #if (CONFIG_CCLK_DIV == 8) |
| 308 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV8 |
| 309 | #endif |
| 310 | #ifndef CONFIG_CCLK_ACT_DIV |
| 311 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly |
| 312 | #endif |
| 313 | |
| 314 | #if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) |
| 315 | #error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK |
| 316 | #endif |
| 317 | |
| 318 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
| 319 | |
| 320 | #ifdef CONFIG_BF561 |
| 321 | #define CPU "BF561" |
| 322 | #define CPUID 0x027bb000 |
| 323 | #endif |
| 324 | #ifndef CPU |
| 325 | #define CPU "UNKNOWN" |
| 326 | #define CPUID 0x0 |
| 327 | #endif |
| 328 | |
| 329 | #if (CONFIG_MEM_SIZE % 4) |
| 330 | #error "SDRAM memory size must be a multiple of 4MB!" |
| 331 | #endif |
| 332 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) |
| 333 | #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) |
| 334 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
| 335 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) |
| 336 | |
| 337 | /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ |
| 338 | |
| 339 | #define ANOMALY_05000158_WORKAROUND 0x200 |
| 340 | #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ |
| 341 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ |
| 342 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) |
| 343 | #else /*Write Through */ |
| 344 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \ |
| 345 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) |
| 346 | #endif |
| 347 | |
| 348 | |
| 349 | #define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) |
| 350 | #define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) |
| 351 | #define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) |
| 352 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) |
| 353 | |
| 354 | #define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) |
| 355 | |
| 356 | #define SIZE_1K 0x00000400 /* 1K */ |
| 357 | #define SIZE_4K 0x00001000 /* 4K */ |
| 358 | #define SIZE_1M 0x00100000 /* 1M */ |
| 359 | #define SIZE_4M 0x00400000 /* 4M */ |
| 360 | |
| 361 | #define MAX_CPLBS (16 * 2) |
| 362 | |
| 363 | /* |
| 364 | * Number of required data CPLB switchtable entries |
| 365 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs |
| 366 | * approx 16 for smaller 1MB page size CPLBs for allignment purposes |
| 367 | * 1 for L1 Data Memory |
| 368 | * 1 for L2 Data Memory |
| 369 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO |
| 370 | * 64 for ASYNC Memory |
| 371 | */ |
| 372 | |
| 373 | |
| 374 | #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2) |
| 375 | |
| 376 | /* |
| 377 | * Number of required instruction CPLB switchtable entries |
| 378 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs |
| 379 | * approx 12 for smaller 1MB page size CPLBs for allignment purposes |
| 380 | * 1 for L1 Instruction Memory |
| 381 | * 1 for L2 Instruction Memory |
| 382 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO |
| 383 | */ |
| 384 | |
| 385 | #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) |
| 386 | |
| 387 | #if 0 /* comment by mhfan */ |
| 388 | /* Event Vector Table Address */ |
| 389 | #define EVT_EMULATION_ADDR 0xffe02000 |
| 390 | #define EVT_RESET_ADDR 0xffe02004 |
| 391 | #define EVT_NMI_ADDR 0xffe02008 |
| 392 | #define EVT_EXCEPTION_ADDR 0xffe0200c |
| 393 | #define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 |
| 394 | #define EVT_HARDWARE_ERROR_ADDR 0xffe02014 |
| 395 | #define EVT_TIMER_ADDR 0xffe02018 |
| 396 | #define EVT_IVG7_ADDR 0xffe0201c |
| 397 | #define EVT_IVG8_ADDR 0xffe02020 |
| 398 | #define EVT_IVG9_ADDR 0xffe02024 |
| 399 | #define EVT_IVG10_ADDR 0xffe02028 |
| 400 | #define EVT_IVG11_ADDR 0xffe0202c |
| 401 | #define EVT_IVG12_ADDR 0xffe02030 |
| 402 | #define EVT_IVG13_ADDR 0xffe02034 |
| 403 | #define EVT_IVG14_ADDR 0xffe02038 |
| 404 | #define EVT_IVG15_ADDR 0xffe0203c |
| 405 | #define EVT_OVERRIDE_ADDR 0xffe02100 |
| 406 | #endif /* comment by mhfan */ |
| 407 | |
| 408 | #endif /* __MACH_BF561_H__ */ |