Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // mt8195-mt6359-rt1019-rt5682.c -- |
| 4 | // MT8195-MT6359-RT1019-RT6358 ALSA SoC machine driver |
| 5 | // |
| 6 | // Copyright (c) 2021 MediaTek Inc. |
| 7 | // Author: Trevor Wu <trevor.wu@mediatek.com> |
| 8 | // |
| 9 | |
| 10 | #include <linux/input.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/pm_runtime.h> |
| 13 | #include <sound/jack.h> |
| 14 | #include <sound/pcm_params.h> |
| 15 | #include <sound/rt5682.h> |
| 16 | #include <sound/soc.h> |
| 17 | #include "../../codecs/mt6359.h" |
| 18 | #include "../../codecs/rt5682.h" |
| 19 | #include "../common/mtk-afe-platform-driver.h" |
| 20 | #include "mt8195-afe-common.h" |
| 21 | |
| 22 | #define RT1019_CODEC_DAI "HiFi" |
| 23 | #define RT1019_DEV0_NAME "rt1019p" |
| 24 | |
| 25 | #define RT5682_CODEC_DAI "rt5682-aif1" |
| 26 | #define RT5682_DEV0_NAME "rt5682.2-001a" |
| 27 | |
| 28 | struct mt8195_mt6359_rt1019_rt5682_priv { |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 29 | struct device_node *platform_node; |
| 30 | struct device_node *hdmi_node; |
| 31 | struct device_node *dp_node; |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 32 | struct snd_soc_jack headset_jack; |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 33 | struct snd_soc_jack dp_jack; |
Trevor Wu | ef46cd4 | 2021-08-19 16:41:43 +0800 | [diff] [blame] | 34 | struct snd_soc_jack hdmi_jack; |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | static const struct snd_soc_dapm_widget |
| 38 | mt8195_mt6359_rt1019_rt5682_widgets[] = { |
| 39 | SND_SOC_DAPM_SPK("Speakers", NULL), |
| 40 | SND_SOC_DAPM_HP("Headphone Jack", NULL), |
| 41 | SND_SOC_DAPM_MIC("Headset Mic", NULL), |
| 42 | }; |
| 43 | |
| 44 | static const struct snd_soc_dapm_route mt8195_mt6359_rt1019_rt5682_routes[] = { |
| 45 | /* speaker */ |
| 46 | { "Speakers", NULL, "Speaker" }, |
| 47 | /* headset */ |
| 48 | { "Headphone Jack", NULL, "HPOL" }, |
| 49 | { "Headphone Jack", NULL, "HPOR" }, |
| 50 | { "IN1P", NULL, "Headset Mic" }, |
| 51 | }; |
| 52 | |
| 53 | static const struct snd_kcontrol_new mt8195_mt6359_rt1019_rt5682_controls[] = { |
| 54 | SOC_DAPM_PIN_SWITCH("Speakers"), |
| 55 | SOC_DAPM_PIN_SWITCH("Headphone Jack"), |
| 56 | SOC_DAPM_PIN_SWITCH("Headset Mic"), |
| 57 | }; |
| 58 | |
| 59 | static int mt8195_rt5682_etdm_hw_params(struct snd_pcm_substream *substream, |
| 60 | struct snd_pcm_hw_params *params) |
| 61 | { |
| 62 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 63 | struct snd_soc_card *card = rtd->card; |
| 64 | struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); |
| 65 | struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); |
| 66 | unsigned int rate = params_rate(params); |
| 67 | unsigned int mclk_fs_ratio = 128; |
| 68 | unsigned int mclk_fs = rate * mclk_fs_ratio; |
| 69 | int bitwidth; |
| 70 | int ret; |
| 71 | |
| 72 | bitwidth = snd_pcm_format_width(params_format(params)); |
| 73 | if (bitwidth < 0) { |
| 74 | dev_err(card->dev, "invalid bit width: %d\n", bitwidth); |
| 75 | return bitwidth; |
| 76 | } |
| 77 | |
| 78 | ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth); |
| 79 | if (ret) { |
| 80 | dev_err(card->dev, "failed to set tdm slot\n"); |
| 81 | return ret; |
| 82 | } |
| 83 | |
| 84 | ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1, |
| 85 | RT5682_PLL1_S_BCLK1, |
| 86 | params_rate(params) * 64, |
| 87 | params_rate(params) * 512); |
| 88 | if (ret) { |
| 89 | dev_err(card->dev, "failed to set pll\n"); |
| 90 | return ret; |
| 91 | } |
| 92 | |
| 93 | ret = snd_soc_dai_set_sysclk(codec_dai, |
| 94 | RT5682_SCLK_S_PLL1, |
| 95 | params_rate(params) * 512, |
| 96 | SND_SOC_CLOCK_IN); |
| 97 | if (ret) { |
| 98 | dev_err(card->dev, "failed to set sysclk\n"); |
| 99 | return ret; |
| 100 | } |
| 101 | |
| 102 | return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT); |
| 103 | } |
| 104 | |
| 105 | static const struct snd_soc_ops mt8195_rt5682_etdm_ops = { |
| 106 | .hw_params = mt8195_rt5682_etdm_hw_params, |
| 107 | }; |
| 108 | |
| 109 | #define CKSYS_AUD_TOP_CFG 0x032c |
| 110 | #define CKSYS_AUD_TOP_MON 0x0330 |
| 111 | |
| 112 | static int mt8195_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd) |
| 113 | { |
| 114 | struct snd_soc_component *cmpnt_afe = |
| 115 | snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); |
| 116 | struct snd_soc_component *cmpnt_codec = |
| 117 | asoc_rtd_to_codec(rtd, 0)->component; |
| 118 | struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe); |
| 119 | struct mt8195_afe_private *afe_priv = afe->platform_priv; |
| 120 | struct mtkaif_param *param = &afe_priv->mtkaif_params; |
| 121 | int phase; |
| 122 | unsigned int monitor; |
| 123 | int mtkaif_calibration_num_phase; |
| 124 | int test_done_1, test_done_2, test_done_3; |
| 125 | int cycle_1, cycle_2, cycle_3; |
| 126 | int prev_cycle_1, prev_cycle_2, prev_cycle_3; |
| 127 | int chosen_phase_1, chosen_phase_2, chosen_phase_3; |
| 128 | int counter; |
| 129 | bool mtkaif_calibration_ok; |
| 130 | int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM]; |
| 131 | int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM]; |
| 132 | int i; |
| 133 | |
| 134 | dev_info(afe->dev, "%s(), start\n", __func__); |
| 135 | |
| 136 | param->mtkaif_calibration_ok = false; |
| 137 | for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++) { |
| 138 | param->mtkaif_chosen_phase[i] = -1; |
| 139 | param->mtkaif_phase_cycle[i] = 0; |
| 140 | mtkaif_chosen_phase[i] = -1; |
| 141 | mtkaif_phase_cycle[i] = 0; |
| 142 | } |
| 143 | |
| 144 | if (IS_ERR(afe_priv->topckgen)) { |
| 145 | dev_info(afe->dev, "%s() Cannot find topckgen controller\n", |
| 146 | __func__); |
| 147 | return 0; |
| 148 | } |
| 149 | |
| 150 | pm_runtime_get_sync(afe->dev); |
| 151 | mt6359_mtkaif_calibration_enable(cmpnt_codec); |
| 152 | |
| 153 | /* set test type to synchronizer pulse */ |
| 154 | regmap_update_bits(afe_priv->topckgen, |
| 155 | CKSYS_AUD_TOP_CFG, 0xffff, 0x4); |
| 156 | mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */ |
| 157 | mtkaif_calibration_ok = true; |
| 158 | |
| 159 | for (phase = 0; |
| 160 | phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok; |
| 161 | phase++) { |
| 162 | mt6359_set_mtkaif_calibration_phase(cmpnt_codec, |
| 163 | phase, phase, phase); |
| 164 | |
| 165 | regmap_update_bits(afe_priv->topckgen, |
| 166 | CKSYS_AUD_TOP_CFG, 0x1, 0x1); |
| 167 | |
| 168 | test_done_1 = 0; |
| 169 | test_done_2 = 0; |
| 170 | test_done_3 = 0; |
| 171 | cycle_1 = -1; |
| 172 | cycle_2 = -1; |
| 173 | cycle_3 = -1; |
| 174 | counter = 0; |
| 175 | while (!(test_done_1 & test_done_2 & test_done_3)) { |
| 176 | regmap_read(afe_priv->topckgen, |
| 177 | CKSYS_AUD_TOP_MON, &monitor); |
| 178 | test_done_1 = (monitor >> 28) & 0x1; |
| 179 | test_done_2 = (monitor >> 29) & 0x1; |
| 180 | test_done_3 = (monitor >> 30) & 0x1; |
| 181 | if (test_done_1 == 1) |
| 182 | cycle_1 = monitor & 0xf; |
| 183 | |
| 184 | if (test_done_2 == 1) |
| 185 | cycle_2 = (monitor >> 4) & 0xf; |
| 186 | |
| 187 | if (test_done_3 == 1) |
| 188 | cycle_3 = (monitor >> 8) & 0xf; |
| 189 | |
| 190 | /* handle if never test done */ |
| 191 | if (++counter > 10000) { |
| 192 | dev_info(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n", |
| 193 | __func__, |
| 194 | cycle_1, cycle_2, cycle_3, monitor); |
| 195 | mtkaif_calibration_ok = false; |
| 196 | break; |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | if (phase == 0) { |
| 201 | prev_cycle_1 = cycle_1; |
| 202 | prev_cycle_2 = cycle_2; |
| 203 | prev_cycle_3 = cycle_3; |
| 204 | } |
| 205 | |
| 206 | if (cycle_1 != prev_cycle_1 && |
| 207 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) { |
| 208 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = phase - 1; |
| 209 | mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] = prev_cycle_1; |
| 210 | } |
| 211 | |
| 212 | if (cycle_2 != prev_cycle_2 && |
| 213 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) { |
| 214 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = phase - 1; |
| 215 | mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] = prev_cycle_2; |
| 216 | } |
| 217 | |
| 218 | if (cycle_3 != prev_cycle_3 && |
| 219 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) { |
| 220 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = phase - 1; |
| 221 | mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] = prev_cycle_3; |
| 222 | } |
| 223 | |
| 224 | regmap_update_bits(afe_priv->topckgen, |
| 225 | CKSYS_AUD_TOP_CFG, 0x1, 0x0); |
| 226 | |
| 227 | if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] >= 0 && |
| 228 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] >= 0 && |
| 229 | mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] >= 0) |
| 230 | break; |
| 231 | } |
| 232 | |
| 233 | if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) { |
| 234 | mtkaif_calibration_ok = false; |
| 235 | chosen_phase_1 = 0; |
| 236 | } else { |
| 237 | chosen_phase_1 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0]; |
| 238 | } |
| 239 | |
| 240 | if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) { |
| 241 | mtkaif_calibration_ok = false; |
| 242 | chosen_phase_2 = 0; |
| 243 | } else { |
| 244 | chosen_phase_2 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1]; |
| 245 | } |
| 246 | |
| 247 | if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) { |
| 248 | mtkaif_calibration_ok = false; |
| 249 | chosen_phase_3 = 0; |
| 250 | } else { |
| 251 | chosen_phase_3 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2]; |
| 252 | } |
| 253 | |
| 254 | mt6359_set_mtkaif_calibration_phase(cmpnt_codec, |
| 255 | chosen_phase_1, |
| 256 | chosen_phase_2, |
| 257 | chosen_phase_3); |
| 258 | |
| 259 | mt6359_mtkaif_calibration_disable(cmpnt_codec); |
| 260 | pm_runtime_put(afe->dev); |
| 261 | |
| 262 | param->mtkaif_calibration_ok = mtkaif_calibration_ok; |
| 263 | param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = chosen_phase_1; |
| 264 | param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = chosen_phase_2; |
| 265 | param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = chosen_phase_3; |
| 266 | for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++) |
| 267 | param->mtkaif_phase_cycle[i] = mtkaif_phase_cycle[i]; |
| 268 | |
| 269 | dev_info(afe->dev, "%s(), end, calibration ok %d\n", |
| 270 | __func__, param->mtkaif_calibration_ok); |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static int mt8195_mt6359_init(struct snd_soc_pcm_runtime *rtd) |
| 276 | { |
| 277 | struct snd_soc_component *cmpnt_codec = |
| 278 | asoc_rtd_to_codec(rtd, 0)->component; |
| 279 | |
| 280 | /* set mtkaif protocol */ |
| 281 | mt6359_set_mtkaif_protocol(cmpnt_codec, |
| 282 | MT6359_MTKAIF_PROTOCOL_2_CLK_P2); |
| 283 | |
| 284 | /* mtkaif calibration */ |
| 285 | mt8195_mt6359_mtkaif_calibration(rtd); |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | static int mt8195_rt5682_init(struct snd_soc_pcm_runtime *rtd) |
| 291 | { |
| 292 | struct snd_soc_component *cmpnt_codec = |
| 293 | asoc_rtd_to_codec(rtd, 0)->component; |
| 294 | struct mt8195_mt6359_rt1019_rt5682_priv *priv = |
| 295 | snd_soc_card_get_drvdata(rtd->card); |
| 296 | struct snd_soc_jack *jack = &priv->headset_jack; |
| 297 | int ret; |
| 298 | |
| 299 | ret = snd_soc_card_jack_new(rtd->card, "Headset Jack", |
| 300 | SND_JACK_HEADSET | SND_JACK_BTN_0 | |
| 301 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | |
| 302 | SND_JACK_BTN_3, |
| 303 | jack, NULL, 0); |
| 304 | if (ret) { |
| 305 | dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret); |
| 306 | return ret; |
| 307 | } |
| 308 | |
| 309 | snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); |
| 310 | snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND); |
| 311 | snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP); |
| 312 | snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN); |
| 313 | |
| 314 | ret = snd_soc_component_set_jack(cmpnt_codec, jack, NULL); |
| 315 | if (ret) { |
| 316 | dev_err(rtd->dev, "Headset Jack set failed: %d\n", ret); |
| 317 | return ret; |
| 318 | } |
| 319 | |
| 320 | return 0; |
| 321 | }; |
| 322 | |
| 323 | static int mt8195_etdm_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, |
| 324 | struct snd_pcm_hw_params *params) |
| 325 | { |
| 326 | /* fix BE i2s format to 32bit, clean param mask first */ |
| 327 | snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), |
| 328 | 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST); |
| 329 | |
| 330 | params_set_format(params, SNDRV_PCM_FORMAT_S24_LE); |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 335 | static int mt8195_hdmitx_dptx_startup(struct snd_pcm_substream *substream) |
| 336 | { |
| 337 | static const unsigned int rates[] = { |
| 338 | 48000 |
| 339 | }; |
| 340 | static const unsigned int channels[] = { |
| 341 | 2, 4, 6, 8 |
| 342 | }; |
| 343 | static const struct snd_pcm_hw_constraint_list constraints_rates = { |
| 344 | .count = ARRAY_SIZE(rates), |
| 345 | .list = rates, |
| 346 | .mask = 0, |
| 347 | }; |
| 348 | static const struct snd_pcm_hw_constraint_list constraints_channels = { |
| 349 | .count = ARRAY_SIZE(channels), |
| 350 | .list = channels, |
| 351 | .mask = 0, |
| 352 | }; |
| 353 | |
| 354 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
| 355 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 356 | int ret; |
| 357 | |
| 358 | ret = snd_pcm_hw_constraint_list(runtime, 0, |
| 359 | SNDRV_PCM_HW_PARAM_RATE, |
| 360 | &constraints_rates); |
| 361 | if (ret < 0) { |
| 362 | dev_err(rtd->dev, "hw_constraint_list rate failed\n"); |
| 363 | return ret; |
| 364 | } |
| 365 | |
| 366 | ret = snd_pcm_hw_constraint_list(runtime, 0, |
| 367 | SNDRV_PCM_HW_PARAM_CHANNELS, |
| 368 | &constraints_channels); |
| 369 | if (ret < 0) { |
| 370 | dev_err(rtd->dev, "hw_constraint_list channel failed\n"); |
| 371 | return ret; |
| 372 | } |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | static const struct snd_soc_ops mt8195_hdmitx_dptx_playback_ops = { |
| 378 | .startup = mt8195_hdmitx_dptx_startup, |
| 379 | }; |
| 380 | |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 381 | static int mt8195_dptx_hw_params(struct snd_pcm_substream *substream, |
| 382 | struct snd_pcm_hw_params *params) |
| 383 | { |
| 384 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 385 | struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); |
| 386 | unsigned int rate = params_rate(params); |
| 387 | unsigned int mclk_fs_ratio = 256; |
| 388 | unsigned int mclk_fs = rate * mclk_fs_ratio; |
| 389 | |
| 390 | return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, |
| 391 | SND_SOC_CLOCK_OUT); |
| 392 | } |
| 393 | |
| 394 | static struct snd_soc_ops mt8195_dptx_ops = { |
| 395 | .hw_params = mt8195_dptx_hw_params, |
| 396 | }; |
| 397 | |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 398 | static int mt8195_dptx_codec_init(struct snd_soc_pcm_runtime *rtd) |
| 399 | { |
| 400 | struct mt8195_mt6359_rt1019_rt5682_priv *priv = |
| 401 | snd_soc_card_get_drvdata(rtd->card); |
| 402 | struct snd_soc_component *cmpnt_codec = |
| 403 | asoc_rtd_to_codec(rtd, 0)->component; |
| 404 | int ret = 0; |
| 405 | |
| 406 | ret = snd_soc_card_jack_new(rtd->card, "DP Jack", SND_JACK_LINEOUT, |
| 407 | &priv->dp_jack, NULL, 0); |
| 408 | if (ret) |
| 409 | return ret; |
| 410 | |
| 411 | return snd_soc_component_set_jack(cmpnt_codec, &priv->dp_jack, NULL); |
| 412 | } |
| 413 | |
Trevor Wu | ef46cd4 | 2021-08-19 16:41:43 +0800 | [diff] [blame] | 414 | static int mt8195_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) |
| 415 | { |
| 416 | struct mt8195_mt6359_rt1019_rt5682_priv *priv = |
| 417 | snd_soc_card_get_drvdata(rtd->card); |
| 418 | struct snd_soc_component *cmpnt_codec = |
| 419 | asoc_rtd_to_codec(rtd, 0)->component; |
| 420 | int ret = 0; |
| 421 | |
| 422 | ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, |
| 423 | &priv->hdmi_jack, NULL, 0); |
| 424 | if (ret) |
| 425 | return ret; |
| 426 | |
| 427 | return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL); |
| 428 | } |
| 429 | |
Trevor Wu | 3abe2ee | 2021-09-17 16:28:05 +0800 | [diff] [blame] | 430 | static int mt8195_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, |
| 431 | struct snd_pcm_hw_params *params) |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 432 | |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 433 | { |
| 434 | /* fix BE i2s format to 32bit, clean param mask first */ |
| 435 | snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), |
| 436 | 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST); |
| 437 | |
| 438 | params_set_format(params, SNDRV_PCM_FORMAT_S24_LE); |
| 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | static int mt8195_playback_startup(struct snd_pcm_substream *substream) |
| 444 | { |
| 445 | static const unsigned int rates[] = { |
| 446 | 48000 |
| 447 | }; |
| 448 | static const unsigned int channels[] = { |
| 449 | 2 |
| 450 | }; |
| 451 | static const struct snd_pcm_hw_constraint_list constraints_rates = { |
| 452 | .count = ARRAY_SIZE(rates), |
| 453 | .list = rates, |
| 454 | .mask = 0, |
| 455 | }; |
| 456 | static const struct snd_pcm_hw_constraint_list constraints_channels = { |
| 457 | .count = ARRAY_SIZE(channels), |
| 458 | .list = channels, |
| 459 | .mask = 0, |
| 460 | }; |
| 461 | |
| 462 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
| 463 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 464 | int ret; |
| 465 | |
| 466 | ret = snd_pcm_hw_constraint_list(runtime, 0, |
| 467 | SNDRV_PCM_HW_PARAM_RATE, |
| 468 | &constraints_rates); |
| 469 | if (ret < 0) { |
| 470 | dev_err(rtd->dev, "hw_constraint_list rate failed\n"); |
| 471 | return ret; |
| 472 | } |
| 473 | |
| 474 | ret = snd_pcm_hw_constraint_list(runtime, 0, |
| 475 | SNDRV_PCM_HW_PARAM_CHANNELS, |
| 476 | &constraints_channels); |
| 477 | if (ret < 0) { |
| 478 | dev_err(rtd->dev, "hw_constraint_list channel failed\n"); |
| 479 | return ret; |
| 480 | } |
| 481 | |
| 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | static const struct snd_soc_ops mt8195_playback_ops = { |
| 486 | .startup = mt8195_playback_startup, |
| 487 | }; |
| 488 | |
| 489 | static int mt8195_capture_startup(struct snd_pcm_substream *substream) |
| 490 | { |
| 491 | static const unsigned int rates[] = { |
| 492 | 48000 |
| 493 | }; |
| 494 | static const unsigned int channels[] = { |
| 495 | 1, 2 |
| 496 | }; |
| 497 | static const struct snd_pcm_hw_constraint_list constraints_rates = { |
| 498 | .count = ARRAY_SIZE(rates), |
| 499 | .list = rates, |
| 500 | .mask = 0, |
| 501 | }; |
| 502 | static const struct snd_pcm_hw_constraint_list constraints_channels = { |
| 503 | .count = ARRAY_SIZE(channels), |
| 504 | .list = channels, |
| 505 | .mask = 0, |
| 506 | }; |
| 507 | |
| 508 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
| 509 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 510 | int ret; |
| 511 | |
| 512 | ret = snd_pcm_hw_constraint_list(runtime, 0, |
| 513 | SNDRV_PCM_HW_PARAM_RATE, |
| 514 | &constraints_rates); |
| 515 | if (ret < 0) { |
| 516 | dev_err(rtd->dev, "hw_constraint_list rate failed\n"); |
| 517 | return ret; |
| 518 | } |
| 519 | |
| 520 | ret = snd_pcm_hw_constraint_list(runtime, 0, |
| 521 | SNDRV_PCM_HW_PARAM_CHANNELS, |
| 522 | &constraints_channels); |
| 523 | if (ret < 0) { |
| 524 | dev_err(rtd->dev, "hw_constraint_list channel failed\n"); |
| 525 | return ret; |
| 526 | } |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | static const struct snd_soc_ops mt8195_capture_ops = { |
| 532 | .startup = mt8195_capture_startup, |
| 533 | }; |
| 534 | |
| 535 | enum { |
| 536 | DAI_LINK_DL2_FE, |
| 537 | DAI_LINK_DL3_FE, |
| 538 | DAI_LINK_DL6_FE, |
| 539 | DAI_LINK_DL7_FE, |
| 540 | DAI_LINK_DL8_FE, |
| 541 | DAI_LINK_DL10_FE, |
| 542 | DAI_LINK_DL11_FE, |
| 543 | DAI_LINK_UL1_FE, |
| 544 | DAI_LINK_UL2_FE, |
| 545 | DAI_LINK_UL3_FE, |
| 546 | DAI_LINK_UL4_FE, |
| 547 | DAI_LINK_UL5_FE, |
| 548 | DAI_LINK_UL6_FE, |
| 549 | DAI_LINK_UL8_FE, |
| 550 | DAI_LINK_UL9_FE, |
| 551 | DAI_LINK_UL10_FE, |
| 552 | DAI_LINK_DL_SRC_BE, |
| 553 | DAI_LINK_DPTX_BE, |
| 554 | DAI_LINK_ETDM1_IN_BE, |
| 555 | DAI_LINK_ETDM2_IN_BE, |
| 556 | DAI_LINK_ETDM1_OUT_BE, |
| 557 | DAI_LINK_ETDM2_OUT_BE, |
| 558 | DAI_LINK_ETDM3_OUT_BE, |
| 559 | DAI_LINK_PCM1_BE, |
| 560 | DAI_LINK_UL_SRC1_BE, |
| 561 | DAI_LINK_UL_SRC2_BE, |
| 562 | }; |
| 563 | |
| 564 | /* FE */ |
| 565 | SND_SOC_DAILINK_DEFS(DL2_FE, |
| 566 | DAILINK_COMP_ARRAY(COMP_CPU("DL2")), |
| 567 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 568 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 569 | |
| 570 | SND_SOC_DAILINK_DEFS(DL3_FE, |
| 571 | DAILINK_COMP_ARRAY(COMP_CPU("DL3")), |
| 572 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 573 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 574 | |
| 575 | SND_SOC_DAILINK_DEFS(DL6_FE, |
| 576 | DAILINK_COMP_ARRAY(COMP_CPU("DL6")), |
| 577 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 578 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 579 | |
| 580 | SND_SOC_DAILINK_DEFS(DL7_FE, |
| 581 | DAILINK_COMP_ARRAY(COMP_CPU("DL7")), |
| 582 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 583 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 584 | |
| 585 | SND_SOC_DAILINK_DEFS(DL8_FE, |
| 586 | DAILINK_COMP_ARRAY(COMP_CPU("DL8")), |
| 587 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 588 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 589 | |
| 590 | SND_SOC_DAILINK_DEFS(DL10_FE, |
| 591 | DAILINK_COMP_ARRAY(COMP_CPU("DL10")), |
| 592 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 593 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 594 | |
| 595 | SND_SOC_DAILINK_DEFS(DL11_FE, |
| 596 | DAILINK_COMP_ARRAY(COMP_CPU("DL11")), |
| 597 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 598 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 599 | |
| 600 | SND_SOC_DAILINK_DEFS(UL1_FE, |
| 601 | DAILINK_COMP_ARRAY(COMP_CPU("UL1")), |
| 602 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 603 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 604 | |
| 605 | SND_SOC_DAILINK_DEFS(UL2_FE, |
| 606 | DAILINK_COMP_ARRAY(COMP_CPU("UL2")), |
| 607 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 608 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 609 | |
| 610 | SND_SOC_DAILINK_DEFS(UL3_FE, |
| 611 | DAILINK_COMP_ARRAY(COMP_CPU("UL3")), |
| 612 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 613 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 614 | |
| 615 | SND_SOC_DAILINK_DEFS(UL4_FE, |
| 616 | DAILINK_COMP_ARRAY(COMP_CPU("UL4")), |
| 617 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 618 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 619 | |
| 620 | SND_SOC_DAILINK_DEFS(UL5_FE, |
| 621 | DAILINK_COMP_ARRAY(COMP_CPU("UL5")), |
| 622 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 623 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 624 | |
| 625 | SND_SOC_DAILINK_DEFS(UL6_FE, |
| 626 | DAILINK_COMP_ARRAY(COMP_CPU("UL6")), |
| 627 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 628 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 629 | |
| 630 | SND_SOC_DAILINK_DEFS(UL8_FE, |
| 631 | DAILINK_COMP_ARRAY(COMP_CPU("UL8")), |
| 632 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 633 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 634 | |
| 635 | SND_SOC_DAILINK_DEFS(UL9_FE, |
| 636 | DAILINK_COMP_ARRAY(COMP_CPU("UL9")), |
| 637 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 638 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 639 | |
| 640 | SND_SOC_DAILINK_DEFS(UL10_FE, |
| 641 | DAILINK_COMP_ARRAY(COMP_CPU("UL10")), |
| 642 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 643 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 644 | |
| 645 | /* BE */ |
| 646 | SND_SOC_DAILINK_DEFS(DL_SRC_BE, |
| 647 | DAILINK_COMP_ARRAY(COMP_CPU("DL_SRC")), |
| 648 | DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound", |
| 649 | "mt6359-snd-codec-aif1")), |
| 650 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 651 | |
| 652 | SND_SOC_DAILINK_DEFS(DPTX_BE, |
| 653 | DAILINK_COMP_ARRAY(COMP_CPU("DPTX")), |
| 654 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 655 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 656 | |
| 657 | SND_SOC_DAILINK_DEFS(ETDM1_IN_BE, |
| 658 | DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_IN")), |
| 659 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 660 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 661 | |
| 662 | SND_SOC_DAILINK_DEFS(ETDM2_IN_BE, |
| 663 | DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_IN")), |
| 664 | DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME, |
| 665 | RT5682_CODEC_DAI)), |
| 666 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 667 | |
| 668 | SND_SOC_DAILINK_DEFS(ETDM1_OUT_BE, |
| 669 | DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_OUT")), |
| 670 | DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME, |
| 671 | RT5682_CODEC_DAI)), |
| 672 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 673 | |
| 674 | SND_SOC_DAILINK_DEFS(ETDM2_OUT_BE, |
| 675 | DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_OUT")), |
| 676 | DAILINK_COMP_ARRAY(COMP_CODEC(RT1019_DEV0_NAME, |
| 677 | RT1019_CODEC_DAI)), |
| 678 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 679 | |
| 680 | SND_SOC_DAILINK_DEFS(ETDM3_OUT_BE, |
| 681 | DAILINK_COMP_ARRAY(COMP_CPU("ETDM3_OUT")), |
| 682 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 683 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 684 | |
| 685 | SND_SOC_DAILINK_DEFS(PCM1_BE, |
| 686 | DAILINK_COMP_ARRAY(COMP_CPU("PCM1")), |
| 687 | DAILINK_COMP_ARRAY(COMP_DUMMY()), |
| 688 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 689 | |
| 690 | SND_SOC_DAILINK_DEFS(UL_SRC1_BE, |
| 691 | DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC1")), |
| 692 | DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound", |
| 693 | "mt6359-snd-codec-aif1"), |
| 694 | COMP_CODEC("dmic-codec", |
| 695 | "dmic-hifi")), |
| 696 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 697 | |
| 698 | SND_SOC_DAILINK_DEFS(UL_SRC2_BE, |
| 699 | DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC2")), |
| 700 | DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound", |
| 701 | "mt6359-snd-codec-aif2")), |
| 702 | DAILINK_COMP_ARRAY(COMP_EMPTY())); |
| 703 | |
| 704 | static struct snd_soc_dai_link mt8195_mt6359_rt1019_rt5682_dai_links[] = { |
| 705 | /* FE */ |
| 706 | [DAI_LINK_DL2_FE] = { |
| 707 | .name = "DL2_FE", |
| 708 | .stream_name = "DL2 Playback", |
| 709 | .trigger = { |
| 710 | SND_SOC_DPCM_TRIGGER_POST, |
| 711 | SND_SOC_DPCM_TRIGGER_POST, |
| 712 | }, |
| 713 | .dynamic = 1, |
| 714 | .dpcm_playback = 1, |
| 715 | .ops = &mt8195_playback_ops, |
| 716 | SND_SOC_DAILINK_REG(DL2_FE), |
| 717 | }, |
| 718 | [DAI_LINK_DL3_FE] = { |
| 719 | .name = "DL3_FE", |
| 720 | .stream_name = "DL3 Playback", |
| 721 | .trigger = { |
| 722 | SND_SOC_DPCM_TRIGGER_POST, |
| 723 | SND_SOC_DPCM_TRIGGER_POST, |
| 724 | }, |
| 725 | .dynamic = 1, |
| 726 | .dpcm_playback = 1, |
| 727 | .ops = &mt8195_playback_ops, |
| 728 | SND_SOC_DAILINK_REG(DL3_FE), |
| 729 | }, |
| 730 | [DAI_LINK_DL6_FE] = { |
| 731 | .name = "DL6_FE", |
| 732 | .stream_name = "DL6 Playback", |
| 733 | .trigger = { |
| 734 | SND_SOC_DPCM_TRIGGER_POST, |
| 735 | SND_SOC_DPCM_TRIGGER_POST, |
| 736 | }, |
| 737 | .dynamic = 1, |
| 738 | .dpcm_playback = 1, |
| 739 | .ops = &mt8195_playback_ops, |
| 740 | SND_SOC_DAILINK_REG(DL6_FE), |
| 741 | }, |
| 742 | [DAI_LINK_DL7_FE] = { |
| 743 | .name = "DL7_FE", |
| 744 | .stream_name = "DL7 Playback", |
| 745 | .trigger = { |
| 746 | SND_SOC_DPCM_TRIGGER_PRE, |
| 747 | SND_SOC_DPCM_TRIGGER_PRE, |
| 748 | }, |
| 749 | .dynamic = 1, |
| 750 | .dpcm_playback = 1, |
| 751 | SND_SOC_DAILINK_REG(DL7_FE), |
| 752 | }, |
| 753 | [DAI_LINK_DL8_FE] = { |
| 754 | .name = "DL8_FE", |
| 755 | .stream_name = "DL8 Playback", |
| 756 | .trigger = { |
| 757 | SND_SOC_DPCM_TRIGGER_POST, |
| 758 | SND_SOC_DPCM_TRIGGER_POST, |
| 759 | }, |
| 760 | .dynamic = 1, |
| 761 | .dpcm_playback = 1, |
| 762 | .ops = &mt8195_playback_ops, |
| 763 | SND_SOC_DAILINK_REG(DL8_FE), |
| 764 | }, |
| 765 | [DAI_LINK_DL10_FE] = { |
| 766 | .name = "DL10_FE", |
| 767 | .stream_name = "DL10 Playback", |
| 768 | .trigger = { |
| 769 | SND_SOC_DPCM_TRIGGER_POST, |
| 770 | SND_SOC_DPCM_TRIGGER_POST, |
| 771 | }, |
| 772 | .dynamic = 1, |
| 773 | .dpcm_playback = 1, |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 774 | .ops = &mt8195_hdmitx_dptx_playback_ops, |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 775 | SND_SOC_DAILINK_REG(DL10_FE), |
| 776 | }, |
| 777 | [DAI_LINK_DL11_FE] = { |
| 778 | .name = "DL11_FE", |
| 779 | .stream_name = "DL11 Playback", |
| 780 | .trigger = { |
| 781 | SND_SOC_DPCM_TRIGGER_POST, |
| 782 | SND_SOC_DPCM_TRIGGER_POST, |
| 783 | }, |
| 784 | .dynamic = 1, |
| 785 | .dpcm_playback = 1, |
| 786 | .ops = &mt8195_playback_ops, |
| 787 | SND_SOC_DAILINK_REG(DL11_FE), |
| 788 | }, |
| 789 | [DAI_LINK_UL1_FE] = { |
| 790 | .name = "UL1_FE", |
| 791 | .stream_name = "UL1 Capture", |
| 792 | .trigger = { |
| 793 | SND_SOC_DPCM_TRIGGER_PRE, |
| 794 | SND_SOC_DPCM_TRIGGER_PRE, |
| 795 | }, |
| 796 | .dynamic = 1, |
| 797 | .dpcm_capture = 1, |
| 798 | SND_SOC_DAILINK_REG(UL1_FE), |
| 799 | }, |
| 800 | [DAI_LINK_UL2_FE] = { |
| 801 | .name = "UL2_FE", |
| 802 | .stream_name = "UL2 Capture", |
| 803 | .trigger = { |
| 804 | SND_SOC_DPCM_TRIGGER_POST, |
| 805 | SND_SOC_DPCM_TRIGGER_POST, |
| 806 | }, |
| 807 | .dynamic = 1, |
| 808 | .dpcm_capture = 1, |
| 809 | .ops = &mt8195_capture_ops, |
| 810 | SND_SOC_DAILINK_REG(UL2_FE), |
| 811 | }, |
| 812 | [DAI_LINK_UL3_FE] = { |
| 813 | .name = "UL3_FE", |
| 814 | .stream_name = "UL3 Capture", |
| 815 | .trigger = { |
| 816 | SND_SOC_DPCM_TRIGGER_POST, |
| 817 | SND_SOC_DPCM_TRIGGER_POST, |
| 818 | }, |
| 819 | .dynamic = 1, |
| 820 | .dpcm_capture = 1, |
| 821 | .ops = &mt8195_capture_ops, |
| 822 | SND_SOC_DAILINK_REG(UL3_FE), |
| 823 | }, |
| 824 | [DAI_LINK_UL4_FE] = { |
| 825 | .name = "UL4_FE", |
| 826 | .stream_name = "UL4 Capture", |
| 827 | .trigger = { |
| 828 | SND_SOC_DPCM_TRIGGER_POST, |
| 829 | SND_SOC_DPCM_TRIGGER_POST, |
| 830 | }, |
| 831 | .dynamic = 1, |
| 832 | .dpcm_capture = 1, |
| 833 | .ops = &mt8195_capture_ops, |
| 834 | SND_SOC_DAILINK_REG(UL4_FE), |
| 835 | }, |
| 836 | [DAI_LINK_UL5_FE] = { |
| 837 | .name = "UL5_FE", |
| 838 | .stream_name = "UL5 Capture", |
| 839 | .trigger = { |
| 840 | SND_SOC_DPCM_TRIGGER_POST, |
| 841 | SND_SOC_DPCM_TRIGGER_POST, |
| 842 | }, |
| 843 | .dynamic = 1, |
| 844 | .dpcm_capture = 1, |
| 845 | .ops = &mt8195_capture_ops, |
| 846 | SND_SOC_DAILINK_REG(UL5_FE), |
| 847 | }, |
| 848 | [DAI_LINK_UL6_FE] = { |
| 849 | .name = "UL6_FE", |
| 850 | .stream_name = "UL6 Capture", |
| 851 | .trigger = { |
| 852 | SND_SOC_DPCM_TRIGGER_PRE, |
| 853 | SND_SOC_DPCM_TRIGGER_PRE, |
| 854 | }, |
| 855 | .dynamic = 1, |
| 856 | .dpcm_capture = 1, |
| 857 | SND_SOC_DAILINK_REG(UL6_FE), |
| 858 | }, |
| 859 | [DAI_LINK_UL8_FE] = { |
| 860 | .name = "UL8_FE", |
| 861 | .stream_name = "UL8 Capture", |
| 862 | .trigger = { |
| 863 | SND_SOC_DPCM_TRIGGER_POST, |
| 864 | SND_SOC_DPCM_TRIGGER_POST, |
| 865 | }, |
| 866 | .dynamic = 1, |
| 867 | .dpcm_capture = 1, |
| 868 | .ops = &mt8195_capture_ops, |
| 869 | SND_SOC_DAILINK_REG(UL8_FE), |
| 870 | }, |
| 871 | [DAI_LINK_UL9_FE] = { |
| 872 | .name = "UL9_FE", |
| 873 | .stream_name = "UL9 Capture", |
| 874 | .trigger = { |
| 875 | SND_SOC_DPCM_TRIGGER_POST, |
| 876 | SND_SOC_DPCM_TRIGGER_POST, |
| 877 | }, |
| 878 | .dynamic = 1, |
| 879 | .dpcm_capture = 1, |
| 880 | .ops = &mt8195_capture_ops, |
| 881 | SND_SOC_DAILINK_REG(UL9_FE), |
| 882 | }, |
| 883 | [DAI_LINK_UL10_FE] = { |
| 884 | .name = "UL10_FE", |
| 885 | .stream_name = "UL10 Capture", |
| 886 | .trigger = { |
| 887 | SND_SOC_DPCM_TRIGGER_POST, |
| 888 | SND_SOC_DPCM_TRIGGER_POST, |
| 889 | }, |
| 890 | .dynamic = 1, |
| 891 | .dpcm_capture = 1, |
| 892 | .ops = &mt8195_capture_ops, |
| 893 | SND_SOC_DAILINK_REG(UL10_FE), |
| 894 | }, |
| 895 | /* BE */ |
| 896 | [DAI_LINK_DL_SRC_BE] = { |
| 897 | .name = "DL_SRC_BE", |
| 898 | .init = mt8195_mt6359_init, |
| 899 | .no_pcm = 1, |
| 900 | .dpcm_playback = 1, |
| 901 | SND_SOC_DAILINK_REG(DL_SRC_BE), |
| 902 | }, |
| 903 | [DAI_LINK_DPTX_BE] = { |
| 904 | .name = "DPTX_BE", |
| 905 | .no_pcm = 1, |
| 906 | .dpcm_playback = 1, |
| 907 | .ops = &mt8195_dptx_ops, |
Trevor Wu | 3abe2ee | 2021-09-17 16:28:05 +0800 | [diff] [blame] | 908 | .be_hw_params_fixup = mt8195_dptx_hw_params_fixup, |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 909 | SND_SOC_DAILINK_REG(DPTX_BE), |
| 910 | }, |
| 911 | [DAI_LINK_ETDM1_IN_BE] = { |
| 912 | .name = "ETDM1_IN_BE", |
| 913 | .no_pcm = 1, |
| 914 | .dai_fmt = SND_SOC_DAIFMT_I2S | |
| 915 | SND_SOC_DAIFMT_NB_NF | |
| 916 | SND_SOC_DAIFMT_CBS_CFS, |
| 917 | .dpcm_capture = 1, |
| 918 | SND_SOC_DAILINK_REG(ETDM1_IN_BE), |
| 919 | }, |
| 920 | [DAI_LINK_ETDM2_IN_BE] = { |
| 921 | .name = "ETDM2_IN_BE", |
| 922 | .no_pcm = 1, |
| 923 | .dai_fmt = SND_SOC_DAIFMT_I2S | |
| 924 | SND_SOC_DAIFMT_NB_NF | |
| 925 | SND_SOC_DAIFMT_CBS_CFS, |
| 926 | .dpcm_capture = 1, |
| 927 | .init = mt8195_rt5682_init, |
| 928 | .ops = &mt8195_rt5682_etdm_ops, |
| 929 | .be_hw_params_fixup = mt8195_etdm_hw_params_fixup, |
| 930 | SND_SOC_DAILINK_REG(ETDM2_IN_BE), |
| 931 | }, |
| 932 | [DAI_LINK_ETDM1_OUT_BE] = { |
| 933 | .name = "ETDM1_OUT_BE", |
| 934 | .no_pcm = 1, |
| 935 | .dai_fmt = SND_SOC_DAIFMT_I2S | |
| 936 | SND_SOC_DAIFMT_NB_NF | |
| 937 | SND_SOC_DAIFMT_CBS_CFS, |
| 938 | .dpcm_playback = 1, |
| 939 | .ops = &mt8195_rt5682_etdm_ops, |
| 940 | .be_hw_params_fixup = mt8195_etdm_hw_params_fixup, |
| 941 | SND_SOC_DAILINK_REG(ETDM1_OUT_BE), |
| 942 | }, |
| 943 | [DAI_LINK_ETDM2_OUT_BE] = { |
| 944 | .name = "ETDM2_OUT_BE", |
| 945 | .no_pcm = 1, |
| 946 | .dai_fmt = SND_SOC_DAIFMT_I2S | |
| 947 | SND_SOC_DAIFMT_NB_NF | |
| 948 | SND_SOC_DAIFMT_CBS_CFS, |
| 949 | .dpcm_playback = 1, |
| 950 | SND_SOC_DAILINK_REG(ETDM2_OUT_BE), |
| 951 | }, |
| 952 | [DAI_LINK_ETDM3_OUT_BE] = { |
| 953 | .name = "ETDM3_OUT_BE", |
| 954 | .no_pcm = 1, |
| 955 | .dai_fmt = SND_SOC_DAIFMT_I2S | |
| 956 | SND_SOC_DAIFMT_NB_NF | |
| 957 | SND_SOC_DAIFMT_CBS_CFS, |
| 958 | .dpcm_playback = 1, |
| 959 | SND_SOC_DAILINK_REG(ETDM3_OUT_BE), |
| 960 | }, |
| 961 | [DAI_LINK_PCM1_BE] = { |
| 962 | .name = "PCM1_BE", |
| 963 | .no_pcm = 1, |
| 964 | .dai_fmt = SND_SOC_DAIFMT_I2S | |
| 965 | SND_SOC_DAIFMT_NB_NF | |
| 966 | SND_SOC_DAIFMT_CBS_CFS, |
| 967 | .dpcm_capture = 1, |
| 968 | SND_SOC_DAILINK_REG(PCM1_BE), |
| 969 | }, |
| 970 | [DAI_LINK_UL_SRC1_BE] = { |
| 971 | .name = "UL_SRC1_BE", |
| 972 | .no_pcm = 1, |
| 973 | .dpcm_capture = 1, |
| 974 | SND_SOC_DAILINK_REG(UL_SRC1_BE), |
| 975 | }, |
| 976 | [DAI_LINK_UL_SRC2_BE] = { |
| 977 | .name = "UL_SRC2_BE", |
| 978 | .no_pcm = 1, |
| 979 | .dpcm_capture = 1, |
| 980 | SND_SOC_DAILINK_REG(UL_SRC2_BE), |
| 981 | }, |
| 982 | }; |
| 983 | |
| 984 | static struct snd_soc_card mt8195_mt6359_rt1019_rt5682_soc_card = { |
| 985 | .name = "mt8195_r1019_5682", |
| 986 | .owner = THIS_MODULE, |
| 987 | .dai_link = mt8195_mt6359_rt1019_rt5682_dai_links, |
| 988 | .num_links = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_dai_links), |
| 989 | .controls = mt8195_mt6359_rt1019_rt5682_controls, |
| 990 | .num_controls = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_controls), |
| 991 | .dapm_widgets = mt8195_mt6359_rt1019_rt5682_widgets, |
| 992 | .num_dapm_widgets = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_widgets), |
| 993 | .dapm_routes = mt8195_mt6359_rt1019_rt5682_routes, |
| 994 | .num_dapm_routes = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_routes), |
| 995 | }; |
| 996 | |
| 997 | static int mt8195_mt6359_rt1019_rt5682_dev_probe(struct platform_device *pdev) |
| 998 | { |
| 999 | struct snd_soc_card *card = &mt8195_mt6359_rt1019_rt5682_soc_card; |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1000 | struct snd_soc_dai_link *dai_link; |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1001 | struct mt8195_mt6359_rt1019_rt5682_priv *priv; |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1002 | int ret, i; |
| 1003 | |
| 1004 | card->dev = &pdev->dev; |
| 1005 | |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1006 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 1007 | if (!priv) |
| 1008 | return -ENOMEM; |
| 1009 | |
| 1010 | priv->platform_node = of_parse_phandle(pdev->dev.of_node, |
| 1011 | "mediatek,platform", 0); |
| 1012 | if (!priv->platform_node) { |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1013 | dev_dbg(&pdev->dev, "Property 'platform' missing or invalid\n"); |
| 1014 | return -EINVAL; |
| 1015 | } |
| 1016 | |
| 1017 | for_each_card_prelinks(card, i, dai_link) { |
| 1018 | if (!dai_link->platforms->name) |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1019 | dai_link->platforms->of_node = priv->platform_node; |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 1020 | |
| 1021 | if (strcmp(dai_link->name, "DPTX_BE") == 0) { |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1022 | priv->dp_node = |
| 1023 | of_parse_phandle(pdev->dev.of_node, |
| 1024 | "mediatek,dptx-codec", 0); |
| 1025 | |
| 1026 | if (!priv->dp_node) { |
Trevor Wu | 7eac1e2 | 2021-09-03 14:00:49 +0800 | [diff] [blame] | 1027 | dev_dbg(&pdev->dev, "No property 'dptx-codec'\n"); |
| 1028 | } else { |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1029 | dai_link->codecs->of_node = priv->dp_node; |
Trevor Wu | 7eac1e2 | 2021-09-03 14:00:49 +0800 | [diff] [blame] | 1030 | dai_link->codecs->name = NULL; |
| 1031 | dai_link->codecs->dai_name = "i2s-hifi"; |
| 1032 | dai_link->init = mt8195_dptx_codec_init; |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 1033 | } |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 1034 | } |
Trevor Wu | ef46cd4 | 2021-08-19 16:41:43 +0800 | [diff] [blame] | 1035 | |
| 1036 | if (strcmp(dai_link->name, "ETDM3_OUT_BE") == 0) { |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1037 | priv->hdmi_node = |
| 1038 | of_parse_phandle(pdev->dev.of_node, |
| 1039 | "mediatek,hdmi-codec", 0); |
| 1040 | if (!priv->hdmi_node) { |
Trevor Wu | 7eac1e2 | 2021-09-03 14:00:49 +0800 | [diff] [blame] | 1041 | dev_dbg(&pdev->dev, "No property 'hdmi-codec'\n"); |
| 1042 | } else { |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1043 | dai_link->codecs->of_node = priv->hdmi_node; |
Trevor Wu | 7eac1e2 | 2021-09-03 14:00:49 +0800 | [diff] [blame] | 1044 | dai_link->codecs->name = NULL; |
| 1045 | dai_link->codecs->dai_name = "i2s-hifi"; |
| 1046 | dai_link->init = mt8195_hdmi_codec_init; |
Trevor Wu | ef46cd4 | 2021-08-19 16:41:43 +0800 | [diff] [blame] | 1047 | } |
Trevor Wu | ef46cd4 | 2021-08-19 16:41:43 +0800 | [diff] [blame] | 1048 | } |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1049 | } |
| 1050 | |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1051 | snd_soc_card_set_drvdata(card, priv); |
| 1052 | |
| 1053 | ret = devm_snd_soc_register_card(&pdev->dev, card); |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1054 | if (ret) { |
Trevor Wu | e581e30 | 2021-08-19 16:41:42 +0800 | [diff] [blame] | 1055 | dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n", |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1056 | __func__, ret); |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1057 | of_node_put(priv->hdmi_node); |
| 1058 | of_node_put(priv->dp_node); |
| 1059 | of_node_put(priv->platform_node); |
| 1060 | } |
Bixuan Cui | b2fc2c9 | 2021-09-11 16:12:46 +0800 | [diff] [blame] | 1061 | |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1062 | return ret; |
| 1063 | } |
| 1064 | |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1065 | static int mt8195_mt6359_rt1019_rt5682_dev_remove(struct platform_device *pdev) |
| 1066 | { |
| 1067 | struct snd_soc_card *card = platform_get_drvdata(pdev); |
| 1068 | struct mt8195_mt6359_rt1019_rt5682_priv *priv = |
| 1069 | snd_soc_card_get_drvdata(card); |
| 1070 | |
| 1071 | of_node_put(priv->hdmi_node); |
| 1072 | of_node_put(priv->dp_node); |
| 1073 | of_node_put(priv->platform_node); |
| 1074 | |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1078 | #ifdef CONFIG_OF |
| 1079 | static const struct of_device_id mt8195_mt6359_rt1019_rt5682_dt_match[] = { |
| 1080 | {.compatible = "mediatek,mt8195_mt6359_rt1019_rt5682",}, |
| 1081 | {} |
| 1082 | }; |
| 1083 | #endif |
| 1084 | |
| 1085 | static const struct dev_pm_ops mt8195_mt6359_rt1019_rt5682_pm_ops = { |
| 1086 | .poweroff = snd_soc_poweroff, |
| 1087 | .restore = snd_soc_resume, |
| 1088 | }; |
| 1089 | |
| 1090 | static struct platform_driver mt8195_mt6359_rt1019_rt5682_driver = { |
| 1091 | .driver = { |
| 1092 | .name = "mt8195_mt6359_rt1019_rt5682", |
| 1093 | #ifdef CONFIG_OF |
| 1094 | .of_match_table = mt8195_mt6359_rt1019_rt5682_dt_match, |
| 1095 | #endif |
| 1096 | .pm = &mt8195_mt6359_rt1019_rt5682_pm_ops, |
| 1097 | }, |
| 1098 | .probe = mt8195_mt6359_rt1019_rt5682_dev_probe, |
Trevor Wu | bd8bec1 | 2021-10-01 11:16:01 +0800 | [diff] [blame] | 1099 | .remove = mt8195_mt6359_rt1019_rt5682_dev_remove, |
Trevor Wu | 40d605d | 2021-08-19 16:41:41 +0800 | [diff] [blame] | 1100 | }; |
| 1101 | |
| 1102 | module_platform_driver(mt8195_mt6359_rt1019_rt5682_driver); |
| 1103 | |
| 1104 | /* Module information */ |
| 1105 | MODULE_DESCRIPTION("MT8195-MT6359-RT1019-RT5682 ALSA SoC machine driver"); |
| 1106 | MODULE_AUTHOR("Trevor Wu <trevor.wu@mediatek.com>"); |
| 1107 | MODULE_LICENSE("GPL v2"); |
| 1108 | MODULE_ALIAS("mt8195_mt6359_rt1019_rt5682 soc card"); |