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Thomas Gleixnerc942fdd2019-05-27 08:55:06 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Sascha Hauera5fd9132009-01-07 18:08:58 -08002/*
3 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Luotao Fu, kernel@pengutronix.de
Sascha Hauera5fd9132009-01-07 18:08:58 -08005 */
6
Sascha Hauera5fd9132009-01-07 18:08:58 -08007#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/io.h>
Martin Fuzzeyc9723752020-09-30 10:36:46 +020010#include <linux/ktime.h>
Alexander Shiyan18fd9e3592014-02-22 11:29:50 +040011#include <linux/module.h>
Randy Dunlapac316722018-06-19 22:47:28 -070012#include <linux/mod_devicetable.h>
Alexander Shiyan18fd9e3592014-02-22 11:29:50 +040013#include <linux/platform_device.h>
Sascha Hauera5fd9132009-01-07 18:08:58 -080014
Andrew F. Davisde0d6db2017-06-05 08:52:08 -050015#include <linux/w1.h>
Sascha Hauera5fd9132009-01-07 18:08:58 -080016
Sascha Hauera5fd9132009-01-07 18:08:58 -080017/*
18 * MXC W1 Register offsets
19 */
Alexander Shiyan18fd9e3592014-02-22 11:29:50 +040020#define MXC_W1_CONTROL 0x00
21# define MXC_W1_CONTROL_RDST BIT(3)
22# define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
23# define MXC_W1_CONTROL_PST BIT(6)
24# define MXC_W1_CONTROL_RPP BIT(7)
25#define MXC_W1_TIME_DIVIDER 0x02
26#define MXC_W1_RESET 0x04
Alexander Shiyanb7ce0b52014-05-08 11:56:39 +040027# define MXC_W1_RESET_RST BIT(0)
Sascha Hauera5fd9132009-01-07 18:08:58 -080028
29struct mxc_w1_device {
30 void __iomem *regs;
Sascha Hauera5fd9132009-01-07 18:08:58 -080031 struct clk *clk;
32 struct w1_bus_master bus_master;
33};
34
35/*
36 * this is the low level routine to
37 * reset the device on the One Wire interface
38 * on the hardware
39 */
40static u8 mxc_w1_ds2_reset_bus(void *data)
41{
Sascha Hauera5fd9132009-01-07 18:08:58 -080042 struct mxc_w1_device *dev = data;
Martin Fuzzeyc9723752020-09-30 10:36:46 +020043 ktime_t timeout;
Sascha Hauera5fd9132009-01-07 18:08:58 -080044
Alexander Shiyanb0dceb62014-05-08 11:56:38 +040045 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
Sascha Hauera5fd9132009-01-07 18:08:58 -080046
Alexander Shiyanb0dceb62014-05-08 11:56:38 +040047 /* Wait for reset sequence 511+512us, use 1500us for sure */
Martin Fuzzeyc9723752020-09-30 10:36:46 +020048 timeout = ktime_add_us(ktime_get(), 1500);
Sascha Hauera5fd9132009-01-07 18:08:58 -080049
Alexander Shiyanb0dceb62014-05-08 11:56:38 +040050 udelay(511 + 512);
Sascha Hauera5fd9132009-01-07 18:08:58 -080051
Alexander Shiyanb0dceb62014-05-08 11:56:38 +040052 do {
53 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
54
55 /* PST bit is valid after the RPP bit is self-cleared */
56 if (!(ctrl & MXC_W1_CONTROL_RPP))
57 return !(ctrl & MXC_W1_CONTROL_PST);
Martin Fuzzeyc9723752020-09-30 10:36:46 +020058 } while (ktime_before(ktime_get(), timeout));
Alexander Shiyanb0dceb62014-05-08 11:56:38 +040059
60 return 1;
Sascha Hauera5fd9132009-01-07 18:08:58 -080061}
62
63/*
64 * this is the low level routine to read/write a bit on the One Wire
65 * interface on the hardware. It does write 0 if parameter bit is set
66 * to 0, otherwise a write 1/read.
67 */
68static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
69{
Alexander Shiyanf80b2582014-05-08 11:56:40 +040070 struct mxc_w1_device *dev = data;
Martin Fuzzeyc9723752020-09-30 10:36:46 +020071 ktime_t timeout;
Sascha Hauera5fd9132009-01-07 18:08:58 -080072
Alexander Shiyanf80b2582014-05-08 11:56:40 +040073 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
Sascha Hauera5fd9132009-01-07 18:08:58 -080074
Alexander Shiyanf80b2582014-05-08 11:56:40 +040075 /* Wait for read/write bit (60us, Max 120us), use 200us for sure */
Martin Fuzzeyc9723752020-09-30 10:36:46 +020076 timeout = ktime_add_us(ktime_get(), 200);
Sascha Hauera5fd9132009-01-07 18:08:58 -080077
Alexander Shiyanf80b2582014-05-08 11:56:40 +040078 udelay(60);
Sascha Hauera5fd9132009-01-07 18:08:58 -080079
Alexander Shiyanf80b2582014-05-08 11:56:40 +040080 do {
81 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
82
83 /* RDST bit is valid after the WR1/RD bit is self-cleared */
84 if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
85 return !!(ctrl & MXC_W1_CONTROL_RDST);
Martin Fuzzeyc9723752020-09-30 10:36:46 +020086 } while (ktime_before(ktime_get(), timeout));
Alexander Shiyanf80b2582014-05-08 11:56:40 +040087
88 return 0;
Sascha Hauera5fd9132009-01-07 18:08:58 -080089}
90
Bill Pemberton479e2bc2012-11-19 13:21:43 -050091static int mxc_w1_probe(struct platform_device *pdev)
Sascha Hauera5fd9132009-01-07 18:08:58 -080092{
93 struct mxc_w1_device *mdev;
Alexander Shiyan71531f52013-11-29 15:39:29 +040094 unsigned long clkrate;
Alexander Shiyana0822632013-11-29 15:39:28 +040095 unsigned int clkdiv;
Alexander Shiyan001d1952013-11-29 15:39:30 +040096 int err;
Sascha Hauera5fd9132009-01-07 18:08:58 -080097
Julia Lawalle5279ff2012-12-07 00:15:24 +010098 mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
99 GFP_KERNEL);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800100 if (!mdev)
101 return -ENOMEM;
102
Julia Lawalle5279ff2012-12-07 00:15:24 +0100103 mdev->clk = devm_clk_get(&pdev->dev, NULL);
104 if (IS_ERR(mdev->clk))
105 return PTR_ERR(mdev->clk);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800106
Stefan Potyra955bc612018-05-02 10:55:31 +0200107 err = clk_prepare_enable(mdev->clk);
108 if (err)
109 return err;
110
Alexander Shiyan71531f52013-11-29 15:39:29 +0400111 clkrate = clk_get_rate(mdev->clk);
112 if (clkrate < 10000000)
113 dev_warn(&pdev->dev,
114 "Low clock frequency causes improper function\n");
115
116 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
117 clkrate /= clkdiv;
118 if ((clkrate < 980000) || (clkrate > 1020000))
119 dev_warn(&pdev->dev,
120 "Incorrect time base frequency %lu Hz\n", clkrate);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800121
YueHaibingb0a523f2019-08-02 21:48:19 +0800122 mdev->regs = devm_platform_ioremap_resource(pdev, 0);
Stefan Potyra955bc612018-05-02 10:55:31 +0200123 if (IS_ERR(mdev->regs)) {
124 err = PTR_ERR(mdev->regs);
125 goto out_disable_clk;
126 }
Alexander Shiyan001d1952013-11-29 15:39:30 +0400127
Alexander Shiyanb7ce0b52014-05-08 11:56:39 +0400128 /* Software reset 1-Wire module */
129 writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
130 writeb(0, mdev->regs + MXC_W1_RESET);
131
Alexander Shiyanfc945d62014-02-22 11:29:51 +0400132 writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800133
134 mdev->bus_master.data = mdev;
135 mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
136 mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
137
Sascha Hauera5fd9132009-01-07 18:08:58 -0800138 platform_set_drvdata(pdev, mdev);
Alexander Shiyan001d1952013-11-29 15:39:30 +0400139
140 err = w1_add_master_device(&mdev->bus_master);
141 if (err)
Stefan Potyra955bc612018-05-02 10:55:31 +0200142 goto out_disable_clk;
Alexander Shiyan001d1952013-11-29 15:39:30 +0400143
Stefan Potyra955bc612018-05-02 10:55:31 +0200144 return 0;
145
146out_disable_clk:
147 clk_disable_unprepare(mdev->clk);
Alexander Shiyan001d1952013-11-29 15:39:30 +0400148 return err;
Sascha Hauera5fd9132009-01-07 18:08:58 -0800149}
150
151/*
152 * disassociate the w1 device from the driver
153 */
Bill Pemberton82849a92012-11-19 13:26:23 -0500154static int mxc_w1_remove(struct platform_device *pdev)
Sascha Hauera5fd9132009-01-07 18:08:58 -0800155{
156 struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800157
158 w1_remove_master_device(&mdev->bus_master);
159
Sascha Hauer60178b62012-03-07 20:59:36 +0100160 clk_disable_unprepare(mdev->clk);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800161
Sascha Hauera5fd9132009-01-07 18:08:58 -0800162 return 0;
163}
164
Fabian Frederick0a56c0e2015-03-16 20:20:29 +0100165static const struct of_device_id mxc_w1_dt_ids[] = {
Martin Fuzzey28c55dc2013-01-29 16:46:10 +0100166 { .compatible = "fsl,imx21-owire" },
167 { /* sentinel */ }
168};
169MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
170
Sascha Hauera5fd9132009-01-07 18:08:58 -0800171static struct platform_driver mxc_w1_driver = {
172 .driver = {
Martin Fuzzey28c55dc2013-01-29 16:46:10 +0100173 .name = "mxc_w1",
174 .of_match_table = mxc_w1_dt_ids,
Sascha Hauera5fd9132009-01-07 18:08:58 -0800175 },
176 .probe = mxc_w1_probe,
Greg Kroah-Hartman10532fe2012-12-21 12:55:26 -0800177 .remove = mxc_w1_remove,
Sascha Hauera5fd9132009-01-07 18:08:58 -0800178};
Fabio Estevamfd21bfc2012-11-19 10:19:48 -0200179module_platform_driver(mxc_w1_driver);
Sascha Hauera5fd9132009-01-07 18:08:58 -0800180
181MODULE_LICENSE("GPL");
182MODULE_AUTHOR("Freescale Semiconductors Inc");
183MODULE_DESCRIPTION("Driver for One-Wire on MXC");