Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. |
| 4 | * Copyright 2008 Luotao Fu, kernel@pengutronix.de |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 7 | #include <linux/clk.h> |
| 8 | #include <linux/delay.h> |
| 9 | #include <linux/io.h> |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 10 | #include <linux/ktime.h> |
Alexander Shiyan | 18fd9e359 | 2014-02-22 11:29:50 +0400 | [diff] [blame] | 11 | #include <linux/module.h> |
Randy Dunlap | ac31672 | 2018-06-19 22:47:28 -0700 | [diff] [blame] | 12 | #include <linux/mod_devicetable.h> |
Alexander Shiyan | 18fd9e359 | 2014-02-22 11:29:50 +0400 | [diff] [blame] | 13 | #include <linux/platform_device.h> |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 14 | |
Andrew F. Davis | de0d6db | 2017-06-05 08:52:08 -0500 | [diff] [blame] | 15 | #include <linux/w1.h> |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 16 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 17 | /* |
| 18 | * MXC W1 Register offsets |
| 19 | */ |
Alexander Shiyan | 18fd9e359 | 2014-02-22 11:29:50 +0400 | [diff] [blame] | 20 | #define MXC_W1_CONTROL 0x00 |
| 21 | # define MXC_W1_CONTROL_RDST BIT(3) |
| 22 | # define MXC_W1_CONTROL_WR(x) BIT(5 - (x)) |
| 23 | # define MXC_W1_CONTROL_PST BIT(6) |
| 24 | # define MXC_W1_CONTROL_RPP BIT(7) |
| 25 | #define MXC_W1_TIME_DIVIDER 0x02 |
| 26 | #define MXC_W1_RESET 0x04 |
Alexander Shiyan | b7ce0b5 | 2014-05-08 11:56:39 +0400 | [diff] [blame] | 27 | # define MXC_W1_RESET_RST BIT(0) |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 28 | |
| 29 | struct mxc_w1_device { |
| 30 | void __iomem *regs; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 31 | struct clk *clk; |
| 32 | struct w1_bus_master bus_master; |
| 33 | }; |
| 34 | |
| 35 | /* |
| 36 | * this is the low level routine to |
| 37 | * reset the device on the One Wire interface |
| 38 | * on the hardware |
| 39 | */ |
| 40 | static u8 mxc_w1_ds2_reset_bus(void *data) |
| 41 | { |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 42 | struct mxc_w1_device *dev = data; |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 43 | ktime_t timeout; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 44 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 45 | writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 46 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 47 | /* Wait for reset sequence 511+512us, use 1500us for sure */ |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 48 | timeout = ktime_add_us(ktime_get(), 1500); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 49 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 50 | udelay(511 + 512); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 51 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 52 | do { |
| 53 | u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); |
| 54 | |
| 55 | /* PST bit is valid after the RPP bit is self-cleared */ |
| 56 | if (!(ctrl & MXC_W1_CONTROL_RPP)) |
| 57 | return !(ctrl & MXC_W1_CONTROL_PST); |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 58 | } while (ktime_before(ktime_get(), timeout)); |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 59 | |
| 60 | return 1; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | /* |
| 64 | * this is the low level routine to read/write a bit on the One Wire |
| 65 | * interface on the hardware. It does write 0 if parameter bit is set |
| 66 | * to 0, otherwise a write 1/read. |
| 67 | */ |
| 68 | static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit) |
| 69 | { |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 70 | struct mxc_w1_device *dev = data; |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 71 | ktime_t timeout; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 72 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 73 | writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 74 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 75 | /* Wait for read/write bit (60us, Max 120us), use 200us for sure */ |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 76 | timeout = ktime_add_us(ktime_get(), 200); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 77 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 78 | udelay(60); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 79 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 80 | do { |
| 81 | u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); |
| 82 | |
| 83 | /* RDST bit is valid after the WR1/RD bit is self-cleared */ |
| 84 | if (!(ctrl & MXC_W1_CONTROL_WR(bit))) |
| 85 | return !!(ctrl & MXC_W1_CONTROL_RDST); |
Martin Fuzzey | c972375 | 2020-09-30 10:36:46 +0200 | [diff] [blame] | 86 | } while (ktime_before(ktime_get(), timeout)); |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 87 | |
| 88 | return 0; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 89 | } |
| 90 | |
Bill Pemberton | 479e2bc | 2012-11-19 13:21:43 -0500 | [diff] [blame] | 91 | static int mxc_w1_probe(struct platform_device *pdev) |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 92 | { |
| 93 | struct mxc_w1_device *mdev; |
Alexander Shiyan | 71531f5 | 2013-11-29 15:39:29 +0400 | [diff] [blame] | 94 | unsigned long clkrate; |
Alexander Shiyan | a082263 | 2013-11-29 15:39:28 +0400 | [diff] [blame] | 95 | unsigned int clkdiv; |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 96 | int err; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 97 | |
Julia Lawall | e5279ff | 2012-12-07 00:15:24 +0100 | [diff] [blame] | 98 | mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device), |
| 99 | GFP_KERNEL); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 100 | if (!mdev) |
| 101 | return -ENOMEM; |
| 102 | |
Julia Lawall | e5279ff | 2012-12-07 00:15:24 +0100 | [diff] [blame] | 103 | mdev->clk = devm_clk_get(&pdev->dev, NULL); |
| 104 | if (IS_ERR(mdev->clk)) |
| 105 | return PTR_ERR(mdev->clk); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 106 | |
Stefan Potyra | 955bc61 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 107 | err = clk_prepare_enable(mdev->clk); |
| 108 | if (err) |
| 109 | return err; |
| 110 | |
Alexander Shiyan | 71531f5 | 2013-11-29 15:39:29 +0400 | [diff] [blame] | 111 | clkrate = clk_get_rate(mdev->clk); |
| 112 | if (clkrate < 10000000) |
| 113 | dev_warn(&pdev->dev, |
| 114 | "Low clock frequency causes improper function\n"); |
| 115 | |
| 116 | clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); |
| 117 | clkrate /= clkdiv; |
| 118 | if ((clkrate < 980000) || (clkrate > 1020000)) |
| 119 | dev_warn(&pdev->dev, |
| 120 | "Incorrect time base frequency %lu Hz\n", clkrate); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 121 | |
YueHaibing | b0a523f | 2019-08-02 21:48:19 +0800 | [diff] [blame] | 122 | mdev->regs = devm_platform_ioremap_resource(pdev, 0); |
Stefan Potyra | 955bc61 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 123 | if (IS_ERR(mdev->regs)) { |
| 124 | err = PTR_ERR(mdev->regs); |
| 125 | goto out_disable_clk; |
| 126 | } |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 127 | |
Alexander Shiyan | b7ce0b5 | 2014-05-08 11:56:39 +0400 | [diff] [blame] | 128 | /* Software reset 1-Wire module */ |
| 129 | writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET); |
| 130 | writeb(0, mdev->regs + MXC_W1_RESET); |
| 131 | |
Alexander Shiyan | fc945d6 | 2014-02-22 11:29:51 +0400 | [diff] [blame] | 132 | writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 133 | |
| 134 | mdev->bus_master.data = mdev; |
| 135 | mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus; |
| 136 | mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit; |
| 137 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 138 | platform_set_drvdata(pdev, mdev); |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 139 | |
| 140 | err = w1_add_master_device(&mdev->bus_master); |
| 141 | if (err) |
Stefan Potyra | 955bc61 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 142 | goto out_disable_clk; |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 143 | |
Stefan Potyra | 955bc61 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 144 | return 0; |
| 145 | |
| 146 | out_disable_clk: |
| 147 | clk_disable_unprepare(mdev->clk); |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 148 | return err; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /* |
| 152 | * disassociate the w1 device from the driver |
| 153 | */ |
Bill Pemberton | 82849a9 | 2012-11-19 13:26:23 -0500 | [diff] [blame] | 154 | static int mxc_w1_remove(struct platform_device *pdev) |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 155 | { |
| 156 | struct mxc_w1_device *mdev = platform_get_drvdata(pdev); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 157 | |
| 158 | w1_remove_master_device(&mdev->bus_master); |
| 159 | |
Sascha Hauer | 60178b6 | 2012-03-07 20:59:36 +0100 | [diff] [blame] | 160 | clk_disable_unprepare(mdev->clk); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 161 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 162 | return 0; |
| 163 | } |
| 164 | |
Fabian Frederick | 0a56c0e | 2015-03-16 20:20:29 +0100 | [diff] [blame] | 165 | static const struct of_device_id mxc_w1_dt_ids[] = { |
Martin Fuzzey | 28c55dc | 2013-01-29 16:46:10 +0100 | [diff] [blame] | 166 | { .compatible = "fsl,imx21-owire" }, |
| 167 | { /* sentinel */ } |
| 168 | }; |
| 169 | MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids); |
| 170 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 171 | static struct platform_driver mxc_w1_driver = { |
| 172 | .driver = { |
Martin Fuzzey | 28c55dc | 2013-01-29 16:46:10 +0100 | [diff] [blame] | 173 | .name = "mxc_w1", |
| 174 | .of_match_table = mxc_w1_dt_ids, |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 175 | }, |
| 176 | .probe = mxc_w1_probe, |
Greg Kroah-Hartman | 10532fe | 2012-12-21 12:55:26 -0800 | [diff] [blame] | 177 | .remove = mxc_w1_remove, |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 178 | }; |
Fabio Estevam | fd21bfc | 2012-11-19 10:19:48 -0200 | [diff] [blame] | 179 | module_platform_driver(mxc_w1_driver); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 180 | |
| 181 | MODULE_LICENSE("GPL"); |
| 182 | MODULE_AUTHOR("Freescale Semiconductors Inc"); |
| 183 | MODULE_DESCRIPTION("Driver for One-Wire on MXC"); |