| Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| Andrew Jeffery | 4d3d0e42 | 2016-08-30 17:24:24 +0930 | [diff] [blame] | 2 | config PINCTRL_ASPEED |
| 3 | bool |
| 4 | depends on (ARCH_ASPEED || COMPILE_TEST) && OF |
| 5 | depends on MFD_SYSCON |
| 6 | select PINMUX |
| 7 | select PINCONF |
| 8 | select GENERIC_PINCONF |
| 9 | select REGMAP_MMIO |
| Andrew Jeffery | 524594d | 2016-08-30 17:24:25 +0930 | [diff] [blame] | 10 | |
| 11 | config PINCTRL_ASPEED_G4 |
| 12 | bool "Aspeed G4 SoC pin control" |
| 13 | depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF |
| 14 | select PINCTRL_ASPEED |
| 15 | help |
| 16 | Say Y here to enable pin controller support for Aspeed's 4th |
| 17 | generation SoCs. GPIO is provided by a separate GPIO driver. |
| Andrew Jeffery | 56e57cb | 2016-08-30 17:24:26 +0930 | [diff] [blame] | 18 | |
| 19 | config PINCTRL_ASPEED_G5 |
| 20 | bool "Aspeed G5 SoC pin control" |
| 21 | depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF |
| 22 | select PINCTRL_ASPEED |
| 23 | help |
| 24 | Say Y here to enable pin controller support for Aspeed's 5th |
| 25 | generation SoCs. GPIO is provided by a separate GPIO driver. |
| Andrew Jeffery | 2eda1cd | 2019-07-11 13:49:42 +0930 | [diff] [blame] | 26 | |
| 27 | config PINCTRL_ASPEED_G6 |
| 28 | bool "Aspeed G6 SoC pin control" |
| 29 | depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF |
| 30 | select PINCTRL_ASPEED |
| 31 | help |
| 32 | Say Y here to enable pin controller support for Aspeed's 6th |
| 33 | generation SoCs. GPIO is provided by a separate GPIO driver. |