arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020 Microchip Technology Inc */

/dts-v1/;

#include "microchip-mpfs.dtsi"

/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ		1000000

/ {
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

	aliases {
		ethernet0 = &emac1;
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	cpus {
		timebase-frequency = <RTCCLK_FREQ>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		clocks = <&clkcfg 26>;
	};
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&serial3 {
	status = "okay";
};

&mmc {
	status = "okay";

	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&emac0 {
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@8 {
		reg = <8>;
		ti,fifo-depth = <0x01>;
	};
};

&emac1 {
	status = "okay";
	phy-mode = "sgmii";
	phy-handle = <&phy1>;
	phy1: ethernet-phy@9 {
		reg = <9>;
		ti,fifo-depth = <0x01>;
	};
};