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Ralf Baechle05490622016-04-15 10:25:33 +02001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Macros for 32/64-bit neutral inline assembler
7 */
8
9#ifndef __ASM_LLSC_H
10#define __ASM_LLSC_H
11
Paul Burtonef85d052019-10-01 21:53:06 +000012#include <asm/isa-rev.h>
13
Ralf Baechle05490622016-04-15 10:25:33 +020014#if _MIPS_SZLONG == 32
Ralf Baechle05490622016-04-15 10:25:33 +020015#define __LL "ll "
16#define __SC "sc "
17#define __INS "ins "
18#define __EXT "ext "
19#elif _MIPS_SZLONG == 64
Ralf Baechle05490622016-04-15 10:25:33 +020020#define __LL "lld "
21#define __SC "scd "
22#define __INS "dins "
23#define __EXT "dext "
24#endif
25
Paul Burton878f75c2019-10-01 21:53:05 +000026/*
27 * Using a branch-likely instruction to check the result of an sc instruction
28 * works around a bug present in R10000 CPUs prior to revision 3.0 that could
29 * cause ll-sc sequences to execute non-atomically.
30 */
Thomas Bogendoerfer256ec482020-08-24 18:32:49 +020031#ifdef CONFIG_WAR_R10000_LLSC
Paul Burton878f75c2019-10-01 21:53:05 +000032# define __SC_BEQZ "beqzl "
Paul Burtonef85d052019-10-01 21:53:06 +000033#elif MIPS_ISA_REV >= 6
34# define __SC_BEQZ "beqzc "
Paul Burton878f75c2019-10-01 21:53:05 +000035#else
36# define __SC_BEQZ "beqz "
37#endif
38
Ralf Baechle05490622016-04-15 10:25:33 +020039#endif /* __ASM_LLSC_H */