Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | # Copyright 2019 BayLibre, SAS |
| 3 | %YAML 1.2 |
| 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | |
| 8 | title: STMicroelectronics STM32 / MCU DWMAC glue layer controller |
| 9 | |
| 10 | maintainers: |
Patrice Chotard | f4eedeb | 2021-11-10 16:01:44 +0100 | [diff] [blame] | 11 | - Alexandre Torgue <alexandre.torgue@foss.st.com> |
| 12 | - Christophe Roullier <christophe.roullier@foss.st.com> |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 13 | |
| 14 | description: |
| 15 | This file documents platform glue layer for stmmac. |
| 16 | |
| 17 | # We need a select here so we don't match all nodes with 'snps,dwmac' |
| 18 | select: |
| 19 | properties: |
| 20 | compatible: |
| 21 | contains: |
| 22 | enum: |
| 23 | - st,stm32-dwmac |
| 24 | - st,stm32mp1-dwmac |
| 25 | required: |
| 26 | - compatible |
| 27 | |
| 28 | allOf: |
| 29 | - $ref: "snps,dwmac.yaml#" |
| 30 | |
| 31 | properties: |
| 32 | compatible: |
| 33 | oneOf: |
| 34 | - items: |
| 35 | - enum: |
| 36 | - st,stm32mp1-dwmac |
| 37 | - const: snps,dwmac-4.20a |
| 38 | - items: |
| 39 | - enum: |
| 40 | - st,stm32-dwmac |
| 41 | - const: snps,dwmac-4.10a |
| 42 | - items: |
| 43 | - enum: |
| 44 | - st,stm32-dwmac |
| 45 | - const: snps,dwmac-3.50a |
| 46 | |
| 47 | clocks: |
| 48 | minItems: 3 |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 49 | items: |
Rob Herring | f516fb7 | 2020-04-20 21:24:47 -0500 | [diff] [blame] | 50 | - description: GMAC main clock |
| 51 | - description: MAC TX clock |
| 52 | - description: MAC RX clock |
| 53 | - description: For MPU family, used for power mode |
| 54 | - description: For MPU family, used for PHY without quartz |
Alexandre Torgue | fea9982 | 2021-04-15 12:10:32 +0200 | [diff] [blame] | 55 | - description: PTP clock |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 56 | |
| 57 | clock-names: |
| 58 | minItems: 3 |
Alexandre Torgue | fea9982 | 2021-04-15 12:10:32 +0200 | [diff] [blame] | 59 | maxItems: 6 |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 60 | contains: |
| 61 | enum: |
| 62 | - stmmaceth |
| 63 | - mac-clk-tx |
| 64 | - mac-clk-rx |
| 65 | - ethstp |
| 66 | - eth-ck |
Alexandre Torgue | fea9982 | 2021-04-15 12:10:32 +0200 | [diff] [blame] | 67 | - ptp_ref |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 68 | |
| 69 | st,syscon: |
Rob Herring | 3d21a46 | 2020-04-15 19:55:49 -0500 | [diff] [blame] | 70 | $ref: "/schemas/types.yaml#/definitions/phandle-array" |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 71 | description: |
| 72 | Should be phandle/offset pair. The phandle to the syscon node which |
| 73 | encompases the glue register, and the offset of the control register |
| 74 | |
| 75 | st,eth-clk-sel: |
| 76 | description: |
| 77 | set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. |
| 78 | type: boolean |
| 79 | |
| 80 | st,eth-ref-clk-sel: |
| 81 | description: |
| 82 | set this property in RMII mode when you have PHY without crystal 50MHz and want to |
| 83 | select RCC clock instead of ETH_REF_CLK. |
| 84 | type: boolean |
| 85 | |
| 86 | required: |
| 87 | - compatible |
| 88 | - clocks |
| 89 | - clock-names |
| 90 | - st,syscon |
| 91 | |
Rob Herring | 6fdc6e2 | 2020-10-05 13:38:27 -0500 | [diff] [blame] | 92 | unevaluatedProperties: false |
| 93 | |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 94 | examples: |
Rob Herring | f516fb7 | 2020-04-20 21:24:47 -0500 | [diff] [blame] | 95 | - | |
Christophe Roullier | eb57a29 | 2020-04-03 16:04:15 +0200 | [diff] [blame] | 96 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 97 | #include <dt-bindings/clock/stm32mp1-clks.h> |
| 98 | #include <dt-bindings/reset/stm32mp1-resets.h> |
| 99 | #include <dt-bindings/mfd/stm32h7-rcc.h> |
| 100 | //Example 1 |
| 101 | ethernet0: ethernet@5800a000 { |
| 102 | compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; |
| 103 | reg = <0x5800a000 0x2000>; |
| 104 | reg-names = "stmmaceth"; |
| 105 | interrupts = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 106 | interrupt-names = "macirq"; |
| 107 | clock-names = "stmmaceth", |
| 108 | "mac-clk-tx", |
| 109 | "mac-clk-rx", |
| 110 | "ethstp", |
| 111 | "eth-ck"; |
| 112 | clocks = <&rcc ETHMAC>, |
| 113 | <&rcc ETHTX>, |
| 114 | <&rcc ETHRX>, |
| 115 | <&rcc ETHSTP>, |
| 116 | <&rcc ETHCK_K>; |
| 117 | st,syscon = <&syscfg 0x4>; |
| 118 | snps,pbl = <2>; |
| 119 | snps,axi-config = <&stmmac_axi_config_0>; |
| 120 | snps,tso; |
| 121 | phy-mode = "rgmii"; |
| 122 | }; |
| 123 | |
| 124 | //Example 2 (MCU example) |
| 125 | ethernet1: ethernet@40028000 { |
| 126 | compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; |
| 127 | reg = <0x40028000 0x8000>; |
| 128 | reg-names = "stmmaceth"; |
| 129 | interrupts = <0 61 0>, <0 62 0>; |
| 130 | interrupt-names = "macirq", "eth_wake_irq"; |
| 131 | clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; |
| 132 | clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; |
| 133 | st,syscon = <&syscfg 0x4>; |
| 134 | snps,pbl = <8>; |
| 135 | snps,mixed-burst; |
| 136 | phy-mode = "mii"; |
| 137 | }; |
| 138 | |
| 139 | //Example 3 |
| 140 | ethernet2: ethernet@40027000 { |
| 141 | compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; |
| 142 | reg = <0x40028000 0x8000>; |
| 143 | reg-names = "stmmaceth"; |
| 144 | interrupts = <61>; |
| 145 | interrupt-names = "macirq"; |
| 146 | clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; |
| 147 | clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>; |
| 148 | st,syscon = <&syscfg 0x4>; |
| 149 | snps,pbl = <8>; |
| 150 | phy-mode = "mii"; |
| 151 | }; |