| Joseph Chan | 37773cf | 2008-10-15 22:03:26 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
| 3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
| 4 | |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public |
| 7 | * License as published by the Free Software Foundation; |
| 8 | * either version 2, or (at your option) any later version. |
| 9 | |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even |
| 12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR |
| 13 | * A PARTICULAR PURPOSE.See the GNU General Public License |
| 14 | * for more details. |
| 15 | |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., |
| 19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | */ |
| 21 | |
| 22 | #ifndef __SHARE_H__ |
| 23 | #define __SHARE_H__ |
| 24 | |
| 25 | /* Define Return Value */ |
| 26 | #define FAIL -1 |
| 27 | #define OK 1 |
| 28 | |
| 29 | #ifndef NULL |
| 30 | #define NULL 0 |
| 31 | #endif |
| 32 | |
| 33 | /* Define Bit Field */ |
| 34 | #define BIT0 0x01 |
| 35 | #define BIT1 0x02 |
| 36 | #define BIT2 0x04 |
| 37 | #define BIT3 0x08 |
| 38 | #define BIT4 0x10 |
| 39 | #define BIT5 0x20 |
| 40 | #define BIT6 0x40 |
| 41 | #define BIT7 0x80 |
| 42 | |
| 43 | /* Video Memory Size */ |
| 44 | #define VIDEO_MEMORY_SIZE_16M 0x1000000 |
| 45 | |
| Joseph Chan | 37773cf | 2008-10-15 22:03:26 -0700 | [diff] [blame] | 46 | /* standard VGA IO port |
| 47 | */ |
| 48 | #define VIARMisc 0x3CC |
| 49 | #define VIAWMisc 0x3C2 |
| 50 | #define VIAStatus 0x3DA |
| 51 | #define VIACR 0x3D4 |
| 52 | #define VIASR 0x3C4 |
| 53 | #define VIAGR 0x3CE |
| 54 | #define VIAAR 0x3C0 |
| 55 | |
| 56 | #define StdCR 0x19 |
| 57 | #define StdSR 0x04 |
| 58 | #define StdGR 0x09 |
| 59 | #define StdAR 0x14 |
| 60 | |
| 61 | #define PatchCR 11 |
| 62 | |
| 63 | /* Display path */ |
| 64 | #define IGA1 1 |
| 65 | #define IGA2 2 |
| Joseph Chan | 37773cf | 2008-10-15 22:03:26 -0700 | [diff] [blame] | 66 | |
| 67 | /* Define Color Depth */ |
| 68 | #define MODE_8BPP 1 |
| 69 | #define MODE_16BPP 2 |
| 70 | #define MODE_32BPP 4 |
| 71 | |
| 72 | #define GR20 0x20 |
| 73 | #define GR21 0x21 |
| 74 | #define GR22 0x22 |
| 75 | |
| 76 | /* Sequencer Registers */ |
| 77 | #define SR01 0x01 |
| 78 | #define SR10 0x10 |
| 79 | #define SR12 0x12 |
| 80 | #define SR15 0x15 |
| 81 | #define SR16 0x16 |
| 82 | #define SR17 0x17 |
| 83 | #define SR18 0x18 |
| 84 | #define SR1B 0x1B |
| 85 | #define SR1A 0x1A |
| 86 | #define SR1C 0x1C |
| 87 | #define SR1D 0x1D |
| 88 | #define SR1E 0x1E |
| 89 | #define SR1F 0x1F |
| 90 | #define SR20 0x20 |
| 91 | #define SR21 0x21 |
| 92 | #define SR22 0x22 |
| 93 | #define SR2A 0x2A |
| 94 | #define SR2D 0x2D |
| 95 | #define SR2E 0x2E |
| 96 | |
| 97 | #define SR30 0x30 |
| 98 | #define SR39 0x39 |
| 99 | #define SR3D 0x3D |
| 100 | #define SR3E 0x3E |
| 101 | #define SR3F 0x3F |
| 102 | #define SR40 0x40 |
| 103 | #define SR43 0x43 |
| 104 | #define SR44 0x44 |
| 105 | #define SR45 0x45 |
| 106 | #define SR46 0x46 |
| 107 | #define SR47 0x47 |
| 108 | #define SR48 0x48 |
| 109 | #define SR49 0x49 |
| 110 | #define SR4A 0x4A |
| 111 | #define SR4B 0x4B |
| 112 | #define SR4C 0x4C |
| 113 | #define SR52 0x52 |
| Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 114 | #define SR57 0x57 |
| 115 | #define SR58 0x58 |
| 116 | #define SR59 0x59 |
| 117 | #define SR5D 0x5D |
| Joseph Chan | 37773cf | 2008-10-15 22:03:26 -0700 | [diff] [blame] | 118 | #define SR5E 0x5E |
| 119 | #define SR65 0x65 |
| 120 | |
| 121 | /* CRT Controller Registers */ |
| 122 | #define CR00 0x00 |
| 123 | #define CR01 0x01 |
| 124 | #define CR02 0x02 |
| 125 | #define CR03 0x03 |
| 126 | #define CR04 0x04 |
| 127 | #define CR05 0x05 |
| 128 | #define CR06 0x06 |
| 129 | #define CR07 0x07 |
| 130 | #define CR08 0x08 |
| 131 | #define CR09 0x09 |
| 132 | #define CR0A 0x0A |
| 133 | #define CR0B 0x0B |
| 134 | #define CR0C 0x0C |
| 135 | #define CR0D 0x0D |
| 136 | #define CR0E 0x0E |
| 137 | #define CR0F 0x0F |
| 138 | #define CR10 0x10 |
| 139 | #define CR11 0x11 |
| 140 | #define CR12 0x12 |
| 141 | #define CR13 0x13 |
| 142 | #define CR14 0x14 |
| 143 | #define CR15 0x15 |
| 144 | #define CR16 0x16 |
| 145 | #define CR17 0x17 |
| 146 | #define CR18 0x18 |
| 147 | |
| 148 | /* Extend CRT Controller Registers */ |
| 149 | #define CR30 0x30 |
| 150 | #define CR31 0x31 |
| 151 | #define CR32 0x32 |
| 152 | #define CR33 0x33 |
| 153 | #define CR34 0x34 |
| 154 | #define CR35 0x35 |
| 155 | #define CR36 0x36 |
| 156 | #define CR37 0x37 |
| 157 | #define CR38 0x38 |
| 158 | #define CR39 0x39 |
| 159 | #define CR3A 0x3A |
| 160 | #define CR3B 0x3B |
| 161 | #define CR3C 0x3C |
| 162 | #define CR3D 0x3D |
| 163 | #define CR3E 0x3E |
| 164 | #define CR3F 0x3F |
| 165 | #define CR40 0x40 |
| 166 | #define CR41 0x41 |
| 167 | #define CR42 0x42 |
| 168 | #define CR43 0x43 |
| 169 | #define CR44 0x44 |
| 170 | #define CR45 0x45 |
| 171 | #define CR46 0x46 |
| 172 | #define CR47 0x47 |
| 173 | #define CR48 0x48 |
| 174 | #define CR49 0x49 |
| 175 | #define CR4A 0x4A |
| 176 | #define CR4B 0x4B |
| 177 | #define CR4C 0x4C |
| 178 | #define CR4D 0x4D |
| 179 | #define CR4E 0x4E |
| 180 | #define CR4F 0x4F |
| 181 | #define CR50 0x50 |
| 182 | #define CR51 0x51 |
| 183 | #define CR52 0x52 |
| 184 | #define CR53 0x53 |
| 185 | #define CR54 0x54 |
| 186 | #define CR55 0x55 |
| 187 | #define CR56 0x56 |
| 188 | #define CR57 0x57 |
| 189 | #define CR58 0x58 |
| 190 | #define CR59 0x59 |
| 191 | #define CR5A 0x5A |
| 192 | #define CR5B 0x5B |
| 193 | #define CR5C 0x5C |
| 194 | #define CR5D 0x5D |
| 195 | #define CR5E 0x5E |
| 196 | #define CR5F 0x5F |
| 197 | #define CR60 0x60 |
| 198 | #define CR61 0x61 |
| 199 | #define CR62 0x62 |
| 200 | #define CR63 0x63 |
| 201 | #define CR64 0x64 |
| 202 | #define CR65 0x65 |
| 203 | #define CR66 0x66 |
| 204 | #define CR67 0x67 |
| 205 | #define CR68 0x68 |
| 206 | #define CR69 0x69 |
| 207 | #define CR6A 0x6A |
| 208 | #define CR6B 0x6B |
| 209 | #define CR6C 0x6C |
| 210 | #define CR6D 0x6D |
| 211 | #define CR6E 0x6E |
| 212 | #define CR6F 0x6F |
| 213 | #define CR70 0x70 |
| 214 | #define CR71 0x71 |
| 215 | #define CR72 0x72 |
| 216 | #define CR73 0x73 |
| 217 | #define CR74 0x74 |
| 218 | #define CR75 0x75 |
| 219 | #define CR76 0x76 |
| 220 | #define CR77 0x77 |
| 221 | #define CR78 0x78 |
| 222 | #define CR79 0x79 |
| 223 | #define CR7A 0x7A |
| 224 | #define CR7B 0x7B |
| 225 | #define CR7C 0x7C |
| 226 | #define CR7D 0x7D |
| 227 | #define CR7E 0x7E |
| 228 | #define CR7F 0x7F |
| 229 | #define CR80 0x80 |
| 230 | #define CR81 0x81 |
| 231 | #define CR82 0x82 |
| 232 | #define CR83 0x83 |
| 233 | #define CR84 0x84 |
| 234 | #define CR85 0x85 |
| 235 | #define CR86 0x86 |
| 236 | #define CR87 0x87 |
| 237 | #define CR88 0x88 |
| 238 | #define CR89 0x89 |
| 239 | #define CR8A 0x8A |
| 240 | #define CR8B 0x8B |
| 241 | #define CR8C 0x8C |
| 242 | #define CR8D 0x8D |
| 243 | #define CR8E 0x8E |
| 244 | #define CR8F 0x8F |
| 245 | #define CR90 0x90 |
| 246 | #define CR91 0x91 |
| 247 | #define CR92 0x92 |
| 248 | #define CR93 0x93 |
| 249 | #define CR94 0x94 |
| 250 | #define CR95 0x95 |
| 251 | #define CR96 0x96 |
| 252 | #define CR97 0x97 |
| 253 | #define CR98 0x98 |
| 254 | #define CR99 0x99 |
| 255 | #define CR9A 0x9A |
| 256 | #define CR9B 0x9B |
| 257 | #define CR9C 0x9C |
| 258 | #define CR9D 0x9D |
| 259 | #define CR9E 0x9E |
| 260 | #define CR9F 0x9F |
| 261 | #define CRA0 0xA0 |
| 262 | #define CRA1 0xA1 |
| 263 | #define CRA2 0xA2 |
| 264 | #define CRA3 0xA3 |
| 265 | #define CRD2 0xD2 |
| 266 | #define CRD3 0xD3 |
| 267 | #define CRD4 0xD4 |
| 268 | |
| 269 | /* LUT Table*/ |
| 270 | #define LUT_DATA 0x3C9 /* DACDATA */ |
| 271 | #define LUT_INDEX_READ 0x3C7 /* DACRX */ |
| 272 | #define LUT_INDEX_WRITE 0x3C8 /* DACWX */ |
| 273 | #define DACMASK 0x3C6 |
| 274 | |
| 275 | /* Definition Device */ |
| 276 | #define DEVICE_CRT 0x01 |
| 277 | #define DEVICE_DVI 0x03 |
| 278 | #define DEVICE_LCD 0x04 |
| 279 | |
| 280 | /* Device output interface */ |
| 281 | #define INTERFACE_NONE 0x00 |
| 282 | #define INTERFACE_ANALOG_RGB 0x01 |
| 283 | #define INTERFACE_DVP0 0x02 |
| 284 | #define INTERFACE_DVP1 0x03 |
| 285 | #define INTERFACE_DFP_HIGH 0x04 |
| 286 | #define INTERFACE_DFP_LOW 0x05 |
| 287 | #define INTERFACE_DFP 0x06 |
| 288 | #define INTERFACE_LVDS0 0x07 |
| 289 | #define INTERFACE_LVDS1 0x08 |
| 290 | #define INTERFACE_LVDS0LVDS1 0x09 |
| 291 | #define INTERFACE_TMDS 0x0A |
| 292 | |
| 293 | #define HW_LAYOUT_LCD_ONLY 0x01 |
| 294 | #define HW_LAYOUT_DVI_ONLY 0x02 |
| 295 | #define HW_LAYOUT_LCD_DVI 0x03 |
| 296 | #define HW_LAYOUT_LCD1_LCD2 0x04 |
| 297 | #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10 |
| 298 | |
| 299 | /* Definition Refresh Rate */ |
| 300 | #define REFRESH_50 50 |
| 301 | #define REFRESH_60 60 |
| 302 | #define REFRESH_75 75 |
| 303 | #define REFRESH_85 85 |
| 304 | #define REFRESH_100 100 |
| 305 | #define REFRESH_120 120 |
| 306 | |
| 307 | /* Definition Sync Polarity*/ |
| 308 | #define NEGATIVE 1 |
| 309 | #define POSITIVE 0 |
| 310 | |
| 311 | /*480x640@60 Sync Polarity (GTF) |
| 312 | */ |
| 313 | #define M480X640_R60_HSP NEGATIVE |
| 314 | #define M480X640_R60_VSP POSITIVE |
| 315 | |
| 316 | /*640x480@60 Sync Polarity (VESA Mode) |
| 317 | */ |
| 318 | #define M640X480_R60_HSP NEGATIVE |
| 319 | #define M640X480_R60_VSP NEGATIVE |
| 320 | |
| 321 | /*640x480@75 Sync Polarity (VESA Mode) |
| 322 | */ |
| 323 | #define M640X480_R75_HSP NEGATIVE |
| 324 | #define M640X480_R75_VSP NEGATIVE |
| 325 | |
| 326 | /*640x480@85 Sync Polarity (VESA Mode) |
| 327 | */ |
| 328 | #define M640X480_R85_HSP NEGATIVE |
| 329 | #define M640X480_R85_VSP NEGATIVE |
| 330 | |
| 331 | /*640x480@100 Sync Polarity (GTF Mode) |
| 332 | */ |
| 333 | #define M640X480_R100_HSP NEGATIVE |
| 334 | #define M640X480_R100_VSP POSITIVE |
| 335 | |
| 336 | /*640x480@120 Sync Polarity (GTF Mode) |
| 337 | */ |
| 338 | #define M640X480_R120_HSP NEGATIVE |
| 339 | #define M640X480_R120_VSP POSITIVE |
| 340 | |
| 341 | /*720x480@60 Sync Polarity (GTF Mode) |
| 342 | */ |
| 343 | #define M720X480_R60_HSP NEGATIVE |
| 344 | #define M720X480_R60_VSP POSITIVE |
| 345 | |
| 346 | /*720x576@60 Sync Polarity (GTF Mode) |
| 347 | */ |
| 348 | #define M720X576_R60_HSP NEGATIVE |
| 349 | #define M720X576_R60_VSP POSITIVE |
| 350 | |
| 351 | /*800x600@60 Sync Polarity (VESA Mode) |
| 352 | */ |
| 353 | #define M800X600_R60_HSP POSITIVE |
| 354 | #define M800X600_R60_VSP POSITIVE |
| 355 | |
| 356 | /*800x600@75 Sync Polarity (VESA Mode) |
| 357 | */ |
| 358 | #define M800X600_R75_HSP POSITIVE |
| 359 | #define M800X600_R75_VSP POSITIVE |
| 360 | |
| 361 | /*800x600@85 Sync Polarity (VESA Mode) |
| 362 | */ |
| 363 | #define M800X600_R85_HSP POSITIVE |
| 364 | #define M800X600_R85_VSP POSITIVE |
| 365 | |
| 366 | /*800x600@100 Sync Polarity (GTF Mode) |
| 367 | */ |
| 368 | #define M800X600_R100_HSP NEGATIVE |
| 369 | #define M800X600_R100_VSP POSITIVE |
| 370 | |
| 371 | /*800x600@120 Sync Polarity (GTF Mode) |
| 372 | */ |
| 373 | #define M800X600_R120_HSP NEGATIVE |
| 374 | #define M800X600_R120_VSP POSITIVE |
| 375 | |
| 376 | /*800x480@60 Sync Polarity (CVT Mode) |
| 377 | */ |
| 378 | #define M800X480_R60_HSP NEGATIVE |
| 379 | #define M800X480_R60_VSP POSITIVE |
| 380 | |
| 381 | /*848x480@60 Sync Polarity (CVT Mode) |
| 382 | */ |
| 383 | #define M848X480_R60_HSP NEGATIVE |
| 384 | #define M848X480_R60_VSP POSITIVE |
| 385 | |
| 386 | /*852x480@60 Sync Polarity (GTF Mode) |
| 387 | */ |
| 388 | #define M852X480_R60_HSP NEGATIVE |
| 389 | #define M852X480_R60_VSP POSITIVE |
| 390 | |
| 391 | /*1024x512@60 Sync Polarity (GTF Mode) |
| 392 | */ |
| 393 | #define M1024X512_R60_HSP NEGATIVE |
| 394 | #define M1024X512_R60_VSP POSITIVE |
| 395 | |
| 396 | /*1024x600@60 Sync Polarity (GTF Mode) |
| 397 | */ |
| 398 | #define M1024X600_R60_HSP NEGATIVE |
| 399 | #define M1024X600_R60_VSP POSITIVE |
| 400 | |
| 401 | /*1024x768@60 Sync Polarity (VESA Mode) |
| 402 | */ |
| 403 | #define M1024X768_R60_HSP NEGATIVE |
| 404 | #define M1024X768_R60_VSP NEGATIVE |
| 405 | |
| 406 | /*1024x768@75 Sync Polarity (VESA Mode) |
| 407 | */ |
| 408 | #define M1024X768_R75_HSP POSITIVE |
| 409 | #define M1024X768_R75_VSP POSITIVE |
| 410 | |
| 411 | /*1024x768@85 Sync Polarity (VESA Mode) |
| 412 | */ |
| 413 | #define M1024X768_R85_HSP POSITIVE |
| 414 | #define M1024X768_R85_VSP POSITIVE |
| 415 | |
| 416 | /*1024x768@100 Sync Polarity (GTF Mode) |
| 417 | */ |
| 418 | #define M1024X768_R100_HSP NEGATIVE |
| 419 | #define M1024X768_R100_VSP POSITIVE |
| 420 | |
| 421 | /*1152x864@75 Sync Polarity (VESA Mode) |
| 422 | */ |
| 423 | #define M1152X864_R75_HSP POSITIVE |
| 424 | #define M1152X864_R75_VSP POSITIVE |
| 425 | |
| 426 | /*1280x720@60 Sync Polarity (GTF Mode) |
| 427 | */ |
| 428 | #define M1280X720_R60_HSP NEGATIVE |
| 429 | #define M1280X720_R60_VSP POSITIVE |
| 430 | |
| 431 | /* 1280x768@50 Sync Polarity (GTF Mode) */ |
| 432 | #define M1280X768_R50_HSP NEGATIVE |
| 433 | #define M1280X768_R50_VSP POSITIVE |
| 434 | |
| 435 | /*1280x768@60 Sync Polarity (GTF Mode) |
| 436 | */ |
| 437 | #define M1280X768_R60_HSP NEGATIVE |
| 438 | #define M1280X768_R60_VSP POSITIVE |
| 439 | |
| 440 | /*1280x800@60 Sync Polarity (CVT Mode) |
| 441 | */ |
| 442 | #define M1280X800_R60_HSP NEGATIVE |
| 443 | #define M1280X800_R60_VSP POSITIVE |
| 444 | |
| 445 | /*1280x960@60 Sync Polarity (VESA Mode) |
| 446 | */ |
| 447 | #define M1280X960_R60_HSP POSITIVE |
| 448 | #define M1280X960_R60_VSP POSITIVE |
| 449 | |
| 450 | /*1280x1024@60 Sync Polarity (VESA Mode) |
| 451 | */ |
| 452 | #define M1280X1024_R60_HSP POSITIVE |
| 453 | #define M1280X1024_R60_VSP POSITIVE |
| 454 | |
| 455 | /* 1360x768@60 Sync Polarity (CVT Mode) */ |
| 456 | #define M1360X768_R60_HSP POSITIVE |
| 457 | #define M1360X768_R60_VSP POSITIVE |
| 458 | |
| 459 | /* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 460 | #define M1360X768_RB_R60_HSP POSITIVE |
| 461 | #define M1360X768_RB_R60_VSP NEGATIVE |
| 462 | |
| 463 | /* 1368x768@50 Sync Polarity (GTF Mode) */ |
| 464 | #define M1368X768_R50_HSP NEGATIVE |
| 465 | #define M1368X768_R50_VSP POSITIVE |
| 466 | |
| 467 | /* 1368x768@60 Sync Polarity (VESA Mode) */ |
| 468 | #define M1368X768_R60_HSP NEGATIVE |
| 469 | #define M1368X768_R60_VSP POSITIVE |
| 470 | |
| 471 | /*1280x1024@75 Sync Polarity (VESA Mode) |
| 472 | */ |
| 473 | #define M1280X1024_R75_HSP POSITIVE |
| 474 | #define M1280X1024_R75_VSP POSITIVE |
| 475 | |
| 476 | /*1280x1024@85 Sync Polarity (VESA Mode) |
| 477 | */ |
| 478 | #define M1280X1024_R85_HSP POSITIVE |
| 479 | #define M1280X1024_R85_VSP POSITIVE |
| 480 | |
| 481 | /*1440x1050@60 Sync Polarity (GTF Mode) |
| 482 | */ |
| 483 | #define M1440X1050_R60_HSP NEGATIVE |
| 484 | #define M1440X1050_R60_VSP POSITIVE |
| 485 | |
| 486 | /*1600x1200@60 Sync Polarity (VESA Mode) |
| 487 | */ |
| 488 | #define M1600X1200_R60_HSP POSITIVE |
| 489 | #define M1600X1200_R60_VSP POSITIVE |
| 490 | |
| 491 | /*1600x1200@75 Sync Polarity (VESA Mode) |
| 492 | */ |
| 493 | #define M1600X1200_R75_HSP POSITIVE |
| 494 | #define M1600X1200_R75_VSP POSITIVE |
| 495 | |
| 496 | /* 1680x1050@60 Sync Polarity (CVT Mode) */ |
| 497 | #define M1680x1050_R60_HSP NEGATIVE |
| 498 | #define M1680x1050_R60_VSP NEGATIVE |
| 499 | |
| 500 | /* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 501 | #define M1680x1050_RB_R60_HSP POSITIVE |
| 502 | #define M1680x1050_RB_R60_VSP NEGATIVE |
| 503 | |
| 504 | /* 1680x1050@75 Sync Polarity (CVT Mode) */ |
| 505 | #define M1680x1050_R75_HSP NEGATIVE |
| 506 | #define M1680x1050_R75_VSP POSITIVE |
| 507 | |
| 508 | /*1920x1080@60 Sync Polarity (CVT Mode) |
| 509 | */ |
| 510 | #define M1920X1080_R60_HSP NEGATIVE |
| 511 | #define M1920X1080_R60_VSP POSITIVE |
| 512 | |
| 513 | /* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 514 | #define M1920X1080_RB_R60_HSP POSITIVE |
| 515 | #define M1920X1080_RB_R60_VSP NEGATIVE |
| 516 | |
| 517 | /*1920x1440@60 Sync Polarity (VESA Mode) |
| 518 | */ |
| 519 | #define M1920X1440_R60_HSP NEGATIVE |
| 520 | #define M1920X1440_R60_VSP POSITIVE |
| 521 | |
| 522 | /*1920x1440@75 Sync Polarity (VESA Mode) |
| 523 | */ |
| 524 | #define M1920X1440_R75_HSP NEGATIVE |
| 525 | #define M1920X1440_R75_VSP POSITIVE |
| 526 | |
| 527 | #if 0 |
| 528 | /* 1400x1050@60 Sync Polarity (VESA Mode) */ |
| 529 | #define M1400X1050_R60_HSP NEGATIVE |
| 530 | #define M1400X1050_R60_VSP NEGATIVE |
| 531 | #endif |
| 532 | |
| 533 | /* 1400x1050@60 Sync Polarity (CVT Mode) */ |
| 534 | #define M1400X1050_R60_HSP NEGATIVE |
| 535 | #define M1400X1050_R60_VSP POSITIVE |
| 536 | |
| 537 | /* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 538 | #define M1400X1050_RB_R60_HSP POSITIVE |
| 539 | #define M1400X1050_RB_R60_VSP NEGATIVE |
| 540 | |
| 541 | /* 1400x1050@75 Sync Polarity (CVT Mode) */ |
| 542 | #define M1400X1050_R75_HSP NEGATIVE |
| 543 | #define M1400X1050_R75_VSP POSITIVE |
| 544 | |
| 545 | /* 960x600@60 Sync Polarity (CVT Mode) */ |
| 546 | #define M960X600_R60_HSP NEGATIVE |
| 547 | #define M960X600_R60_VSP POSITIVE |
| 548 | |
| 549 | /* 1000x600@60 Sync Polarity (GTF Mode) */ |
| 550 | #define M1000X600_R60_HSP NEGATIVE |
| 551 | #define M1000X600_R60_VSP POSITIVE |
| 552 | |
| 553 | /* 1024x576@60 Sync Polarity (GTF Mode) */ |
| 554 | #define M1024X576_R60_HSP NEGATIVE |
| 555 | #define M1024X576_R60_VSP POSITIVE |
| 556 | |
| 557 | /*1024x600@60 Sync Polarity (GTF Mode)*/ |
| 558 | #define M1024X600_R60_HSP NEGATIVE |
| 559 | #define M1024X600_R60_VSP POSITIVE |
| 560 | |
| 561 | /* 1088x612@60 Sync Polarity (CVT Mode) */ |
| 562 | #define M1088X612_R60_HSP NEGATIVE |
| 563 | #define M1088X612_R60_VSP POSITIVE |
| 564 | |
| 565 | /* 1152x720@60 Sync Polarity (CVT Mode) */ |
| 566 | #define M1152X720_R60_HSP NEGATIVE |
| 567 | #define M1152X720_R60_VSP POSITIVE |
| 568 | |
| 569 | /* 1200x720@60 Sync Polarity (GTF Mode) */ |
| 570 | #define M1200X720_R60_HSP NEGATIVE |
| 571 | #define M1200X720_R60_VSP POSITIVE |
| 572 | |
| 573 | /* 1280x600@60 Sync Polarity (GTF Mode) */ |
| 574 | #define M1280x600_R60_HSP NEGATIVE |
| 575 | #define M1280x600_R60_VSP POSITIVE |
| 576 | |
| 577 | /* 1280x720@50 Sync Polarity (GTF Mode) */ |
| 578 | #define M1280X720_R50_HSP NEGATIVE |
| 579 | #define M1280X720_R50_VSP POSITIVE |
| 580 | |
| 581 | /* 1280x720@60 Sync Polarity (CEA Mode) */ |
| 582 | #define M1280X720_CEA_R60_HSP POSITIVE |
| 583 | #define M1280X720_CEA_R60_VSP POSITIVE |
| 584 | |
| 585 | /* 1440x900@60 Sync Polarity (CVT Mode) */ |
| 586 | #define M1440X900_R60_HSP NEGATIVE |
| 587 | #define M1440X900_R60_VSP POSITIVE |
| 588 | |
| 589 | /* 1440x900@75 Sync Polarity (CVT Mode) */ |
| 590 | #define M1440X900_R75_HSP NEGATIVE |
| 591 | #define M1440X900_R75_VSP POSITIVE |
| 592 | |
| 593 | /* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 594 | #define M1440X900_RB_R60_HSP POSITIVE |
| 595 | #define M1440X900_RB_R60_VSP NEGATIVE |
| 596 | |
| 597 | /* 1600x900@60 Sync Polarity (CVT Mode) */ |
| 598 | #define M1600X900_R60_HSP NEGATIVE |
| 599 | #define M1600X900_R60_VSP POSITIVE |
| 600 | |
| 601 | /* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 602 | #define M1600X900_RB_R60_HSP POSITIVE |
| 603 | #define M1600X900_RB_R60_VSP NEGATIVE |
| 604 | |
| 605 | /* 1600x1024@60 Sync Polarity (GTF Mode) */ |
| 606 | #define M1600X1024_R60_HSP NEGATIVE |
| 607 | #define M1600X1024_R60_VSP POSITIVE |
| 608 | |
| 609 | /* 1792x1344@60 Sync Polarity (DMT Mode) */ |
| 610 | #define M1792x1344_R60_HSP NEGATIVE |
| 611 | #define M1792x1344_R60_VSP POSITIVE |
| 612 | |
| 613 | /* 1856x1392@60 Sync Polarity (DMT Mode) */ |
| 614 | #define M1856x1392_R60_HSP NEGATIVE |
| 615 | #define M1856x1392_R60_VSP POSITIVE |
| 616 | |
| 617 | /* 1920x1200@60 Sync Polarity (CVT Mode) */ |
| 618 | #define M1920X1200_R60_HSP NEGATIVE |
| 619 | #define M1920X1200_R60_VSP POSITIVE |
| 620 | |
| 621 | /* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */ |
| 622 | #define M1920X1200_RB_R60_HSP POSITIVE |
| 623 | #define M1920X1200_RB_R60_VSP NEGATIVE |
| 624 | |
| 625 | /* 1920x1080@60 Sync Polarity (CEA Mode) */ |
| 626 | #define M1920X1080_CEA_R60_HSP POSITIVE |
| 627 | #define M1920X1080_CEA_R60_VSP POSITIVE |
| 628 | |
| 629 | /* 2048x1536@60 Sync Polarity (CVT Mode) */ |
| 630 | #define M2048x1536_R60_HSP NEGATIVE |
| 631 | #define M2048x1536_R60_VSP POSITIVE |
| 632 | |
| 633 | /* define PLL index: */ |
| 634 | #define CLK_25_175M 25175000 |
| 635 | #define CLK_26_880M 26880000 |
| 636 | #define CLK_29_581M 29581000 |
| 637 | #define CLK_31_490M 31490000 |
| 638 | #define CLK_31_500M 31500000 |
| 639 | #define CLK_31_728M 31728000 |
| 640 | #define CLK_32_668M 32688000 |
| 641 | #define CLK_36_000M 36000000 |
| 642 | #define CLK_40_000M 40000000 |
| 643 | #define CLK_41_291M 41291000 |
| 644 | #define CLK_43_163M 43163000 |
| 645 | #define CLK_45_250M 45250000 /* 45.46MHz */ |
| 646 | #define CLK_46_000M 46000000 |
| 647 | #define CLK_46_996M 46996000 |
| 648 | #define CLK_48_000M 48000000 |
| 649 | #define CLK_48_875M 48875000 |
| 650 | #define CLK_49_500M 49500000 |
| 651 | #define CLK_52_406M 52406000 |
| 652 | #define CLK_52_977M 52977000 |
| 653 | #define CLK_56_250M 56250000 |
| 654 | #define CLK_60_466M 60466000 |
| 655 | #define CLK_61_500M 61500000 |
| 656 | #define CLK_65_000M 65000000 |
| 657 | #define CLK_65_178M 65178000 |
| 658 | #define CLK_66_750M 66750000 /* 67.116MHz */ |
| 659 | #define CLK_68_179M 68179000 |
| 660 | #define CLK_69_924M 69924000 |
| 661 | #define CLK_70_159M 70159000 |
| 662 | #define CLK_72_000M 72000000 |
| 663 | #define CLK_74_270M 74270000 |
| 664 | #define CLK_78_750M 78750000 |
| 665 | #define CLK_80_136M 80136000 |
| 666 | #define CLK_83_375M 83375000 |
| 667 | #define CLK_83_950M 83950000 |
| 668 | #define CLK_84_750M 84750000 /* 84.537Mhz */ |
| 669 | #define CLK_85_860M 85860000 |
| 670 | #define CLK_88_750M 88750000 |
| 671 | #define CLK_94_500M 94500000 |
| 672 | #define CLK_97_750M 97750000 |
| 673 | #define CLK_101_000M 101000000 |
| 674 | #define CLK_106_500M 106500000 |
| 675 | #define CLK_108_000M 108000000 |
| 676 | #define CLK_113_309M 113309000 |
| 677 | #define CLK_118_840M 118840000 |
| 678 | #define CLK_119_000M 119000000 |
| 679 | #define CLK_121_750M 121750000 /* 121.704MHz */ |
| 680 | #define CLK_125_104M 125104000 |
| 681 | #define CLK_133_308M 133308000 |
| 682 | #define CLK_135_000M 135000000 |
| 683 | #define CLK_136_700M 136700000 |
| 684 | #define CLK_138_400M 138400000 |
| 685 | #define CLK_146_760M 146760000 |
| 686 | #define CLK_148_500M 148500000 |
| 687 | |
| 688 | #define CLK_153_920M 153920000 |
| 689 | #define CLK_156_000M 156000000 |
| 690 | #define CLK_157_500M 157500000 |
| 691 | #define CLK_162_000M 162000000 |
| 692 | #define CLK_187_000M 187000000 |
| 693 | #define CLK_193_295M 193295000 |
| 694 | #define CLK_202_500M 202500000 |
| 695 | #define CLK_204_000M 204000000 |
| 696 | #define CLK_218_500M 218500000 |
| 697 | #define CLK_234_000M 234000000 |
| 698 | #define CLK_267_250M 267250000 |
| 699 | #define CLK_297_500M 297500000 |
| 700 | #define CLK_74_481M 74481000 |
| 701 | #define CLK_172_798M 172798000 |
| 702 | #define CLK_122_614M 122614000 |
| 703 | |
| 704 | /* CLE266 PLL value |
| 705 | */ |
| 706 | #define CLE266_PLL_25_175M 0x0000C763 |
| 707 | #define CLE266_PLL_26_880M 0x0000440F |
| 708 | #define CLE266_PLL_29_581M 0x00008421 |
| 709 | #define CLE266_PLL_31_490M 0x00004721 |
| 710 | #define CLE266_PLL_31_500M 0x0000C3B5 |
| 711 | #define CLE266_PLL_31_728M 0x0000471F |
| 712 | #define CLE266_PLL_32_668M 0x0000C449 |
| 713 | #define CLE266_PLL_36_000M 0x0000C5E5 |
| 714 | #define CLE266_PLL_40_000M 0x0000C459 |
| 715 | #define CLE266_PLL_41_291M 0x00004417 |
| 716 | #define CLE266_PLL_43_163M 0x0000C579 |
| 717 | #define CLE266_PLL_45_250M 0x0000C57F /* 45.46MHz */ |
| 718 | #define CLE266_PLL_46_000M 0x0000875A |
| 719 | #define CLE266_PLL_46_996M 0x0000C4E9 |
| 720 | #define CLE266_PLL_48_000M 0x00001443 |
| 721 | #define CLE266_PLL_48_875M 0x00001D63 |
| 722 | #define CLE266_PLL_49_500M 0x00008653 |
| 723 | #define CLE266_PLL_52_406M 0x0000C475 |
| 724 | #define CLE266_PLL_52_977M 0x00004525 |
| 725 | #define CLE266_PLL_56_250M 0x000047B7 |
| 726 | #define CLE266_PLL_60_466M 0x0000494C |
| 727 | #define CLE266_PLL_61_500M 0x00001456 |
| 728 | #define CLE266_PLL_65_000M 0x000086ED |
| 729 | #define CLE266_PLL_65_178M 0x0000855B |
| 730 | #define CLE266_PLL_66_750M 0x0000844B /* 67.116MHz */ |
| 731 | #define CLE266_PLL_68_179M 0x00000413 |
| 732 | #define CLE266_PLL_69_924M 0x00001153 |
| 733 | #define CLE266_PLL_70_159M 0x00001462 |
| 734 | #define CLE266_PLL_72_000M 0x00001879 |
| 735 | #define CLE266_PLL_74_270M 0x00004853 |
| 736 | #define CLE266_PLL_78_750M 0x00004321 |
| 737 | #define CLE266_PLL_80_136M 0x0000051C |
| 738 | #define CLE266_PLL_83_375M 0x0000C25D |
| 739 | #define CLE266_PLL_83_950M 0x00000729 |
| 740 | #define CLE266_PLL_84_750M 0x00008576 /* 84.537MHz */ |
| 741 | #define CLE266_PLL_85_860M 0x00004754 |
| 742 | #define CLE266_PLL_88_750M 0x0000051F |
| 743 | #define CLE266_PLL_94_500M 0x00000521 |
| 744 | #define CLE266_PLL_97_750M 0x00004652 |
| 745 | #define CLE266_PLL_101_000M 0x0000497F |
| 746 | #define CLE266_PLL_106_500M 0x00008477 /* 106.491463 MHz */ |
| 747 | #define CLE266_PLL_108_000M 0x00008479 |
| 748 | #define CLE266_PLL_113_309M 0x00000C5F |
| 749 | #define CLE266_PLL_118_840M 0x00004553 |
| 750 | #define CLE266_PLL_119_000M 0x00000D6C |
| 751 | #define CLE266_PLL_121_750M 0x00004555 /* 121.704MHz */ |
| 752 | #define CLE266_PLL_125_104M 0x000006B5 |
| 753 | #define CLE266_PLL_133_308M 0x0000465F |
| 754 | #define CLE266_PLL_135_000M 0x0000455E |
| 755 | #define CLE266_PLL_136_700M 0x00000C73 |
| 756 | #define CLE266_PLL_138_400M 0x00000957 |
| 757 | #define CLE266_PLL_146_760M 0x00004567 |
| 758 | #define CLE266_PLL_148_500M 0x00000853 |
| 759 | #define CLE266_PLL_153_920M 0x00000856 |
| 760 | #define CLE266_PLL_156_000M 0x0000456D |
| 761 | #define CLE266_PLL_157_500M 0x000005B7 |
| 762 | #define CLE266_PLL_162_000M 0x00004571 |
| 763 | #define CLE266_PLL_187_000M 0x00000976 |
| 764 | #define CLE266_PLL_193_295M 0x0000086C |
| 765 | #define CLE266_PLL_202_500M 0x00000763 |
| 766 | #define CLE266_PLL_204_000M 0x00000764 |
| 767 | #define CLE266_PLL_218_500M 0x0000065C |
| 768 | #define CLE266_PLL_234_000M 0x00000662 |
| 769 | #define CLE266_PLL_267_250M 0x00000670 |
| 770 | #define CLE266_PLL_297_500M 0x000005E6 |
| 771 | #define CLE266_PLL_74_481M 0x0000051A |
| 772 | #define CLE266_PLL_172_798M 0x00004579 |
| 773 | #define CLE266_PLL_122_614M 0x0000073C |
| 774 | |
| 775 | /* K800 PLL value |
| 776 | */ |
| 777 | #define K800_PLL_25_175M 0x00539001 |
| 778 | #define K800_PLL_26_880M 0x001C8C80 |
| 779 | #define K800_PLL_29_581M 0x00409080 |
| 780 | #define K800_PLL_31_490M 0x006F9001 |
| 781 | #define K800_PLL_31_500M 0x008B9002 |
| 782 | #define K800_PLL_31_728M 0x00AF9003 |
| 783 | #define K800_PLL_32_668M 0x00909002 |
| 784 | #define K800_PLL_36_000M 0x009F9002 |
| 785 | #define K800_PLL_40_000M 0x00578C02 |
| 786 | #define K800_PLL_41_291M 0x00438C01 |
| 787 | #define K800_PLL_43_163M 0x00778C03 |
| 788 | #define K800_PLL_45_250M 0x007D8C83 /* 45.46MHz */ |
| 789 | #define K800_PLL_46_000M 0x00658C02 |
| 790 | #define K800_PLL_46_996M 0x00818C83 |
| 791 | #define K800_PLL_48_000M 0x00848C83 |
| 792 | #define K800_PLL_48_875M 0x00508C81 |
| 793 | #define K800_PLL_49_500M 0x00518C01 |
| 794 | #define K800_PLL_52_406M 0x00738C02 |
| 795 | #define K800_PLL_52_977M 0x00928C83 |
| 796 | #define K800_PLL_56_250M 0x007C8C02 |
| 797 | #define K800_PLL_60_466M 0x00A78C83 |
| 798 | #define K800_PLL_61_500M 0x00AA8C83 |
| 799 | #define K800_PLL_65_000M 0x006B8C01 |
| 800 | #define K800_PLL_65_178M 0x00B48C83 |
| 801 | #define K800_PLL_66_750M 0x00948C82 /* 67.116MHz */ |
| 802 | #define K800_PLL_68_179M 0x00708C01 |
| 803 | #define K800_PLL_69_924M 0x00C18C83 |
| 804 | #define K800_PLL_70_159M 0x00C28C83 |
| 805 | #define K800_PLL_72_000M 0x009F8C82 |
| 806 | #define K800_PLL_74_270M 0x00ce0c03 |
| 807 | #define K800_PLL_78_750M 0x00408801 |
| 808 | #define K800_PLL_80_136M 0x00428801 |
| 809 | #define K800_PLL_83_375M 0x005B0882 |
| 810 | #define K800_PLL_83_950M 0x00738803 |
| 811 | #define K800_PLL_84_750M 0x00748883 /* 84.477MHz */ |
| 812 | #define K800_PLL_85_860M 0x00768883 |
| 813 | #define K800_PLL_88_750M 0x007A8883 |
| 814 | #define K800_PLL_94_500M 0x00828803 |
| 815 | #define K800_PLL_97_750M 0x00878883 |
| 816 | #define K800_PLL_101_000M 0x008B8883 |
| 817 | #define K800_PLL_106_500M 0x00758882 /* 106.491463 MHz */ |
| 818 | #define K800_PLL_108_000M 0x00778882 |
| 819 | #define K800_PLL_113_309M 0x005D8881 |
| 820 | #define K800_PLL_118_840M 0x00A48883 |
| 821 | #define K800_PLL_119_000M 0x00838882 |
| 822 | #define K800_PLL_121_750M 0x00A88883 /* 121.704MHz */ |
| 823 | #define K800_PLL_125_104M 0x00688801 |
| 824 | #define K800_PLL_133_308M 0x005D8801 |
| 825 | #define K800_PLL_135_000M 0x001A4081 |
| 826 | #define K800_PLL_136_700M 0x00BD8883 |
| 827 | #define K800_PLL_138_400M 0x00728881 |
| 828 | #define K800_PLL_146_760M 0x00CC8883 |
| 829 | #define K800_PLL_148_500M 0x00ce0803 |
| 830 | #define K800_PLL_153_920M 0x00548482 |
| 831 | #define K800_PLL_156_000M 0x006B8483 |
| 832 | #define K800_PLL_157_500M 0x00142080 |
| 833 | #define K800_PLL_162_000M 0x006F8483 |
| 834 | #define K800_PLL_187_000M 0x00818483 |
| 835 | #define K800_PLL_193_295M 0x004F8481 |
| 836 | #define K800_PLL_202_500M 0x00538481 |
| 837 | #define K800_PLL_204_000M 0x008D8483 |
| 838 | #define K800_PLL_218_500M 0x00978483 |
| 839 | #define K800_PLL_234_000M 0x00608401 |
| 840 | #define K800_PLL_267_250M 0x006E8481 |
| 841 | #define K800_PLL_297_500M 0x00A48402 |
| 842 | #define K800_PLL_74_481M 0x007B8C81 |
| 843 | #define K800_PLL_172_798M 0x00778483 |
| 844 | #define K800_PLL_122_614M 0x00878882 |
| 845 | |
| 846 | /* PLL for VT3324 */ |
| 847 | #define CX700_25_175M 0x008B1003 |
| 848 | #define CX700_26_719M 0x00931003 |
| 849 | #define CX700_26_880M 0x00941003 |
| 850 | #define CX700_29_581M 0x00A49003 |
| 851 | #define CX700_31_490M 0x00AE1003 |
| 852 | #define CX700_31_500M 0x00AE1003 |
| 853 | #define CX700_31_728M 0x00AF1003 |
| 854 | #define CX700_32_668M 0x00B51003 |
| 855 | #define CX700_36_000M 0x00C81003 |
| 856 | #define CX700_40_000M 0x006E0C03 |
| 857 | #define CX700_41_291M 0x00710C03 |
| 858 | #define CX700_43_163M 0x00770C03 |
| 859 | #define CX700_45_250M 0x007D0C03 /* 45.46MHz */ |
| 860 | #define CX700_46_000M 0x007F0C03 |
| 861 | #define CX700_46_996M 0x00818C83 |
| 862 | #define CX700_48_000M 0x00840C03 |
| 863 | #define CX700_48_875M 0x00508C81 |
| 864 | #define CX700_49_500M 0x00880C03 |
| 865 | #define CX700_52_406M 0x00730C02 |
| 866 | #define CX700_52_977M 0x00920C03 |
| 867 | #define CX700_56_250M 0x009B0C03 |
| 868 | #define CX700_60_466M 0x00460C00 |
| 869 | #define CX700_61_500M 0x00AA0C03 |
| 870 | #define CX700_65_000M 0x006B0C01 |
| 871 | #define CX700_65_178M 0x006B0C01 |
| 872 | #define CX700_66_750M 0x00940C02 /*67.116MHz */ |
| 873 | #define CX700_68_179M 0x00BC0C03 |
| 874 | #define CX700_69_924M 0x00C10C03 |
| 875 | #define CX700_70_159M 0x00C20C03 |
| 876 | #define CX700_72_000M 0x009F0C02 |
| 877 | #define CX700_74_270M 0x00CE0C03 |
| 878 | #define CX700_74_481M 0x00CE0C03 |
| 879 | #define CX700_78_750M 0x006C0803 |
| 880 | #define CX700_80_136M 0x006E0803 |
| 881 | #define CX700_83_375M 0x005B0882 |
| 882 | #define CX700_83_950M 0x00730803 |
| 883 | #define CX700_84_750M 0x00740803 /* 84.537Mhz */ |
| 884 | #define CX700_85_860M 0x00760803 |
| 885 | #define CX700_88_750M 0x00AC8885 |
| 886 | #define CX700_94_500M 0x00820803 |
| 887 | #define CX700_97_750M 0x00870803 |
| 888 | #define CX700_101_000M 0x008B0803 |
| 889 | #define CX700_106_500M 0x00750802 |
| 890 | #define CX700_108_000M 0x00950803 |
| 891 | #define CX700_113_309M 0x005D0801 |
| 892 | #define CX700_118_840M 0x00A40803 |
| 893 | #define CX700_119_000M 0x00830802 |
| 894 | #define CX700_121_750M 0x00420800 /* 121.704MHz */ |
| 895 | #define CX700_125_104M 0x00AD0803 |
| 896 | #define CX700_133_308M 0x00930802 |
| 897 | #define CX700_135_000M 0x00950802 |
| 898 | #define CX700_136_700M 0x00BD0803 |
| 899 | #define CX700_138_400M 0x00720801 |
| 900 | #define CX700_146_760M 0x00CC0803 |
| 901 | #define CX700_148_500M 0x00a40802 |
| 902 | #define CX700_153_920M 0x00540402 |
| 903 | #define CX700_156_000M 0x006B0403 |
| 904 | #define CX700_157_500M 0x006C0403 |
| 905 | #define CX700_162_000M 0x006F0403 |
| 906 | #define CX700_172_798M 0x00770403 |
| 907 | #define CX700_187_000M 0x00810403 |
| 908 | #define CX700_193_295M 0x00850403 |
| 909 | #define CX700_202_500M 0x008C0403 |
| 910 | #define CX700_204_000M 0x008D0403 |
| 911 | #define CX700_218_500M 0x00970403 |
| 912 | #define CX700_234_000M 0x00600401 |
| 913 | #define CX700_267_250M 0x00B90403 |
| 914 | #define CX700_297_500M 0x00CE0403 |
| 915 | #define CX700_122_614M 0x00870802 |
| 916 | |
| Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 917 | /* PLL for VX855 */ |
| 918 | #define VX855_22_000M 0x007B1005 |
| 919 | #define VX855_25_175M 0x008D1005 |
| 920 | #define VX855_26_719M 0x00961005 |
| 921 | #define VX855_26_880M 0x00961005 |
| 922 | #define VX855_27_000M 0x00971005 |
| 923 | #define VX855_29_581M 0x00A51005 |
| 924 | #define VX855_29_829M 0x00641003 |
| 925 | #define VX855_31_490M 0x00B01005 |
| 926 | #define VX855_31_500M 0x00B01005 |
| 927 | #define VX855_31_728M 0x008E1004 |
| 928 | #define VX855_32_668M 0x00921004 |
| 929 | #define VX855_36_000M 0x00A11004 |
| 930 | #define VX855_40_000M 0x00700C05 |
| 931 | #define VX855_41_291M 0x00730C05 |
| 932 | #define VX855_43_163M 0x00790C05 |
| 933 | #define VX855_45_250M 0x007F0C05 /* 45.46MHz */ |
| 934 | #define VX855_46_000M 0x00670C04 |
| 935 | #define VX855_46_996M 0x00690C04 |
| 936 | #define VX855_48_000M 0x00860C05 |
| 937 | #define VX855_48_875M 0x00890C05 |
| 938 | #define VX855_49_500M 0x00530C03 |
| 939 | #define VX855_52_406M 0x00580C03 |
| 940 | #define VX855_52_977M 0x00940C05 |
| 941 | #define VX855_56_250M 0x009D0C05 |
| 942 | #define VX855_60_466M 0x00A90C05 |
| 943 | #define VX855_61_500M 0x00AC0C05 |
| 944 | #define VX855_65_000M 0x006D0C03 |
| 945 | #define VX855_65_178M 0x00B60C05 |
| 946 | #define VX855_66_750M 0x00700C03 /*67.116MHz */ |
| 947 | #define VX855_67_295M 0x00BC0C05 |
| 948 | #define VX855_68_179M 0x00BF0C05 |
| 949 | #define VX855_68_369M 0x00BF0C05 |
| 950 | #define VX855_69_924M 0x00C30C05 |
| 951 | #define VX855_70_159M 0x00C30C05 |
| 952 | #define VX855_72_000M 0x00A10C04 |
| 953 | #define VX855_73_023M 0x00CC0C05 |
| 954 | #define VX855_74_481M 0x00D10C05 |
| 955 | #define VX855_78_750M 0x006E0805 |
| 956 | #define VX855_79_466M 0x006F0805 |
| 957 | #define VX855_80_136M 0x00700805 |
| 958 | #define VX855_81_627M 0x00720805 |
| 959 | #define VX855_83_375M 0x00750805 |
| 960 | #define VX855_83_527M 0x00750805 |
| 961 | #define VX855_83_950M 0x00750805 |
| 962 | #define VX855_84_537M 0x00760805 |
| 963 | #define VX855_84_750M 0x00760805 /* 84.537Mhz */ |
| 964 | #define VX855_85_500M 0x00760805 /* 85.909080 MHz*/ |
| 965 | #define VX855_85_860M 0x00760805 |
| 966 | #define VX855_85_909M 0x00760805 |
| 967 | #define VX855_88_750M 0x007C0805 |
| 968 | #define VX855_89_489M 0x007D0805 |
| 969 | #define VX855_94_500M 0x00840805 |
| 970 | #define VX855_96_648M 0x00870805 |
| 971 | #define VX855_97_750M 0x00890805 |
| 972 | #define VX855_101_000M 0x008D0805 |
| 973 | #define VX855_106_500M 0x00950805 |
| 974 | #define VX855_108_000M 0x00970805 |
| 975 | #define VX855_110_125M 0x00990805 |
| 976 | #define VX855_112_000M 0x009D0805 |
| 977 | #define VX855_113_309M 0x009F0805 |
| 978 | #define VX855_115_000M 0x00A10805 |
| 979 | #define VX855_118_840M 0x00A60805 |
| 980 | #define VX855_119_000M 0x00A70805 |
| 981 | #define VX855_121_750M 0x00AA0805 /* 121.704MHz */ |
| 982 | #define VX855_122_614M 0x00AC0805 |
| 983 | #define VX855_126_266M 0x00B10805 |
| 984 | #define VX855_130_250M 0x00B60805 /* 130.250 */ |
| 985 | #define VX855_135_000M 0x00BD0805 |
| 986 | #define VX855_136_700M 0x00BF0805 |
| 987 | #define VX855_137_750M 0x00C10805 |
| 988 | #define VX855_138_400M 0x00C20805 |
| 989 | #define VX855_144_300M 0x00CA0805 |
| 990 | #define VX855_146_760M 0x00CE0805 |
| 991 | #define VX855_148_500M 0x00D00805 |
| 992 | #define VX855_153_920M 0x00540402 |
| 993 | #define VX855_156_000M 0x006C0405 |
| 994 | #define VX855_156_867M 0x006E0405 |
| 995 | #define VX855_157_500M 0x006E0405 |
| 996 | #define VX855_162_000M 0x00710405 |
| 997 | #define VX855_172_798M 0x00790405 |
| 998 | #define VX855_187_000M 0x00830405 |
| 999 | #define VX855_193_295M 0x00870405 |
| 1000 | #define VX855_202_500M 0x008E0405 |
| 1001 | #define VX855_204_000M 0x008F0405 |
| 1002 | #define VX855_218_500M 0x00990405 |
| 1003 | #define VX855_229_500M 0x00A10405 |
| 1004 | #define VX855_234_000M 0x00A40405 |
| 1005 | #define VX855_267_250M 0x00BB0405 |
| 1006 | #define VX855_297_500M 0x00D00405 |
| 1007 | #define VX855_339_500M 0x00770005 |
| 1008 | #define VX855_340_772M 0x00770005 |
| 1009 | |
| 1010 | |
| Joseph Chan | 37773cf | 2008-10-15 22:03:26 -0700 | [diff] [blame] | 1011 | /* Definition CRTC Timing Index */ |
| 1012 | #define H_TOTAL_INDEX 0 |
| 1013 | #define H_ADDR_INDEX 1 |
| 1014 | #define H_BLANK_START_INDEX 2 |
| 1015 | #define H_BLANK_END_INDEX 3 |
| 1016 | #define H_SYNC_START_INDEX 4 |
| 1017 | #define H_SYNC_END_INDEX 5 |
| 1018 | #define V_TOTAL_INDEX 6 |
| 1019 | #define V_ADDR_INDEX 7 |
| 1020 | #define V_BLANK_START_INDEX 8 |
| 1021 | #define V_BLANK_END_INDEX 9 |
| 1022 | #define V_SYNC_START_INDEX 10 |
| 1023 | #define V_SYNC_END_INDEX 11 |
| 1024 | #define H_TOTAL_SHADOW_INDEX 12 |
| 1025 | #define H_BLANK_END_SHADOW_INDEX 13 |
| 1026 | #define V_TOTAL_SHADOW_INDEX 14 |
| 1027 | #define V_ADDR_SHADOW_INDEX 15 |
| 1028 | #define V_BLANK_SATRT_SHADOW_INDEX 16 |
| 1029 | #define V_BLANK_END_SHADOW_INDEX 17 |
| 1030 | #define V_SYNC_SATRT_SHADOW_INDEX 18 |
| 1031 | #define V_SYNC_END_SHADOW_INDEX 19 |
| 1032 | |
| 1033 | /* Definition Video Mode Pixel Clock (picoseconds) |
| 1034 | */ |
| 1035 | #define RES_480X640_60HZ_PIXCLOCK 39722 |
| 1036 | #define RES_640X480_60HZ_PIXCLOCK 39722 |
| 1037 | #define RES_640X480_75HZ_PIXCLOCK 31747 |
| 1038 | #define RES_640X480_85HZ_PIXCLOCK 27777 |
| 1039 | #define RES_640X480_100HZ_PIXCLOCK 23168 |
| 1040 | #define RES_640X480_120HZ_PIXCLOCK 19081 |
| 1041 | #define RES_720X480_60HZ_PIXCLOCK 37020 |
| 1042 | #define RES_720X576_60HZ_PIXCLOCK 30611 |
| 1043 | #define RES_800X600_60HZ_PIXCLOCK 25000 |
| 1044 | #define RES_800X600_75HZ_PIXCLOCK 20203 |
| 1045 | #define RES_800X600_85HZ_PIXCLOCK 17777 |
| 1046 | #define RES_800X600_100HZ_PIXCLOCK 14667 |
| 1047 | #define RES_800X600_120HZ_PIXCLOCK 11912 |
| 1048 | #define RES_800X480_60HZ_PIXCLOCK 33805 |
| 1049 | #define RES_848X480_60HZ_PIXCLOCK 31756 |
| 1050 | #define RES_856X480_60HZ_PIXCLOCK 31518 |
| 1051 | #define RES_1024X512_60HZ_PIXCLOCK 24218 |
| 1052 | #define RES_1024X600_60HZ_PIXCLOCK 20460 |
| 1053 | #define RES_1024X768_60HZ_PIXCLOCK 15385 |
| 1054 | #define RES_1024X768_75HZ_PIXCLOCK 12699 |
| 1055 | #define RES_1024X768_85HZ_PIXCLOCK 10582 |
| 1056 | #define RES_1024X768_100HZ_PIXCLOCK 8825 |
| 1057 | #define RES_1152X864_75HZ_PIXCLOCK 9259 |
| 1058 | #define RES_1280X768_60HZ_PIXCLOCK 12480 |
| 1059 | #define RES_1280X800_60HZ_PIXCLOCK 11994 |
| 1060 | #define RES_1280X960_60HZ_PIXCLOCK 9259 |
| 1061 | #define RES_1280X1024_60HZ_PIXCLOCK 9260 |
| 1062 | #define RES_1280X1024_75HZ_PIXCLOCK 7408 |
| 1063 | #define RES_1280X768_85HZ_PIXCLOCK 6349 |
| 1064 | #define RES_1440X1050_60HZ_PIXCLOCK 7993 |
| 1065 | #define RES_1600X1200_60HZ_PIXCLOCK 6172 |
| 1066 | #define RES_1600X1200_75HZ_PIXCLOCK 4938 |
| 1067 | #define RES_1280X720_60HZ_PIXCLOCK 13426 |
| 1068 | #define RES_1920X1080_60HZ_PIXCLOCK 5787 |
| 1069 | #define RES_1400X1050_60HZ_PIXCLOCK 8214 |
| 1070 | #define RES_1400X1050_75HZ_PIXCLOCK 6410 |
| 1071 | #define RES_1368X768_60HZ_PIXCLOCK 11647 |
| 1072 | #define RES_960X600_60HZ_PIXCLOCK 22099 |
| 1073 | #define RES_1000X600_60HZ_PIXCLOCK 20834 |
| 1074 | #define RES_1024X576_60HZ_PIXCLOCK 21278 |
| 1075 | #define RES_1088X612_60HZ_PIXCLOCK 18877 |
| 1076 | #define RES_1152X720_60HZ_PIXCLOCK 14981 |
| 1077 | #define RES_1200X720_60HZ_PIXCLOCK 14253 |
| 1078 | #define RES_1280X600_60HZ_PIXCLOCK 16260 |
| 1079 | #define RES_1280X720_50HZ_PIXCLOCK 16538 |
| 1080 | #define RES_1280X768_50HZ_PIXCLOCK 15342 |
| 1081 | #define RES_1366X768_50HZ_PIXCLOCK 14301 |
| 1082 | #define RES_1366X768_60HZ_PIXCLOCK 11646 |
| 1083 | #define RES_1360X768_60HZ_PIXCLOCK 11799 |
| 1084 | #define RES_1440X900_60HZ_PIXCLOCK 9390 |
| 1085 | #define RES_1440X900_75HZ_PIXCLOCK 7315 |
| 1086 | #define RES_1600X900_60HZ_PIXCLOCK 8415 |
| 1087 | #define RES_1600X1024_60HZ_PIXCLOCK 7315 |
| 1088 | #define RES_1680X1050_60HZ_PIXCLOCK 6814 |
| 1089 | #define RES_1680X1050_75HZ_PIXCLOCK 5348 |
| 1090 | #define RES_1792X1344_60HZ_PIXCLOCK 4902 |
| 1091 | #define RES_1856X1392_60HZ_PIXCLOCK 4577 |
| 1092 | #define RES_1920X1200_60HZ_PIXCLOCK 5173 |
| 1093 | #define RES_1920X1440_60HZ_PIXCLOCK 4274 |
| 1094 | #define RES_1920X1440_75HZ_PIXCLOCK 3367 |
| 1095 | #define RES_2048X1536_60HZ_PIXCLOCK 3742 |
| 1096 | |
| 1097 | #define RES_1360X768_RB_60HZ_PIXCLOCK 13889 |
| 1098 | #define RES_1400X1050_RB_60HZ_PIXCLOCK 9901 |
| 1099 | #define RES_1440X900_RB_60HZ_PIXCLOCK 11268 |
| 1100 | #define RES_1600X900_RB_60HZ_PIXCLOCK 10230 |
| 1101 | #define RES_1680X1050_RB_60HZ_PIXCLOCK 8403 |
| 1102 | #define RES_1920X1080_RB_60HZ_PIXCLOCK 7225 |
| 1103 | #define RES_1920X1200_RB_60HZ_PIXCLOCK 6497 |
| 1104 | |
| 1105 | /* LCD display method |
| 1106 | */ |
| 1107 | #define LCD_EXPANDSION 0x00 |
| 1108 | #define LCD_CENTERING 0x01 |
| 1109 | |
| 1110 | /* LCD mode |
| 1111 | */ |
| 1112 | #define LCD_OPENLDI 0x00 |
| 1113 | #define LCD_SPWG 0x01 |
| 1114 | |
| 1115 | /* Define display timing |
| 1116 | */ |
| 1117 | struct display_timing { |
| 1118 | u16 hor_total; |
| 1119 | u16 hor_addr; |
| 1120 | u16 hor_blank_start; |
| 1121 | u16 hor_blank_end; |
| 1122 | u16 hor_sync_start; |
| 1123 | u16 hor_sync_end; |
| 1124 | u16 ver_total; |
| 1125 | u16 ver_addr; |
| 1126 | u16 ver_blank_start; |
| 1127 | u16 ver_blank_end; |
| 1128 | u16 ver_sync_start; |
| 1129 | u16 ver_sync_end; |
| 1130 | }; |
| 1131 | |
| 1132 | struct crt_mode_table { |
| 1133 | int refresh_rate; |
| 1134 | unsigned long clk; |
| 1135 | int h_sync_polarity; |
| 1136 | int v_sync_polarity; |
| 1137 | struct display_timing crtc; |
| 1138 | }; |
| 1139 | |
| 1140 | struct io_reg { |
| 1141 | int port; |
| 1142 | u8 index; |
| 1143 | u8 mask; |
| 1144 | u8 value; |
| 1145 | }; |
| 1146 | |
| 1147 | #endif /* __SHARE_H__ */ |