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Karl Beldan44524a02016-08-05 20:29:49 +00001/*
2 * Copyright (c) 2016 BayLibre, Inc.
3 *
4 * Licensed under GPLv2.
5 */
6/dts-v1/;
7#include "da850.dtsi"
8#include <dt-bindings/gpio/gpio.h>
Bartosz Golaszewskie3d9e1e2016-12-19 10:53:54 +01009#include <dt-bindings/input/input.h>
Karl Beldan44524a02016-08-05 20:29:49 +000010
11/ {
12 model = "DA850/AM1808/OMAP-L138 LCDK";
13 compatible = "ti,da850-lcdk", "ti,da850";
14
15 aliases {
16 serial2 = &serial2;
Fabien Parente177e732016-11-24 15:35:45 +010017 ethernet0 = &eth0;
Karl Beldan44524a02016-08-05 20:29:49 +000018 };
19
20 chosen {
21 stdout-path = "serial2:115200n8";
22 };
23
Sekhar Nori01de0be2018-04-18 14:54:08 +053024 memory@c0000000 {
25 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
Karl Beldan44524a02016-08-05 20:29:49 +000026 reg = <0xc0000000 0x08000000>;
27 };
Karl Beldan9d05b382016-08-17 12:54:54 +000028
Suman Annad9fe22b2017-09-18 19:28:32 -050029 reserved-memory {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 ranges;
33
34 dsp_memory_region: dsp-memory@c3000000 {
35 compatible = "shared-dma-pool";
36 reg = <0xc3000000 0x1000000>;
37 reusable;
38 status = "okay";
39 };
40 };
41
Karl Beldan9d05b382016-08-17 12:54:54 +000042 sound {
43 compatible = "simple-audio-card";
44 simple-audio-card,name = "DA850/OMAP-L138 LCDK";
45 simple-audio-card,widgets =
46 "Line", "Line In",
Peter Ujfalusi7dd2e8f2018-12-19 13:47:27 +020047 "Line", "Line Out",
48 "Microphone", "Mic Jack";
Karl Beldan9d05b382016-08-17 12:54:54 +000049 simple-audio-card,routing =
50 "LINE1L", "Line In",
51 "LINE1R", "Line In",
52 "Line Out", "LLOUT",
Peter Ujfalusi7dd2e8f2018-12-19 13:47:27 +020053 "Line Out", "RLOUT",
54 "MIC3L", "Mic Jack",
55 "MIC3R", "Mic Jack",
56 "Mic Jack", "Mic Bias";
Karl Beldan9d05b382016-08-17 12:54:54 +000057 simple-audio-card,format = "dsp_b";
58 simple-audio-card,bitclock-master = <&link0_codec>;
59 simple-audio-card,frame-master = <&link0_codec>;
60 simple-audio-card,bitclock-inversion;
61
62 simple-audio-card,cpu {
63 sound-dai = <&mcasp0>;
64 system-clock-frequency = <24576000>;
65 };
66
67 link0_codec: simple-audio-card,codec {
68 sound-dai = <&tlv320aic3106>;
69 system-clock-frequency = <24576000>;
70 };
71 };
Bartosz Golaszewskie3d9e1e2016-12-19 10:53:54 +010072
73 gpio-keys {
74 compatible = "gpio-keys";
75 autorepeat;
76
77 user1 {
78 label = "GPIO Key USER1";
79 linux,code = <BTN_0>;
80 gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
81 };
82
83 user2 {
84 label = "GPIO Key USER2";
85 linux,code = <BTN_1>;
86 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
87 };
88 };
Bartosz Golaszewskic9825342016-12-13 11:09:18 +010089
90 vga-bridge {
91 compatible = "ti,ths8135";
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 ports {
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 port@0 {
100 reg = <0>;
101
102 vga_bridge_in: endpoint {
103 remote-endpoint = <&lcdc_out_vga>;
104 };
105 };
106
107 port@1 {
108 reg = <1>;
109
110 vga_bridge_out: endpoint {
111 remote-endpoint = <&vga_con_in>;
112 };
113 };
114 };
115 };
116
117 vga {
118 compatible = "vga-connector";
119
120 ddc-i2c-bus = <&i2c0>;
121
122 port {
123 vga_con_in: endpoint {
124 remote-endpoint = <&vga_bridge_out>;
125 };
126 };
127 };
Karl Beldan44524a02016-08-05 20:29:49 +0000128};
129
David Lechner3652e272018-05-18 11:48:29 -0500130&ref_clk {
131 clock-frequency = <24000000>;
132};
133
Karl Beldan44524a02016-08-05 20:29:49 +0000134&pmx_core {
135 status = "okay";
Karl Beldan9d05b382016-08-17 12:54:54 +0000136
137 mcasp0_pins: pinmux_mcasp0_pins {
138 pinctrl-single,bits = <
139 /* AHCLKX AFSX ACLKX */
140 0x00 0x00101010 0x00f0f0f0
141 /* ARX13 ARX14 */
142 0x04 0x00000110 0x00000ff0
143 >;
144 };
Karl Beldan9304af12016-09-08 11:33:24 -0700145
146 nand_pins: nand_pins {
147 pinctrl-single,bits = <
148 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
149 0x1c 0x10110010 0xf0ff00f0
150 /*
151 * EMA_D[0], EMA_D[1], EMA_D[2],
152 * EMA_D[3], EMA_D[4], EMA_D[5],
153 * EMA_D[6], EMA_D[7]
154 */
155 0x24 0x11111111 0xffffffff
156 /*
157 * EMA_D[8], EMA_D[9], EMA_D[10],
158 * EMA_D[11], EMA_D[12], EMA_D[13],
159 * EMA_D[14], EMA_D[15]
160 */
161 0x20 0x11111111 0xffffffff
162 /* EMA_A[1], EMA_A[2] */
163 0x30 0x01100000 0x0ff00000
164 >;
165 };
Karl Beldan44524a02016-08-05 20:29:49 +0000166};
167
168&serial2 {
169 pinctrl-names = "default";
170 pinctrl-0 = <&serial2_rxtx_pins>;
171 status = "okay";
172};
173
174&wdt {
175 status = "okay";
176};
177
178&rtc0 {
179 status = "okay";
180};
181
182&gpio {
183 status = "okay";
184};
185
David Lechner3652e272018-05-18 11:48:29 -0500186&sata_refclk {
187 status = "okay";
188 clock-frequency = <100000000>;
189};
190
Bartosz Golaszewski91aba932017-01-30 11:02:11 +0100191&sata {
192 status = "okay";
193};
194
Karl Beldan44524a02016-08-05 20:29:49 +0000195&mdio {
196 pinctrl-names = "default";
197 pinctrl-0 = <&mdio_pins>;
198 bus_freq = <2200000>;
199 status = "okay";
200};
201
202&eth0 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&mii_pins>;
205 status = "okay";
206};
207
208&mmc0 {
209 max-frequency = <50000000>;
210 bus-width = <4>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc0_pins>;
Axel Haslama9aa4232016-11-21 16:41:55 +0100213 cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
Karl Beldan44524a02016-08-05 20:29:49 +0000214 status = "okay";
215};
Karl Beldan9d05b382016-08-17 12:54:54 +0000216
217&i2c0 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&i2c0_pins>;
220 clock-frequency = <100000>;
221 status = "okay";
222
223 tlv320aic3106: tlv320aic3106@18 {
224 #sound-dai-cells = <0>;
225 compatible = "ti,tlv320aic3106";
226 reg = <0x18>;
Peter Ujfalusi7dd2e8f2018-12-19 13:47:27 +0200227 adc-settle-ms = <40>;
228 ai3x-micbias-vg = <1>; /* 2.0V */
Karl Beldan9d05b382016-08-17 12:54:54 +0000229 status = "okay";
230 };
231};
232
233&mcasp0 {
234 #sound-dai-cells = <0>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&mcasp0_pins>;
237 status = "okay";
238
239 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
240 tdm-slots = <2>;
241 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
242 0 0 0 0
243 0 0 0 0
244 0 0 0 0
245 0 1 2 0
246 >;
247 tx-num-evt = <32>;
248 rx-num-evt = <32>;
249};
Karl Beldan9304af12016-09-08 11:33:24 -0700250
Alexandre Bailon83de0862016-11-16 12:07:36 +0100251&usb_phy {
252 status = "okay";
253};
254
255&usb0 {
256 status = "okay";
257};
258
Axel Haslam9e6612e2017-01-06 10:40:54 +0100259&usb1 {
260 status = "okay";
261};
262
Karl Beldan9304af12016-09-08 11:33:24 -0700263&aemif {
264 pinctrl-names = "default";
265 pinctrl-0 = <&nand_pins>;
266 status = "okay";
267 cs3 {
268 #address-cells = <2>;
269 #size-cells = <1>;
270 clock-ranges;
271 ranges;
272
273 ti,cs-chipselect = <3>;
274
275 nand@2000000,0 {
276 compatible = "ti,davinci-nand";
277 #address-cells = <1>;
278 #size-cells = <1>;
279 reg = <0 0x02000000 0x02000000
280 1 0x00000000 0x00008000>;
281
282 ti,davinci-chipselect = <1>;
283 ti,davinci-mask-ale = <0>;
284 ti,davinci-mask-cle = <0>;
285 ti,davinci-mask-chipsel = <0>;
286
287 ti,davinci-nand-buswidth = <16>;
288 ti,davinci-ecc-mode = "hw";
289 ti,davinci-ecc-bits = <4>;
290 ti,davinci-nand-use-bbt;
291
292 /*
293 * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
294 * "To boot from NAND Flash, the AIS should be written
295 * to NAND block 1 (NAND block 0 is not used by default)".
296 * The same doc mentions that for ROM "Silicon Revision 2.1",
297 * "Updated NAND boot mode to offer boot from block 0 or block 1".
298 * However the limitaion is left here by default for compatibility
299 * with older silicon and because it needs new boot pin settings
300 * not possible in stock LCDK.
301 */
302 partitions {
303 compatible = "fixed-partitions";
304 #address-cells = <1>;
305 #size-cells = <1>;
306
307 partition@0 {
308 label = "u-boot env";
309 reg = <0 0x020000>;
310 };
Mathieu Malaterre7669b122017-12-15 13:46:57 +0100311 partition@20000 {
Karl Beldan9304af12016-09-08 11:33:24 -0700312 /* The LCDK defaults to booting from this partition */
313 label = "u-boot";
314 reg = <0x020000 0x080000>;
315 };
Mathieu Malaterre7669b122017-12-15 13:46:57 +0100316 partition@a0000 {
Karl Beldan9304af12016-09-08 11:33:24 -0700317 label = "free space";
318 reg = <0x0a0000 0>;
319 };
320 };
321 };
322 };
323};
Bartosz Golaszewski878e9082016-11-24 10:31:24 +0100324
325&prictrl {
326 status = "okay";
327};
328
329&memctrl {
330 status = "okay";
331};
Bartosz Golaszewskic9825342016-12-13 11:09:18 +0100332
333&lcdc {
334 status = "okay";
335 pinctrl-names = "default";
336 pinctrl-0 = <&lcd_pins>;
337
338 port {
339 lcdc_out_vga: endpoint {
340 remote-endpoint = <&vga_bridge_in>;
341 };
342 };
343};
Kevin Hilman5280bc32017-01-09 12:55:28 -0800344
345&vpif {
346 pinctrl-names = "default";
347 pinctrl-0 = <&vpif_capture_pins>;
348 status = "okay";
Kevin Hilman5280bc32017-01-09 12:55:28 -0800349};
Suman Annad9fe22b2017-09-18 19:28:32 -0500350
351&dsp {
352 memory-region = <&dsp_memory_region>;
353 status = "okay";
354};