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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7db3cde5123e2acdd65ff7458628a9835c804b27 / . / arch / arm / boot / dts / omap24xx-clocks.dtsi
blob: 07af87edf0e2e4beccd1038f89f9effe032d5b3f [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]2/*
3 * Device Tree Source for OMAP24xx clock data
4 *
5 * Copyright (C) 2014 Texas Instruments, Inc.
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]6 */
Tero Kristo72b10ac2015-02-12 10:38:16 +0200[diff] [blame]7&scm_clocks {
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]8 mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
11 clocks = <&func_96m_ck>, <&mcbsp_clks>;
12 ti,bit-shift = <2>;
Tero Kristo72b10ac2015-02-12 10:38:16 +0200[diff] [blame]13 reg = <0x4>;
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]14 };
15
16 mcbsp1_fck: mcbsp1_fck {
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
19 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
20 };
21
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]22 mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
26 ti,bit-shift = <6>;
Tero Kristo72b10ac2015-02-12 10:38:16 +0200[diff] [blame]27 reg = <0x4>;
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]28 };
29
30 mcbsp2_fck: mcbsp2_fck {
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
33 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
34 };
35};
36
37&prcm_clocks {
38 func_32k_ck: func_32k_ck {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <32768>;
42 };
43
44 secure_32k_ck: secure_32k_ck {
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 virt_12m_ck: virt_12m_ck {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <12000000>;
54 };
55
56 virt_13m_ck: virt_13m_ck {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <13000000>;
60 };
61
62 virt_19200000_ck: virt_19200000_ck {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <19200000>;
66 };
67
68 virt_26m_ck: virt_26m_ck {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <26000000>;
72 };
73
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]74 aplls_clkin_ck: aplls_clkin_ck@540 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]75 #clock-cells = <0>;
76 compatible = "ti,mux-clock";
77 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
78 ti,bit-shift = <23>;
79 reg = <0x0540>;
80 };
81
82 aplls_clkin_x2_ck: aplls_clkin_x2_ck {
83 #clock-cells = <0>;
84 compatible = "fixed-factor-clock";
85 clocks = <&aplls_clkin_ck>;
86 clock-mult = <2>;
87 clock-div = <1>;
88 };
89
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]90 osc_ck: osc_ck@60 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]91 #clock-cells = <0>;
92 compatible = "ti,mux-clock";
93 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
94 ti,bit-shift = <6>;
95 reg = <0x0060>;
96 ti,index-starts-at-one;
97 };
98
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]99 sys_ck: sys_ck@60 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]100 #clock-cells = <0>;
101 compatible = "ti,divider-clock";
102 clocks = <&osc_ck>;
103 ti,bit-shift = <6>;
104 ti,max-div = <3>;
105 reg = <0x0060>;
106 ti,index-starts-at-one;
107 };
108
109 alt_ck: alt_ck {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <54000000>;
113 };
114
115 mcbsp_clks: mcbsp_clks {
116 #clock-cells = <0>;
117 compatible = "fixed-clock";
118 clock-frequency = <0x0>;
119 };
120
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]121 dpll_ck: dpll_ck@500 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]122 #clock-cells = <0>;
123 compatible = "ti,omap2-dpll-core-clock";
124 clocks = <&sys_ck>, <&sys_ck>;
125 reg = <0x0500>, <0x0540>;
126 };
127
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]128 apll96_ck: apll96_ck@500 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]129 #clock-cells = <0>;
130 compatible = "ti,omap2-apll-clock";
131 clocks = <&sys_ck>;
132 ti,bit-shift = <2>;
133 ti,idlest-shift = <8>;
134 ti,clock-frequency = <96000000>;
135 reg = <0x0500>, <0x0530>, <0x0520>;
136 };
137
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]138 apll54_ck: apll54_ck@500 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]139 #clock-cells = <0>;
140 compatible = "ti,omap2-apll-clock";
141 clocks = <&sys_ck>;
142 ti,bit-shift = <6>;
143 ti,idlest-shift = <9>;
144 ti,clock-frequency = <54000000>;
145 reg = <0x0500>, <0x0530>, <0x0520>;
146 };
147
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]148 func_54m_ck: func_54m_ck@540 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]149 #clock-cells = <0>;
150 compatible = "ti,mux-clock";
151 clocks = <&apll54_ck>, <&alt_ck>;
152 ti,bit-shift = <5>;
153 reg = <0x0540>;
154 };
155
156 core_ck: core_ck {
157 #clock-cells = <0>;
158 compatible = "fixed-factor-clock";
159 clocks = <&dpll_ck>;
160 clock-mult = <1>;
161 clock-div = <1>;
162 };
163
Javier Martinez Canillasb0062612016-06-27 15:20:42 -0400[diff] [blame]164 func_96m_ck: func_96m_ck@540 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]165 #clock-cells = <0>;
166 };
167
168 apll96_d2_ck: apll96_d2_ck {
169 #clock-cells = <0>;
170 compatible = "fixed-factor-clock";
171 clocks = <&apll96_ck>;
172 clock-mult = <1>;
173 clock-div = <2>;
174 };
175
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]176 func_48m_ck: func_48m_ck@540 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]177 #clock-cells = <0>;
178 compatible = "ti,mux-clock";
179 clocks = <&apll96_d2_ck>, <&alt_ck>;
180 ti,bit-shift = <3>;
181 reg = <0x0540>;
182 };
183
184 func_12m_ck: func_12m_ck {
185 #clock-cells = <0>;
186 compatible = "fixed-factor-clock";
187 clocks = <&func_48m_ck>;
188 clock-mult = <1>;
189 clock-div = <4>;
190 };
191
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]192 sys_clkout_src_gate: sys_clkout_src_gate@70 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]193 #clock-cells = <0>;
194 compatible = "ti,composite-no-wait-gate-clock";
195 clocks = <&core_ck>;
196 ti,bit-shift = <7>;
197 reg = <0x0070>;
198 };
199
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]200 sys_clkout_src_mux: sys_clkout_src_mux@70 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]201 #clock-cells = <0>;
202 compatible = "ti,composite-mux-clock";
203 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
204 reg = <0x0070>;
205 };
206
207 sys_clkout_src: sys_clkout_src {
208 #clock-cells = <0>;
209 compatible = "ti,composite-clock";
210 clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
211 };
212
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]213 sys_clkout: sys_clkout@70 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]214 #clock-cells = <0>;
215 compatible = "ti,divider-clock";
216 clocks = <&sys_clkout_src>;
217 ti,bit-shift = <3>;
218 ti,max-div = <64>;
219 reg = <0x0070>;
220 ti,index-power-of-two;
221 };
222
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]223 emul_ck: emul_ck@78 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]224 #clock-cells = <0>;
225 compatible = "ti,gate-clock";
226 clocks = <&func_54m_ck>;
227 ti,bit-shift = <0>;
228 reg = <0x0078>;
229 };
230
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]231 mpu_ck: mpu_ck@140 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]232 #clock-cells = <0>;
233 compatible = "ti,divider-clock";
234 clocks = <&core_ck>;
235 ti,max-div = <31>;
236 reg = <0x0140>;
237 ti,index-starts-at-one;
238 };
239
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]240 dsp_gate_fck: dsp_gate_fck@800 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]241 #clock-cells = <0>;
242 compatible = "ti,composite-gate-clock";
243 clocks = <&core_ck>;
244 ti,bit-shift = <0>;
245 reg = <0x0800>;
246 };
247
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]248 dsp_div_fck: dsp_div_fck@840 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]249 #clock-cells = <0>;
250 compatible = "ti,composite-divider-clock";
251 clocks = <&core_ck>;
252 reg = <0x0840>;
253 };
254
255 dsp_fck: dsp_fck {
256 #clock-cells = <0>;
257 compatible = "ti,composite-clock";
258 clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
259 };
260
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]261 core_l3_ck: core_l3_ck@240 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]262 #clock-cells = <0>;
263 compatible = "ti,divider-clock";
264 clocks = <&core_ck>;
265 ti,max-div = <31>;
266 reg = <0x0240>;
267 ti,index-starts-at-one;
268 };
269
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]270 gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]271 #clock-cells = <0>;
272 compatible = "ti,composite-gate-clock";
273 clocks = <&core_l3_ck>;
274 ti,bit-shift = <2>;
275 reg = <0x0300>;
276 };
277
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]278 gfx_3d_div_fck: gfx_3d_div_fck@340 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]279 #clock-cells = <0>;
280 compatible = "ti,composite-divider-clock";
281 clocks = <&core_l3_ck>;
282 ti,max-div = <4>;
283 reg = <0x0340>;
284 ti,index-starts-at-one;
285 };
286
287 gfx_3d_fck: gfx_3d_fck {
288 #clock-cells = <0>;
289 compatible = "ti,composite-clock";
290 clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
291 };
292
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]293 gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]294 #clock-cells = <0>;
295 compatible = "ti,composite-gate-clock";
296 clocks = <&core_l3_ck>;
297 ti,bit-shift = <1>;
298 reg = <0x0300>;
299 };
300
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]301 gfx_2d_div_fck: gfx_2d_div_fck@340 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]302 #clock-cells = <0>;
303 compatible = "ti,composite-divider-clock";
304 clocks = <&core_l3_ck>;
305 ti,max-div = <4>;
306 reg = <0x0340>;
307 ti,index-starts-at-one;
308 };
309
310 gfx_2d_fck: gfx_2d_fck {
311 #clock-cells = <0>;
312 compatible = "ti,composite-clock";
313 clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
314 };
315
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]316 gfx_ick: gfx_ick@310 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]317 #clock-cells = <0>;
318 compatible = "ti,wait-gate-clock";
319 clocks = <&core_l3_ck>;
320 ti,bit-shift = <0>;
321 reg = <0x0310>;
322 };
323
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]324 l4_ck: l4_ck@240 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]325 #clock-cells = <0>;
326 compatible = "ti,divider-clock";
327 clocks = <&core_l3_ck>;
328 ti,bit-shift = <5>;
329 ti,max-div = <3>;
330 reg = <0x0240>;
331 ti,index-starts-at-one;
332 };
333
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]334 dss_ick: dss_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]335 #clock-cells = <0>;
336 compatible = "ti,omap3-no-wait-interface-clock";
337 clocks = <&l4_ck>;
338 ti,bit-shift = <0>;
339 reg = <0x0210>;
340 };
341
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]342 dss1_gate_fck: dss1_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]343 #clock-cells = <0>;
344 compatible = "ti,composite-no-wait-gate-clock";
345 clocks = <&core_ck>;
346 ti,bit-shift = <0>;
347 reg = <0x0200>;
348 };
349
350 core_d2_ck: core_d2_ck {
351 #clock-cells = <0>;
352 compatible = "fixed-factor-clock";
353 clocks = <&core_ck>;
354 clock-mult = <1>;
355 clock-div = <2>;
356 };
357
358 core_d3_ck: core_d3_ck {
359 #clock-cells = <0>;
360 compatible = "fixed-factor-clock";
361 clocks = <&core_ck>;
362 clock-mult = <1>;
363 clock-div = <3>;
364 };
365
366 core_d4_ck: core_d4_ck {
367 #clock-cells = <0>;
368 compatible = "fixed-factor-clock";
369 clocks = <&core_ck>;
370 clock-mult = <1>;
371 clock-div = <4>;
372 };
373
374 core_d5_ck: core_d5_ck {
375 #clock-cells = <0>;
376 compatible = "fixed-factor-clock";
377 clocks = <&core_ck>;
378 clock-mult = <1>;
379 clock-div = <5>;
380 };
381
382 core_d6_ck: core_d6_ck {
383 #clock-cells = <0>;
384 compatible = "fixed-factor-clock";
385 clocks = <&core_ck>;
386 clock-mult = <1>;
387 clock-div = <6>;
388 };
389
390 dummy_ck: dummy_ck {
391 #clock-cells = <0>;
392 compatible = "fixed-clock";
393 clock-frequency = <0>;
394 };
395
396 core_d8_ck: core_d8_ck {
397 #clock-cells = <0>;
398 compatible = "fixed-factor-clock";
399 clocks = <&core_ck>;
400 clock-mult = <1>;
401 clock-div = <8>;
402 };
403
404 core_d9_ck: core_d9_ck {
405 #clock-cells = <0>;
406 compatible = "fixed-factor-clock";
407 clocks = <&core_ck>;
408 clock-mult = <1>;
409 clock-div = <9>;
410 };
411
412 core_d12_ck: core_d12_ck {
413 #clock-cells = <0>;
414 compatible = "fixed-factor-clock";
415 clocks = <&core_ck>;
416 clock-mult = <1>;
417 clock-div = <12>;
418 };
419
420 core_d16_ck: core_d16_ck {
421 #clock-cells = <0>;
422 compatible = "fixed-factor-clock";
423 clocks = <&core_ck>;
424 clock-mult = <1>;
425 clock-div = <16>;
426 };
427
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]428 dss1_mux_fck: dss1_mux_fck@240 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]429 #clock-cells = <0>;
430 compatible = "ti,composite-mux-clock";
431 clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
432 ti,bit-shift = <8>;
433 reg = <0x0240>;
434 };
435
436 dss1_fck: dss1_fck {
437 #clock-cells = <0>;
438 compatible = "ti,composite-clock";
439 clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
440 };
441
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]442 dss2_gate_fck: dss2_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]443 #clock-cells = <0>;
444 compatible = "ti,composite-no-wait-gate-clock";
445 clocks = <&func_48m_ck>;
446 ti,bit-shift = <1>;
447 reg = <0x0200>;
448 };
449
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]450 dss2_mux_fck: dss2_mux_fck@240 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]451 #clock-cells = <0>;
452 compatible = "ti,composite-mux-clock";
453 clocks = <&sys_ck>, <&func_48m_ck>;
454 ti,bit-shift = <13>;
455 reg = <0x0240>;
456 };
457
458 dss2_fck: dss2_fck {
459 #clock-cells = <0>;
460 compatible = "ti,composite-clock";
461 clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
462 };
463
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]464 dss_54m_fck: dss_54m_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]465 #clock-cells = <0>;
466 compatible = "ti,wait-gate-clock";
467 clocks = <&func_54m_ck>;
468 ti,bit-shift = <2>;
469 reg = <0x0200>;
470 };
471
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]472 ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]473 #clock-cells = <0>;
474 compatible = "ti,composite-gate-clock";
475 clocks = <&core_ck>;
476 ti,bit-shift = <1>;
477 reg = <0x0204>;
478 };
479
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]480 ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]481 #clock-cells = <0>;
482 compatible = "ti,composite-divider-clock";
483 clocks = <&core_ck>;
484 ti,bit-shift = <20>;
485 reg = <0x0240>;
486 };
487
488 ssi_ssr_sst_fck: ssi_ssr_sst_fck {
489 #clock-cells = <0>;
490 compatible = "ti,composite-clock";
491 clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
492 };
493
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]494 usb_l4_gate_ick: usb_l4_gate_ick@214 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]495 #clock-cells = <0>;
496 compatible = "ti,composite-interface-clock";
497 clocks = <&core_l3_ck>;
498 ti,bit-shift = <0>;
499 reg = <0x0214>;
500 };
501
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]502 usb_l4_div_ick: usb_l4_div_ick@240 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]503 #clock-cells = <0>;
504 compatible = "ti,composite-divider-clock";
505 clocks = <&core_l3_ck>;
506 ti,bit-shift = <25>;
507 reg = <0x0240>;
508 ti,dividers = <0>, <1>, <2>, <0>, <4>;
509 };
510
511 usb_l4_ick: usb_l4_ick {
512 #clock-cells = <0>;
513 compatible = "ti,composite-clock";
514 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
515 };
516
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]517 ssi_l4_ick: ssi_l4_ick@214 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]518 #clock-cells = <0>;
519 compatible = "ti,omap3-interface-clock";
520 clocks = <&l4_ck>;
521 ti,bit-shift = <1>;
522 reg = <0x0214>;
523 };
524
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]525 gpt1_ick: gpt1_ick@410 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]526 #clock-cells = <0>;
527 compatible = "ti,omap3-interface-clock";
528 clocks = <&sys_ck>;
529 ti,bit-shift = <0>;
530 reg = <0x0410>;
531 };
532
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]533 gpt1_gate_fck: gpt1_gate_fck@400 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]534 #clock-cells = <0>;
535 compatible = "ti,composite-gate-clock";
536 clocks = <&func_32k_ck>;
537 ti,bit-shift = <0>;
538 reg = <0x0400>;
539 };
540
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]541 gpt1_mux_fck: gpt1_mux_fck@440 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]542 #clock-cells = <0>;
543 compatible = "ti,composite-mux-clock";
544 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
545 reg = <0x0440>;
546 };
547
548 gpt1_fck: gpt1_fck {
549 #clock-cells = <0>;
550 compatible = "ti,composite-clock";
551 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
552 };
553
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]554 gpt2_ick: gpt2_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]555 #clock-cells = <0>;
556 compatible = "ti,omap3-interface-clock";
557 clocks = <&l4_ck>;
558 ti,bit-shift = <4>;
559 reg = <0x0210>;
560 };
561
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]562 gpt2_gate_fck: gpt2_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]563 #clock-cells = <0>;
564 compatible = "ti,composite-gate-clock";
565 clocks = <&func_32k_ck>;
566 ti,bit-shift = <4>;
567 reg = <0x0200>;
568 };
569
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]570 gpt2_mux_fck: gpt2_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]571 #clock-cells = <0>;
572 compatible = "ti,composite-mux-clock";
573 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
574 ti,bit-shift = <2>;
575 reg = <0x0244>;
576 };
577
578 gpt2_fck: gpt2_fck {
579 #clock-cells = <0>;
580 compatible = "ti,composite-clock";
581 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
582 };
583
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]584 gpt3_ick: gpt3_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]585 #clock-cells = <0>;
586 compatible = "ti,omap3-interface-clock";
587 clocks = <&l4_ck>;
588 ti,bit-shift = <5>;
589 reg = <0x0210>;
590 };
591
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]592 gpt3_gate_fck: gpt3_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]593 #clock-cells = <0>;
594 compatible = "ti,composite-gate-clock";
595 clocks = <&func_32k_ck>;
596 ti,bit-shift = <5>;
597 reg = <0x0200>;
598 };
599
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]600 gpt3_mux_fck: gpt3_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]601 #clock-cells = <0>;
602 compatible = "ti,composite-mux-clock";
603 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
604 ti,bit-shift = <4>;
605 reg = <0x0244>;
606 };
607
608 gpt3_fck: gpt3_fck {
609 #clock-cells = <0>;
610 compatible = "ti,composite-clock";
611 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
612 };
613
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]614 gpt4_ick: gpt4_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]615 #clock-cells = <0>;
616 compatible = "ti,omap3-interface-clock";
617 clocks = <&l4_ck>;
618 ti,bit-shift = <6>;
619 reg = <0x0210>;
620 };
621
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]622 gpt4_gate_fck: gpt4_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]623 #clock-cells = <0>;
624 compatible = "ti,composite-gate-clock";
625 clocks = <&func_32k_ck>;
626 ti,bit-shift = <6>;
627 reg = <0x0200>;
628 };
629
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]630 gpt4_mux_fck: gpt4_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]631 #clock-cells = <0>;
632 compatible = "ti,composite-mux-clock";
633 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
634 ti,bit-shift = <6>;
635 reg = <0x0244>;
636 };
637
638 gpt4_fck: gpt4_fck {
639 #clock-cells = <0>;
640 compatible = "ti,composite-clock";
641 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
642 };
643
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]644 gpt5_ick: gpt5_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]645 #clock-cells = <0>;
646 compatible = "ti,omap3-interface-clock";
647 clocks = <&l4_ck>;
648 ti,bit-shift = <7>;
649 reg = <0x0210>;
650 };
651
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]652 gpt5_gate_fck: gpt5_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]653 #clock-cells = <0>;
654 compatible = "ti,composite-gate-clock";
655 clocks = <&func_32k_ck>;
656 ti,bit-shift = <7>;
657 reg = <0x0200>;
658 };
659
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]660 gpt5_mux_fck: gpt5_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]661 #clock-cells = <0>;
662 compatible = "ti,composite-mux-clock";
663 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
664 ti,bit-shift = <8>;
665 reg = <0x0244>;
666 };
667
668 gpt5_fck: gpt5_fck {
669 #clock-cells = <0>;
670 compatible = "ti,composite-clock";
671 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
672 };
673
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]674 gpt6_ick: gpt6_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]675 #clock-cells = <0>;
676 compatible = "ti,omap3-interface-clock";
677 clocks = <&l4_ck>;
678 ti,bit-shift = <8>;
679 reg = <0x0210>;
680 };
681
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]682 gpt6_gate_fck: gpt6_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]683 #clock-cells = <0>;
684 compatible = "ti,composite-gate-clock";
685 clocks = <&func_32k_ck>;
686 ti,bit-shift = <8>;
687 reg = <0x0200>;
688 };
689
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]690 gpt6_mux_fck: gpt6_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]691 #clock-cells = <0>;
692 compatible = "ti,composite-mux-clock";
693 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
694 ti,bit-shift = <10>;
695 reg = <0x0244>;
696 };
697
698 gpt6_fck: gpt6_fck {
699 #clock-cells = <0>;
700 compatible = "ti,composite-clock";
701 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
702 };
703
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]704 gpt7_ick: gpt7_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]705 #clock-cells = <0>;
706 compatible = "ti,omap3-interface-clock";
707 clocks = <&l4_ck>;
708 ti,bit-shift = <9>;
709 reg = <0x0210>;
710 };
711
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]712 gpt7_gate_fck: gpt7_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]713 #clock-cells = <0>;
714 compatible = "ti,composite-gate-clock";
715 clocks = <&func_32k_ck>;
716 ti,bit-shift = <9>;
717 reg = <0x0200>;
718 };
719
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]720 gpt7_mux_fck: gpt7_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]721 #clock-cells = <0>;
722 compatible = "ti,composite-mux-clock";
723 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
724 ti,bit-shift = <12>;
725 reg = <0x0244>;
726 };
727
728 gpt7_fck: gpt7_fck {
729 #clock-cells = <0>;
730 compatible = "ti,composite-clock";
731 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
732 };
733
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]734 gpt8_ick: gpt8_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]735 #clock-cells = <0>;
736 compatible = "ti,omap3-interface-clock";
737 clocks = <&l4_ck>;
738 ti,bit-shift = <10>;
739 reg = <0x0210>;
740 };
741
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]742 gpt8_gate_fck: gpt8_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]743 #clock-cells = <0>;
744 compatible = "ti,composite-gate-clock";
745 clocks = <&func_32k_ck>;
746 ti,bit-shift = <10>;
747 reg = <0x0200>;
748 };
749
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]750 gpt8_mux_fck: gpt8_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]751 #clock-cells = <0>;
752 compatible = "ti,composite-mux-clock";
753 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
754 ti,bit-shift = <14>;
755 reg = <0x0244>;
756 };
757
758 gpt8_fck: gpt8_fck {
759 #clock-cells = <0>;
760 compatible = "ti,composite-clock";
761 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
762 };
763
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]764 gpt9_ick: gpt9_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]765 #clock-cells = <0>;
766 compatible = "ti,omap3-interface-clock";
767 clocks = <&l4_ck>;
768 ti,bit-shift = <11>;
769 reg = <0x0210>;
770 };
771
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]772 gpt9_gate_fck: gpt9_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]773 #clock-cells = <0>;
774 compatible = "ti,composite-gate-clock";
775 clocks = <&func_32k_ck>;
776 ti,bit-shift = <11>;
777 reg = <0x0200>;
778 };
779
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]780 gpt9_mux_fck: gpt9_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]781 #clock-cells = <0>;
782 compatible = "ti,composite-mux-clock";
783 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
784 ti,bit-shift = <16>;
785 reg = <0x0244>;
786 };
787
788 gpt9_fck: gpt9_fck {
789 #clock-cells = <0>;
790 compatible = "ti,composite-clock";
791 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
792 };
793
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]794 gpt10_ick: gpt10_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]795 #clock-cells = <0>;
796 compatible = "ti,omap3-interface-clock";
797 clocks = <&l4_ck>;
798 ti,bit-shift = <12>;
799 reg = <0x0210>;
800 };
801
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]802 gpt10_gate_fck: gpt10_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]803 #clock-cells = <0>;
804 compatible = "ti,composite-gate-clock";
805 clocks = <&func_32k_ck>;
806 ti,bit-shift = <12>;
807 reg = <0x0200>;
808 };
809
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]810 gpt10_mux_fck: gpt10_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]811 #clock-cells = <0>;
812 compatible = "ti,composite-mux-clock";
813 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
814 ti,bit-shift = <18>;
815 reg = <0x0244>;
816 };
817
818 gpt10_fck: gpt10_fck {
819 #clock-cells = <0>;
820 compatible = "ti,composite-clock";
821 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
822 };
823
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]824 gpt11_ick: gpt11_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]825 #clock-cells = <0>;
826 compatible = "ti,omap3-interface-clock";
827 clocks = <&l4_ck>;
828 ti,bit-shift = <13>;
829 reg = <0x0210>;
830 };
831
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]832 gpt11_gate_fck: gpt11_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]833 #clock-cells = <0>;
834 compatible = "ti,composite-gate-clock";
835 clocks = <&func_32k_ck>;
836 ti,bit-shift = <13>;
837 reg = <0x0200>;
838 };
839
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]840 gpt11_mux_fck: gpt11_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]841 #clock-cells = <0>;
842 compatible = "ti,composite-mux-clock";
843 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
844 ti,bit-shift = <20>;
845 reg = <0x0244>;
846 };
847
848 gpt11_fck: gpt11_fck {
849 #clock-cells = <0>;
850 compatible = "ti,composite-clock";
851 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
852 };
853
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]854 gpt12_ick: gpt12_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]855 #clock-cells = <0>;
856 compatible = "ti,omap3-interface-clock";
857 clocks = <&l4_ck>;
858 ti,bit-shift = <14>;
859 reg = <0x0210>;
860 };
861
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]862 gpt12_gate_fck: gpt12_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]863 #clock-cells = <0>;
864 compatible = "ti,composite-gate-clock";
865 clocks = <&func_32k_ck>;
866 ti,bit-shift = <14>;
867 reg = <0x0200>;
868 };
869
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]870 gpt12_mux_fck: gpt12_mux_fck@244 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]871 #clock-cells = <0>;
872 compatible = "ti,composite-mux-clock";
873 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
874 ti,bit-shift = <22>;
875 reg = <0x0244>;
876 };
877
878 gpt12_fck: gpt12_fck {
879 #clock-cells = <0>;
880 compatible = "ti,composite-clock";
881 clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
882 };
883
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]884 mcbsp1_ick: mcbsp1_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]885 #clock-cells = <0>;
886 compatible = "ti,omap3-interface-clock";
887 clocks = <&l4_ck>;
888 ti,bit-shift = <15>;
889 reg = <0x0210>;
890 };
891
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]892 mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]893 #clock-cells = <0>;
894 compatible = "ti,composite-gate-clock";
895 clocks = <&mcbsp_clks>;
896 ti,bit-shift = <15>;
897 reg = <0x0200>;
898 };
899
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]900 mcbsp2_ick: mcbsp2_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]901 #clock-cells = <0>;
902 compatible = "ti,omap3-interface-clock";
903 clocks = <&l4_ck>;
904 ti,bit-shift = <16>;
905 reg = <0x0210>;
906 };
907
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]908 mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]909 #clock-cells = <0>;
910 compatible = "ti,composite-gate-clock";
911 clocks = <&mcbsp_clks>;
912 ti,bit-shift = <16>;
913 reg = <0x0200>;
914 };
915
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]916 mcspi1_ick: mcspi1_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]917 #clock-cells = <0>;
918 compatible = "ti,omap3-interface-clock";
919 clocks = <&l4_ck>;
920 ti,bit-shift = <17>;
921 reg = <0x0210>;
922 };
923
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]924 mcspi1_fck: mcspi1_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]925 #clock-cells = <0>;
926 compatible = "ti,wait-gate-clock";
927 clocks = <&func_48m_ck>;
928 ti,bit-shift = <17>;
929 reg = <0x0200>;
930 };
931
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]932 mcspi2_ick: mcspi2_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]933 #clock-cells = <0>;
934 compatible = "ti,omap3-interface-clock";
935 clocks = <&l4_ck>;
936 ti,bit-shift = <18>;
937 reg = <0x0210>;
938 };
939
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]940 mcspi2_fck: mcspi2_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]941 #clock-cells = <0>;
942 compatible = "ti,wait-gate-clock";
943 clocks = <&func_48m_ck>;
944 ti,bit-shift = <18>;
945 reg = <0x0200>;
946 };
947
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]948 uart1_ick: uart1_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]949 #clock-cells = <0>;
950 compatible = "ti,omap3-interface-clock";
951 clocks = <&l4_ck>;
952 ti,bit-shift = <21>;
953 reg = <0x0210>;
954 };
955
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]956 uart1_fck: uart1_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]957 #clock-cells = <0>;
958 compatible = "ti,wait-gate-clock";
959 clocks = <&func_48m_ck>;
960 ti,bit-shift = <21>;
961 reg = <0x0200>;
962 };
963
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]964 uart2_ick: uart2_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]965 #clock-cells = <0>;
966 compatible = "ti,omap3-interface-clock";
967 clocks = <&l4_ck>;
968 ti,bit-shift = <22>;
969 reg = <0x0210>;
970 };
971
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]972 uart2_fck: uart2_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]973 #clock-cells = <0>;
974 compatible = "ti,wait-gate-clock";
975 clocks = <&func_48m_ck>;
976 ti,bit-shift = <22>;
977 reg = <0x0200>;
978 };
979
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]980 uart3_ick: uart3_ick@214 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]981 #clock-cells = <0>;
982 compatible = "ti,omap3-interface-clock";
983 clocks = <&l4_ck>;
984 ti,bit-shift = <2>;
985 reg = <0x0214>;
986 };
987
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]988 uart3_fck: uart3_fck@204 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]989 #clock-cells = <0>;
990 compatible = "ti,wait-gate-clock";
991 clocks = <&func_48m_ck>;
992 ti,bit-shift = <2>;
993 reg = <0x0204>;
994 };
995
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]996 gpios_ick: gpios_ick@410 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]997 #clock-cells = <0>;
998 compatible = "ti,omap3-interface-clock";
999 clocks = <&sys_ck>;
1000 ti,bit-shift = <2>;
1001 reg = <0x0410>;
1002 };
1003
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1004 gpios_fck: gpios_fck@400 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1005 #clock-cells = <0>;
1006 compatible = "ti,wait-gate-clock";
1007 clocks = <&func_32k_ck>;
1008 ti,bit-shift = <2>;
1009 reg = <0x0400>;
1010 };
1011
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1012 mpu_wdt_ick: mpu_wdt_ick@410 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1013 #clock-cells = <0>;
1014 compatible = "ti,omap3-interface-clock";
1015 clocks = <&sys_ck>;
1016 ti,bit-shift = <3>;
1017 reg = <0x0410>;
1018 };
1019
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1020 mpu_wdt_fck: mpu_wdt_fck@400 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1021 #clock-cells = <0>;
1022 compatible = "ti,wait-gate-clock";
1023 clocks = <&func_32k_ck>;
1024 ti,bit-shift = <3>;
1025 reg = <0x0400>;
1026 };
1027
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1028 sync_32k_ick: sync_32k_ick@410 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1029 #clock-cells = <0>;
1030 compatible = "ti,omap3-interface-clock";
1031 clocks = <&sys_ck>;
1032 ti,bit-shift = <1>;
1033 reg = <0x0410>;
1034 };
1035
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1036 wdt1_ick: wdt1_ick@410 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1037 #clock-cells = <0>;
1038 compatible = "ti,omap3-interface-clock";
1039 clocks = <&sys_ck>;
1040 ti,bit-shift = <4>;
1041 reg = <0x0410>;
1042 };
1043
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1044 omapctrl_ick: omapctrl_ick@410 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1045 #clock-cells = <0>;
1046 compatible = "ti,omap3-interface-clock";
1047 clocks = <&sys_ck>;
1048 ti,bit-shift = <5>;
1049 reg = <0x0410>;
1050 };
1051
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1052 cam_fck: cam_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1053 #clock-cells = <0>;
1054 compatible = "ti,gate-clock";
1055 clocks = <&func_96m_ck>;
1056 ti,bit-shift = <31>;
1057 reg = <0x0200>;
1058 };
1059
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1060 cam_ick: cam_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1061 #clock-cells = <0>;
1062 compatible = "ti,omap3-no-wait-interface-clock";
1063 clocks = <&l4_ck>;
1064 ti,bit-shift = <31>;
1065 reg = <0x0210>;
1066 };
1067
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1068 mailboxes_ick: mailboxes_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1069 #clock-cells = <0>;
1070 compatible = "ti,omap3-interface-clock";
1071 clocks = <&l4_ck>;
1072 ti,bit-shift = <30>;
1073 reg = <0x0210>;
1074 };
1075
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1076 wdt4_ick: wdt4_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1077 #clock-cells = <0>;
1078 compatible = "ti,omap3-interface-clock";
1079 clocks = <&l4_ck>;
1080 ti,bit-shift = <29>;
1081 reg = <0x0210>;
1082 };
1083
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1084 wdt4_fck: wdt4_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1085 #clock-cells = <0>;
1086 compatible = "ti,wait-gate-clock";
1087 clocks = <&func_32k_ck>;
1088 ti,bit-shift = <29>;
1089 reg = <0x0200>;
1090 };
1091
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1092 mspro_ick: mspro_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1093 #clock-cells = <0>;
1094 compatible = "ti,omap3-interface-clock";
1095 clocks = <&l4_ck>;
1096 ti,bit-shift = <27>;
1097 reg = <0x0210>;
1098 };
1099
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1100 mspro_fck: mspro_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1101 #clock-cells = <0>;
1102 compatible = "ti,wait-gate-clock";
1103 clocks = <&func_96m_ck>;
1104 ti,bit-shift = <27>;
1105 reg = <0x0200>;
1106 };
1107
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1108 fac_ick: fac_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1109 #clock-cells = <0>;
1110 compatible = "ti,omap3-interface-clock";
1111 clocks = <&l4_ck>;
1112 ti,bit-shift = <25>;
1113 reg = <0x0210>;
1114 };
1115
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1116 fac_fck: fac_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1117 #clock-cells = <0>;
1118 compatible = "ti,wait-gate-clock";
1119 clocks = <&func_12m_ck>;
1120 ti,bit-shift = <25>;
1121 reg = <0x0200>;
1122 };
1123
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1124 hdq_ick: hdq_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1125 #clock-cells = <0>;
1126 compatible = "ti,omap3-interface-clock";
1127 clocks = <&l4_ck>;
1128 ti,bit-shift = <23>;
1129 reg = <0x0210>;
1130 };
1131
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1132 hdq_fck: hdq_fck@200 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1133 #clock-cells = <0>;
1134 compatible = "ti,wait-gate-clock";
1135 clocks = <&func_12m_ck>;
1136 ti,bit-shift = <23>;
1137 reg = <0x0200>;
1138 };
1139
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1140 i2c1_ick: i2c1_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1141 #clock-cells = <0>;
1142 compatible = "ti,omap3-interface-clock";
1143 clocks = <&l4_ck>;
1144 ti,bit-shift = <19>;
1145 reg = <0x0210>;
1146 };
1147
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1148 i2c2_ick: i2c2_ick@210 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1149 #clock-cells = <0>;
1150 compatible = "ti,omap3-interface-clock";
1151 clocks = <&l4_ck>;
1152 ti,bit-shift = <20>;
1153 reg = <0x0210>;
1154 };
1155
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1156 gpmc_fck: gpmc_fck@238 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1157 #clock-cells = <0>;
1158 compatible = "ti,fixed-factor-clock";
1159 clocks = <&core_l3_ck>;
1160 ti,clock-div = <1>;
1161 ti,autoidle-shift = <1>;
1162 reg = <0x0238>;
1163 ti,clock-mult = <1>;
1164 };
1165
1166 sdma_fck: sdma_fck {
1167 #clock-cells = <0>;
1168 compatible = "fixed-factor-clock";
1169 clocks = <&core_l3_ck>;
1170 clock-mult = <1>;
1171 clock-div = <1>;
1172 };
1173
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1174 sdma_ick: sdma_ick@238 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1175 #clock-cells = <0>;
1176 compatible = "ti,fixed-factor-clock";
1177 clocks = <&core_l3_ck>;
1178 ti,clock-div = <1>;
1179 ti,autoidle-shift = <0>;
1180 reg = <0x0238>;
1181 ti,clock-mult = <1>;
1182 };
1183
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1184 sdrc_ick: sdrc_ick@238 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1185 #clock-cells = <0>;
1186 compatible = "ti,fixed-factor-clock";
1187 clocks = <&core_l3_ck>;
1188 ti,clock-div = <1>;
1189 ti,autoidle-shift = <2>;
1190 reg = <0x0238>;
1191 ti,clock-mult = <1>;
1192 };
1193
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1194 des_ick: des_ick@21c {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1195 #clock-cells = <0>;
1196 compatible = "ti,omap3-interface-clock";
1197 clocks = <&l4_ck>;
1198 ti,bit-shift = <0>;
1199 reg = <0x021c>;
1200 };
1201
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1202 sha_ick: sha_ick@21c {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1203 #clock-cells = <0>;
1204 compatible = "ti,omap3-interface-clock";
1205 clocks = <&l4_ck>;
1206 ti,bit-shift = <1>;
1207 reg = <0x021c>;
1208 };
1209
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1210 rng_ick: rng_ick@21c {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1211 #clock-cells = <0>;
1212 compatible = "ti,omap3-interface-clock";
1213 clocks = <&l4_ck>;
1214 ti,bit-shift = <2>;
1215 reg = <0x021c>;
1216 };
1217
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1218 aes_ick: aes_ick@21c {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1219 #clock-cells = <0>;
1220 compatible = "ti,omap3-interface-clock";
1221 clocks = <&l4_ck>;
1222 ti,bit-shift = <3>;
1223 reg = <0x021c>;
1224 };
1225
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1226 pka_ick: pka_ick@21c {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1227 #clock-cells = <0>;
1228 compatible = "ti,omap3-interface-clock";
1229 clocks = <&l4_ck>;
1230 ti,bit-shift = <4>;
1231 reg = <0x021c>;
1232 };
1233
Tero Kristo1bb5fcb2016-04-04 18:16:07 +0300[diff] [blame]1234 usb_fck: usb_fck@204 {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]1235 #clock-cells = <0>;
1236 compatible = "ti,wait-gate-clock";
1237 clocks = <&func_48m_ck>;
1238 ti,bit-shift = <0>;
1239 reg = <0x0204>;
1240 };
1241};