H. Peter Anvin | 2decb19 | 2010-07-19 18:32:04 -0700 | [diff] [blame] | 1 | /* |
Maxime Jayat | 3f79410 | 2013-10-12 01:29:46 +0200 | [diff] [blame] | 2 | * Routines to identify additional cpu features that are scattered in |
H. Peter Anvin | 2decb19 | 2010-07-19 18:32:04 -0700 | [diff] [blame] | 3 | * cpuid space. |
| 4 | */ |
| 5 | #include <linux/cpu.h> |
| 6 | |
| 7 | #include <asm/pat.h> |
| 8 | #include <asm/processor.h> |
| 9 | |
| 10 | #include <asm/apic.h> |
| 11 | |
| 12 | struct cpuid_bit { |
| 13 | u16 feature; |
| 14 | u8 reg; |
| 15 | u8 bit; |
| 16 | u32 level; |
| 17 | u32 sub_leaf; |
| 18 | }; |
| 19 | |
| 20 | enum cpuid_regs { |
| 21 | CR_EAX = 0, |
| 22 | CR_ECX, |
| 23 | CR_EDX, |
| 24 | CR_EBX |
| 25 | }; |
| 26 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 27 | void init_scattered_cpuid_features(struct cpuinfo_x86 *c) |
H. Peter Anvin | 2decb19 | 2010-07-19 18:32:04 -0700 | [diff] [blame] | 28 | { |
| 29 | u32 max_level; |
| 30 | u32 regs[4]; |
| 31 | const struct cpuid_bit *cb; |
| 32 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 33 | static const struct cpuid_bit cpuid_bits[] = { |
Alexander Shishkin | ed69628 | 2015-01-14 14:18:19 +0200 | [diff] [blame] | 34 | { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 }, |
Piotr Luc | 8214899 | 2016-10-18 17:01:11 +0200 | [diff] [blame] | 35 | { X86_FEATURE_AVX512_4VNNIW, CR_EDX, 2, 0x00000007, 0 }, |
| 36 | { X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 }, |
H. Peter Anvin | 2decb19 | 2010-07-19 18:32:04 -0700 | [diff] [blame] | 37 | { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, |
| 38 | { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, |
Fenghua Yu | 4ab15864 | 2016-10-22 06:19:51 -0700 | [diff] [blame] | 39 | { X86_FEATURE_CAT_L3, CR_EBX, 1, 0x00000010, 0 }, |
| 40 | { X86_FEATURE_CAT_L2, CR_EBX, 2, 0x00000010, 0 }, |
| 41 | { X86_FEATURE_CDP_L3, CR_ECX, 2, 0x00000010, 1 }, |
Thomas Renninger | 2f1e097 | 2012-01-26 00:09:11 +0100 | [diff] [blame] | 42 | { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, |
Jacob Shin | 9c5320c | 2013-04-04 16:19:04 +0000 | [diff] [blame] | 43 | { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, |
| 44 | { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, |
H. Peter Anvin | 2decb19 | 2010-07-19 18:32:04 -0700 | [diff] [blame] | 45 | { 0, 0, 0, 0, 0 } |
| 46 | }; |
| 47 | |
| 48 | for (cb = cpuid_bits; cb->feature; cb++) { |
| 49 | |
| 50 | /* Verify that the level is valid */ |
| 51 | max_level = cpuid_eax(cb->level & 0xffff0000); |
| 52 | if (max_level < cb->level || |
| 53 | max_level > (cb->level | 0xffff)) |
| 54 | continue; |
| 55 | |
| 56 | cpuid_count(cb->level, cb->sub_leaf, ®s[CR_EAX], |
| 57 | ®s[CR_EBX], ®s[CR_ECX], ®s[CR_EDX]); |
| 58 | |
| 59 | if (regs[cb->reg] & (1 << cb->bit)) |
| 60 | set_cpu_cap(c, cb->feature); |
| 61 | } |
| 62 | } |