Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 1 | |
Christoph Hellwig | d824e66 | 2006-04-10 22:54:04 -0700 | [diff] [blame] | 2 | #include <linux/irq.h> |
Yinghai Lu | 57b150c | 2009-04-27 17:59:53 -0700 | [diff] [blame] | 3 | #include <linux/interrupt.h> |
| 4 | |
| 5 | #include "internals.h" |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 6 | |
Thomas Gleixner | cdd1636 | 2017-06-20 01:37:19 +0200 | [diff] [blame] | 7 | /** |
| 8 | * irq_fixup_move_pending - Cleanup irq move pending from a dying CPU |
| 9 | * @desc: Interrupt descpriptor to clean up |
| 10 | * @force_clear: If set clear the move pending bit unconditionally. |
| 11 | * If not set, clear it only when the dying CPU is the |
| 12 | * last one in the pending mask. |
| 13 | * |
| 14 | * Returns true if the pending bit was set and the pending mask contains an |
| 15 | * online CPU other than the dying CPU. |
| 16 | */ |
| 17 | bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear) |
| 18 | { |
| 19 | struct irq_data *data = irq_desc_get_irq_data(desc); |
| 20 | |
| 21 | if (!irqd_is_setaffinity_pending(data)) |
| 22 | return false; |
| 23 | |
| 24 | /* |
| 25 | * The outgoing CPU might be the last online target in a pending |
| 26 | * interrupt move. If that's the case clear the pending move bit. |
| 27 | */ |
| 28 | if (cpumask_any_and(desc->pending_mask, cpu_online_mask) >= nr_cpu_ids) { |
| 29 | irqd_clr_move_pending(data); |
| 30 | return false; |
| 31 | } |
| 32 | if (force_clear) |
| 33 | irqd_clr_move_pending(data); |
| 34 | return true; |
| 35 | } |
| 36 | |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 37 | void irq_move_masked_irq(struct irq_data *idata) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 38 | { |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 39 | struct irq_desc *desc = irq_data_to_desc(idata); |
Jiang Liu | 77ed42f | 2015-06-01 16:05:11 +0800 | [diff] [blame] | 40 | struct irq_chip *chip = desc->irq_data.chip; |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 41 | |
Thomas Gleixner | f230b6d | 2011-02-05 15:20:04 +0100 | [diff] [blame] | 42 | if (likely(!irqd_is_setaffinity_pending(&desc->irq_data))) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 43 | return; |
| 44 | |
Thomas Gleixner | a614a610a | 2015-06-20 12:05:40 +0200 | [diff] [blame] | 45 | irqd_clr_move_pending(&desc->irq_data); |
| 46 | |
Bryan Holty | 501f249 | 2006-03-25 03:07:37 -0800 | [diff] [blame] | 47 | /* |
| 48 | * Paranoia: cpu-local interrupts shouldn't be calling in here anyway. |
| 49 | */ |
Thomas Gleixner | a614a610a | 2015-06-20 12:05:40 +0200 | [diff] [blame] | 50 | if (irqd_is_per_cpu(&desc->irq_data)) { |
Bryan Holty | 501f249 | 2006-03-25 03:07:37 -0800 | [diff] [blame] | 51 | WARN_ON(1); |
| 52 | return; |
| 53 | } |
| 54 | |
Mike Travis | 7f7ace0 | 2009-01-10 21:58:08 -0800 | [diff] [blame] | 55 | if (unlikely(cpumask_empty(desc->pending_mask))) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 56 | return; |
| 57 | |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 58 | if (!chip->irq_set_affinity) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 59 | return; |
| 60 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 61 | assert_raw_spin_locked(&desc->lock); |
Bryan Holty | 501f249 | 2006-03-25 03:07:37 -0800 | [diff] [blame] | 62 | |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 63 | /* |
| 64 | * If there was a valid mask to work with, please |
| 65 | * do the disable, re-program, enable sequence. |
| 66 | * This is *not* particularly important for level triggered |
| 67 | * but in a edge trigger case, we might be setting rte |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 68 | * when an active trigger is coming in. This could |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 69 | * cause some ioapics to mal-function. |
| 70 | * Being paranoid i guess! |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 71 | * |
| 72 | * For correct operation this depends on the caller |
| 73 | * masking the irqs. |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 74 | */ |
Jiang Liu | 818b0f3 | 2012-03-30 23:11:34 +0800 | [diff] [blame] | 75 | if (cpumask_any_and(desc->pending_mask, cpu_online_mask) < nr_cpu_ids) |
| 76 | irq_do_set_affinity(&desc->irq_data, desc->pending_mask, false); |
Yinghai Lu | 57b150c | 2009-04-27 17:59:53 -0700 | [diff] [blame] | 77 | |
Mike Travis | 7f7ace0 | 2009-01-10 21:58:08 -0800 | [diff] [blame] | 78 | cpumask_clear(desc->pending_mask); |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 79 | } |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 80 | |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 81 | void irq_move_irq(struct irq_data *idata) |
| 82 | { |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 83 | bool masked; |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 84 | |
Jiang Liu | 77ed42f | 2015-06-01 16:05:11 +0800 | [diff] [blame] | 85 | /* |
| 86 | * Get top level irq_data when CONFIG_IRQ_DOMAIN_HIERARCHY is enabled, |
| 87 | * and it should be optimized away when CONFIG_IRQ_DOMAIN_HIERARCHY is |
| 88 | * disabled. So we avoid an "#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY" here. |
| 89 | */ |
| 90 | idata = irq_desc_get_irq_data(irq_data_to_desc(idata)); |
| 91 | |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 92 | if (likely(!irqd_is_setaffinity_pending(idata))) |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 93 | return; |
| 94 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 95 | if (unlikely(irqd_irq_disabled(idata))) |
Eric W. Biederman | 2a786b4 | 2007-02-23 04:46:20 -0700 | [diff] [blame] | 96 | return; |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 97 | |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 98 | /* |
| 99 | * Be careful vs. already masked interrupts. If this is a |
| 100 | * threaded interrupt with ONESHOT set, we can end up with an |
| 101 | * interrupt storm. |
| 102 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 103 | masked = irqd_irq_masked(idata); |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 104 | if (!masked) |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 105 | idata->chip->irq_mask(idata); |
| 106 | irq_move_masked_irq(idata); |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 107 | if (!masked) |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 108 | idata->chip->irq_unmask(idata); |
| 109 | } |