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Andrew Mortonc777ac52006-03-25 03:07:36 -08001
Christoph Hellwigd824e662006-04-10 22:54:04 -07002#include <linux/irq.h>
Yinghai Lu57b150c2009-04-27 17:59:53 -07003#include <linux/interrupt.h>
4
5#include "internals.h"
Andrew Mortonc777ac52006-03-25 03:07:36 -08006
Thomas Gleixnercdd16362017-06-20 01:37:19 +02007/**
8 * irq_fixup_move_pending - Cleanup irq move pending from a dying CPU
9 * @desc: Interrupt descpriptor to clean up
10 * @force_clear: If set clear the move pending bit unconditionally.
11 * If not set, clear it only when the dying CPU is the
12 * last one in the pending mask.
13 *
14 * Returns true if the pending bit was set and the pending mask contains an
15 * online CPU other than the dying CPU.
16 */
17bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear)
18{
19 struct irq_data *data = irq_desc_get_irq_data(desc);
20
21 if (!irqd_is_setaffinity_pending(data))
22 return false;
23
24 /*
25 * The outgoing CPU might be the last online target in a pending
26 * interrupt move. If that's the case clear the pending move bit.
27 */
28 if (cpumask_any_and(desc->pending_mask, cpu_online_mask) >= nr_cpu_ids) {
29 irqd_clr_move_pending(data);
30 return false;
31 }
32 if (force_clear)
33 irqd_clr_move_pending(data);
34 return true;
35}
36
Thomas Gleixnera4395202011-02-04 18:46:16 +010037void irq_move_masked_irq(struct irq_data *idata)
Andrew Mortonc777ac52006-03-25 03:07:36 -080038{
Thomas Gleixnera4395202011-02-04 18:46:16 +010039 struct irq_desc *desc = irq_data_to_desc(idata);
Jiang Liu77ed42f2015-06-01 16:05:11 +080040 struct irq_chip *chip = desc->irq_data.chip;
Andrew Mortonc777ac52006-03-25 03:07:36 -080041
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +010042 if (likely(!irqd_is_setaffinity_pending(&desc->irq_data)))
Andrew Mortonc777ac52006-03-25 03:07:36 -080043 return;
44
Thomas Gleixnera614a610a2015-06-20 12:05:40 +020045 irqd_clr_move_pending(&desc->irq_data);
46
Bryan Holty501f2492006-03-25 03:07:37 -080047 /*
48 * Paranoia: cpu-local interrupts shouldn't be calling in here anyway.
49 */
Thomas Gleixnera614a610a2015-06-20 12:05:40 +020050 if (irqd_is_per_cpu(&desc->irq_data)) {
Bryan Holty501f2492006-03-25 03:07:37 -080051 WARN_ON(1);
52 return;
53 }
54
Mike Travis7f7ace02009-01-10 21:58:08 -080055 if (unlikely(cpumask_empty(desc->pending_mask)))
Andrew Mortonc777ac52006-03-25 03:07:36 -080056 return;
57
Thomas Gleixnerc96b3b32010-09-27 12:45:41 +000058 if (!chip->irq_set_affinity)
Andrew Mortonc777ac52006-03-25 03:07:36 -080059 return;
60
Thomas Gleixner239007b2009-11-17 16:46:45 +010061 assert_raw_spin_locked(&desc->lock);
Bryan Holty501f2492006-03-25 03:07:37 -080062
Andrew Mortonc777ac52006-03-25 03:07:36 -080063 /*
64 * If there was a valid mask to work with, please
65 * do the disable, re-program, enable sequence.
66 * This is *not* particularly important for level triggered
67 * but in a edge trigger case, we might be setting rte
Lucas De Marchi25985ed2011-03-30 22:57:33 -030068 * when an active trigger is coming in. This could
Andrew Mortonc777ac52006-03-25 03:07:36 -080069 * cause some ioapics to mal-function.
70 * Being paranoid i guess!
Eric W. Biedermane7b946e2006-10-04 02:16:29 -070071 *
72 * For correct operation this depends on the caller
73 * masking the irqs.
Andrew Mortonc777ac52006-03-25 03:07:36 -080074 */
Jiang Liu818b0f32012-03-30 23:11:34 +080075 if (cpumask_any_and(desc->pending_mask, cpu_online_mask) < nr_cpu_ids)
76 irq_do_set_affinity(&desc->irq_data, desc->pending_mask, false);
Yinghai Lu57b150c2009-04-27 17:59:53 -070077
Mike Travis7f7ace02009-01-10 21:58:08 -080078 cpumask_clear(desc->pending_mask);
Andrew Mortonc777ac52006-03-25 03:07:36 -080079}
Eric W. Biedermane7b946e2006-10-04 02:16:29 -070080
Thomas Gleixnera4395202011-02-04 18:46:16 +010081void irq_move_irq(struct irq_data *idata)
82{
Thomas Gleixnerf1a06392011-01-28 08:47:15 +010083 bool masked;
Eric W. Biedermane7b946e2006-10-04 02:16:29 -070084
Jiang Liu77ed42f2015-06-01 16:05:11 +080085 /*
86 * Get top level irq_data when CONFIG_IRQ_DOMAIN_HIERARCHY is enabled,
87 * and it should be optimized away when CONFIG_IRQ_DOMAIN_HIERARCHY is
88 * disabled. So we avoid an "#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY" here.
89 */
90 idata = irq_desc_get_irq_data(irq_data_to_desc(idata));
91
Thomas Gleixnera4395202011-02-04 18:46:16 +010092 if (likely(!irqd_is_setaffinity_pending(idata)))
Eric W. Biedermane7b946e2006-10-04 02:16:29 -070093 return;
94
Thomas Gleixner32f41252011-03-28 14:10:52 +020095 if (unlikely(irqd_irq_disabled(idata)))
Eric W. Biederman2a786b42007-02-23 04:46:20 -070096 return;
Eric W. Biedermane7b946e2006-10-04 02:16:29 -070097
Thomas Gleixnerf1a06392011-01-28 08:47:15 +010098 /*
99 * Be careful vs. already masked interrupts. If this is a
100 * threaded interrupt with ONESHOT set, we can end up with an
101 * interrupt storm.
102 */
Thomas Gleixner32f41252011-03-28 14:10:52 +0200103 masked = irqd_irq_masked(idata);
Thomas Gleixnerf1a06392011-01-28 08:47:15 +0100104 if (!masked)
Thomas Gleixnera4395202011-02-04 18:46:16 +0100105 idata->chip->irq_mask(idata);
106 irq_move_masked_irq(idata);
Thomas Gleixnerf1a06392011-01-28 08:47:15 +0100107 if (!masked)
Thomas Gleixnera4395202011-02-04 18:46:16 +0100108 idata->chip->irq_unmask(idata);
109}