Thomas Gleixner | 5b497af | 2019-05-29 07:18:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __ND_H__ |
| 6 | #define __ND_H__ |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 7 | #include <linux/libnvdimm.h> |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 8 | #include <linux/badblocks.h> |
Dan Williams | f0dc089 | 2015-05-16 12:28:53 -0400 | [diff] [blame] | 9 | #include <linux/blkdev.h> |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 10 | #include <linux/device.h> |
| 11 | #include <linux/mutex.h> |
| 12 | #include <linux/ndctl.h> |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 13 | #include <linux/types.h> |
Dan Williams | 7199946 | 2016-02-18 10:29:49 -0800 | [diff] [blame] | 14 | #include <linux/nd.h> |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 15 | #include "label.h" |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 16 | |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 17 | enum { |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 18 | /* |
| 19 | * Limits the maximum number of block apertures a dimm can |
| 20 | * support and is an input to the geometry/on-disk-format of a |
| 21 | * BTT instance |
| 22 | */ |
| 23 | ND_MAX_LANES = 256, |
Vishal Verma | fcae695 | 2015-06-25 04:22:39 -0400 | [diff] [blame] | 24 | INT_LBASIZE_ALIGNMENT = 64, |
Vishal Verma | 3ae3d67 | 2017-05-10 15:01:30 -0600 | [diff] [blame] | 25 | NVDIMM_IO_ATOMIC = 1, |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 26 | }; |
| 27 | |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 28 | struct nvdimm_drvdata { |
| 29 | struct device *dev; |
Dan Williams | 02881768 | 2017-08-29 18:28:18 -0700 | [diff] [blame] | 30 | int nslabel_size; |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 31 | struct nd_cmd_get_config_size nsarea; |
| 32 | void *data; |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 33 | bool cxl; |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 34 | int ns_current, ns_next; |
| 35 | struct resource dpa; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 36 | struct kref kref; |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 37 | }; |
| 38 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 39 | static inline const u8 *nsl_ref_name(struct nvdimm_drvdata *ndd, |
| 40 | struct nd_namespace_label *nd_label) |
| 41 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 42 | if (ndd->cxl) |
| 43 | return nd_label->cxl.name; |
| 44 | return nd_label->efi.name; |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | static inline u8 *nsl_get_name(struct nvdimm_drvdata *ndd, |
| 48 | struct nd_namespace_label *nd_label, u8 *name) |
| 49 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 50 | if (ndd->cxl) |
| 51 | return memcpy(name, nd_label->cxl.name, NSLABEL_NAME_LEN); |
| 52 | return memcpy(name, nd_label->efi.name, NSLABEL_NAME_LEN); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 53 | } |
| 54 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 55 | static inline u8 *nsl_set_name(struct nvdimm_drvdata *ndd, |
| 56 | struct nd_namespace_label *nd_label, u8 *name) |
| 57 | { |
| 58 | if (!name) |
| 59 | return NULL; |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 60 | if (ndd->cxl) |
| 61 | return memcpy(nd_label->cxl.name, name, NSLABEL_NAME_LEN); |
| 62 | return memcpy(nd_label->efi.name, name, NSLABEL_NAME_LEN); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 63 | } |
| 64 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 65 | static inline u32 nsl_get_slot(struct nvdimm_drvdata *ndd, |
| 66 | struct nd_namespace_label *nd_label) |
| 67 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 68 | if (ndd->cxl) |
| 69 | return __le32_to_cpu(nd_label->cxl.slot); |
| 70 | return __le32_to_cpu(nd_label->efi.slot); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 71 | } |
| 72 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 73 | static inline void nsl_set_slot(struct nvdimm_drvdata *ndd, |
| 74 | struct nd_namespace_label *nd_label, u32 slot) |
| 75 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 76 | if (ndd->cxl) |
| 77 | nd_label->cxl.slot = __cpu_to_le32(slot); |
| 78 | else |
| 79 | nd_label->efi.slot = __cpu_to_le32(slot); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 80 | } |
| 81 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 82 | static inline u64 nsl_get_checksum(struct nvdimm_drvdata *ndd, |
| 83 | struct nd_namespace_label *nd_label) |
| 84 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 85 | if (ndd->cxl) |
| 86 | return __le64_to_cpu(nd_label->cxl.checksum); |
| 87 | return __le64_to_cpu(nd_label->efi.checksum); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 88 | } |
| 89 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 90 | static inline void nsl_set_checksum(struct nvdimm_drvdata *ndd, |
| 91 | struct nd_namespace_label *nd_label, |
| 92 | u64 checksum) |
| 93 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 94 | if (ndd->cxl) |
| 95 | nd_label->cxl.checksum = __cpu_to_le64(checksum); |
| 96 | else |
| 97 | nd_label->efi.checksum = __cpu_to_le64(checksum); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 98 | } |
| 99 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 100 | static inline u32 nsl_get_flags(struct nvdimm_drvdata *ndd, |
| 101 | struct nd_namespace_label *nd_label) |
| 102 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 103 | if (ndd->cxl) |
| 104 | return __le32_to_cpu(nd_label->cxl.flags); |
| 105 | return __le32_to_cpu(nd_label->efi.flags); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 106 | } |
| 107 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 108 | static inline void nsl_set_flags(struct nvdimm_drvdata *ndd, |
| 109 | struct nd_namespace_label *nd_label, u32 flags) |
| 110 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 111 | if (ndd->cxl) |
| 112 | nd_label->cxl.flags = __cpu_to_le32(flags); |
| 113 | else |
| 114 | nd_label->efi.flags = __cpu_to_le32(flags); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 115 | } |
| 116 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 117 | static inline u64 nsl_get_dpa(struct nvdimm_drvdata *ndd, |
| 118 | struct nd_namespace_label *nd_label) |
| 119 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 120 | if (ndd->cxl) |
| 121 | return __le64_to_cpu(nd_label->cxl.dpa); |
| 122 | return __le64_to_cpu(nd_label->efi.dpa); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 123 | } |
| 124 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 125 | static inline void nsl_set_dpa(struct nvdimm_drvdata *ndd, |
| 126 | struct nd_namespace_label *nd_label, u64 dpa) |
| 127 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 128 | if (ndd->cxl) |
| 129 | nd_label->cxl.dpa = __cpu_to_le64(dpa); |
| 130 | else |
| 131 | nd_label->efi.dpa = __cpu_to_le64(dpa); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 132 | } |
| 133 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 134 | static inline u64 nsl_get_rawsize(struct nvdimm_drvdata *ndd, |
| 135 | struct nd_namespace_label *nd_label) |
| 136 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 137 | if (ndd->cxl) |
| 138 | return __le64_to_cpu(nd_label->cxl.rawsize); |
| 139 | return __le64_to_cpu(nd_label->efi.rawsize); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 140 | } |
| 141 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 142 | static inline void nsl_set_rawsize(struct nvdimm_drvdata *ndd, |
| 143 | struct nd_namespace_label *nd_label, |
| 144 | u64 rawsize) |
| 145 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 146 | if (ndd->cxl) |
| 147 | nd_label->cxl.rawsize = __cpu_to_le64(rawsize); |
| 148 | else |
| 149 | nd_label->efi.rawsize = __cpu_to_le64(rawsize); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 150 | } |
| 151 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 152 | static inline u64 nsl_get_isetcookie(struct nvdimm_drvdata *ndd, |
| 153 | struct nd_namespace_label *nd_label) |
| 154 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 155 | /* WARN future refactor attempts that break this assumption */ |
| 156 | if (dev_WARN_ONCE(ndd->dev, ndd->cxl, |
| 157 | "CXL labels do not use the isetcookie concept\n")) |
| 158 | return 0; |
| 159 | return __le64_to_cpu(nd_label->efi.isetcookie); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 160 | } |
| 161 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 162 | static inline void nsl_set_isetcookie(struct nvdimm_drvdata *ndd, |
| 163 | struct nd_namespace_label *nd_label, |
| 164 | u64 isetcookie) |
| 165 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 166 | if (!ndd->cxl) |
| 167 | nd_label->efi.isetcookie = __cpu_to_le64(isetcookie); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 168 | } |
| 169 | |
Dan Williams | 9761b02 | 2021-08-24 09:05:35 -0700 | [diff] [blame] | 170 | static inline bool nsl_validate_isetcookie(struct nvdimm_drvdata *ndd, |
| 171 | struct nd_namespace_label *nd_label, |
| 172 | u64 cookie) |
| 173 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 174 | /* |
| 175 | * Let the EFI and CXL validation comingle, where fields that |
| 176 | * don't matter to CXL always validate. |
| 177 | */ |
| 178 | if (ndd->cxl) |
| 179 | return true; |
| 180 | return cookie == __le64_to_cpu(nd_label->efi.isetcookie); |
Dan Williams | 9761b02 | 2021-08-24 09:05:35 -0700 | [diff] [blame] | 181 | } |
| 182 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 183 | static inline u16 nsl_get_position(struct nvdimm_drvdata *ndd, |
| 184 | struct nd_namespace_label *nd_label) |
| 185 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 186 | if (ndd->cxl) |
| 187 | return __le16_to_cpu(nd_label->cxl.position); |
| 188 | return __le16_to_cpu(nd_label->efi.position); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 189 | } |
| 190 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 191 | static inline void nsl_set_position(struct nvdimm_drvdata *ndd, |
| 192 | struct nd_namespace_label *nd_label, |
| 193 | u16 position) |
| 194 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 195 | if (ndd->cxl) |
| 196 | nd_label->cxl.position = __cpu_to_le16(position); |
| 197 | else |
| 198 | nd_label->efi.position = __cpu_to_le16(position); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 199 | } |
| 200 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 201 | static inline u16 nsl_get_nlabel(struct nvdimm_drvdata *ndd, |
| 202 | struct nd_namespace_label *nd_label) |
| 203 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 204 | if (ndd->cxl) |
| 205 | return 0; |
| 206 | return __le16_to_cpu(nd_label->efi.nlabel); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 207 | } |
| 208 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 209 | static inline void nsl_set_nlabel(struct nvdimm_drvdata *ndd, |
| 210 | struct nd_namespace_label *nd_label, |
| 211 | u16 nlabel) |
| 212 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 213 | if (!ndd->cxl) |
| 214 | nd_label->efi.nlabel = __cpu_to_le16(nlabel); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 215 | } |
| 216 | |
Dan Williams | 42e192a | 2021-09-08 22:11:48 -0700 | [diff] [blame] | 217 | static inline u16 nsl_get_nrange(struct nvdimm_drvdata *ndd, |
| 218 | struct nd_namespace_label *nd_label) |
| 219 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 220 | if (ndd->cxl) |
| 221 | return __le16_to_cpu(nd_label->cxl.nrange); |
Dan Williams | 42e192a | 2021-09-08 22:11:48 -0700 | [diff] [blame] | 222 | return 1; |
| 223 | } |
| 224 | |
| 225 | static inline void nsl_set_nrange(struct nvdimm_drvdata *ndd, |
| 226 | struct nd_namespace_label *nd_label, |
| 227 | u16 nrange) |
| 228 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 229 | if (ndd->cxl) |
| 230 | nd_label->cxl.nrange = __cpu_to_le16(nrange); |
Dan Williams | 42e192a | 2021-09-08 22:11:48 -0700 | [diff] [blame] | 231 | } |
| 232 | |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 233 | static inline u64 nsl_get_lbasize(struct nvdimm_drvdata *ndd, |
| 234 | struct nd_namespace_label *nd_label) |
| 235 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 236 | /* |
| 237 | * Yes, for some reason the EFI labels convey a massive 64-bit |
| 238 | * lbasize, that got fixed for CXL. |
| 239 | */ |
| 240 | if (ndd->cxl) |
| 241 | return __le16_to_cpu(nd_label->cxl.lbasize); |
| 242 | return __le64_to_cpu(nd_label->efi.lbasize); |
Dan Williams | b4366a8 | 2021-08-24 09:05:30 -0700 | [diff] [blame] | 243 | } |
| 244 | |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 245 | static inline void nsl_set_lbasize(struct nvdimm_drvdata *ndd, |
| 246 | struct nd_namespace_label *nd_label, |
| 247 | u64 lbasize) |
| 248 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 249 | if (ndd->cxl) |
| 250 | nd_label->cxl.lbasize = __cpu_to_le16(lbasize); |
| 251 | else |
| 252 | nd_label->efi.lbasize = __cpu_to_le64(lbasize); |
Dan Williams | 8176f14 | 2021-08-24 09:05:41 -0700 | [diff] [blame] | 253 | } |
| 254 | |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 255 | static inline const uuid_t *nsl_get_uuid(struct nvdimm_drvdata *ndd, |
| 256 | struct nd_namespace_label *nd_label, |
| 257 | uuid_t *uuid) |
| 258 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 259 | if (ndd->cxl) |
| 260 | import_uuid(uuid, nd_label->cxl.uuid); |
| 261 | else |
| 262 | import_uuid(uuid, nd_label->efi.uuid); |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 263 | return uuid; |
| 264 | } |
| 265 | |
| 266 | static inline const uuid_t *nsl_set_uuid(struct nvdimm_drvdata *ndd, |
| 267 | struct nd_namespace_label *nd_label, |
| 268 | const uuid_t *uuid) |
| 269 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 270 | if (ndd->cxl) |
| 271 | export_uuid(nd_label->cxl.uuid, uuid); |
| 272 | else |
| 273 | export_uuid(nd_label->efi.uuid, uuid); |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 274 | return uuid; |
| 275 | } |
| 276 | |
| 277 | static inline bool nsl_uuid_equal(struct nvdimm_drvdata *ndd, |
| 278 | struct nd_namespace_label *nd_label, |
| 279 | const uuid_t *uuid) |
| 280 | { |
| 281 | uuid_t tmp; |
| 282 | |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 283 | if (ndd->cxl) |
| 284 | import_uuid(&tmp, nd_label->cxl.uuid); |
| 285 | else |
| 286 | import_uuid(&tmp, nd_label->efi.uuid); |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 287 | return uuid_equal(&tmp, uuid); |
| 288 | } |
| 289 | |
| 290 | static inline const u8 *nsl_uuid_raw(struct nvdimm_drvdata *ndd, |
| 291 | struct nd_namespace_label *nd_label) |
| 292 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 293 | if (ndd->cxl) |
| 294 | return nd_label->cxl.uuid; |
| 295 | return nd_label->efi.uuid; |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 296 | } |
| 297 | |
Dan Williams | f56541a | 2021-08-24 09:05:51 -0700 | [diff] [blame] | 298 | bool nsl_validate_blk_isetcookie(struct nvdimm_drvdata *ndd, |
| 299 | struct nd_namespace_label *nd_label, |
| 300 | u64 isetcookie); |
Dan Williams | 8b03aa0 | 2021-08-24 09:06:02 -0700 | [diff] [blame] | 301 | bool nsl_validate_type_guid(struct nvdimm_drvdata *ndd, |
| 302 | struct nd_namespace_label *nd_label, guid_t *guid); |
Dan Williams | a6e6d72 | 2021-08-24 09:06:07 -0700 | [diff] [blame] | 303 | enum nvdimm_claim_class nsl_get_claim_class(struct nvdimm_drvdata *ndd, |
| 304 | struct nd_namespace_label *nd_label); |
Dan Williams | f56541a | 2021-08-24 09:05:51 -0700 | [diff] [blame] | 305 | |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 306 | struct nd_region_data { |
| 307 | int ns_count; |
| 308 | int ns_active; |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 309 | unsigned int hints_shift; |
Gustavo A. R. Silva | 9106137 | 2020-03-19 18:09:37 -0500 | [diff] [blame] | 310 | void __iomem *flush_wpq[]; |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 311 | }; |
| 312 | |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 313 | static inline void __iomem *ndrd_get_flush_wpq(struct nd_region_data *ndrd, |
| 314 | int dimm, int hint) |
| 315 | { |
| 316 | unsigned int num = 1 << ndrd->hints_shift; |
| 317 | unsigned int mask = num - 1; |
| 318 | |
| 319 | return ndrd->flush_wpq[dimm * num + (hint & mask)]; |
| 320 | } |
| 321 | |
| 322 | static inline void ndrd_set_flush_wpq(struct nd_region_data *ndrd, int dimm, |
| 323 | int hint, void __iomem *flush) |
| 324 | { |
| 325 | unsigned int num = 1 << ndrd->hints_shift; |
| 326 | unsigned int mask = num - 1; |
| 327 | |
| 328 | ndrd->flush_wpq[dimm * num + (hint & mask)] = flush; |
| 329 | } |
| 330 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 331 | static inline struct nd_namespace_index *to_namespace_index( |
| 332 | struct nvdimm_drvdata *ndd, int i) |
| 333 | { |
| 334 | if (i < 0) |
| 335 | return NULL; |
| 336 | |
| 337 | return ndd->data + sizeof_namespace_index(ndd) * i; |
| 338 | } |
| 339 | |
| 340 | static inline struct nd_namespace_index *to_current_namespace_index( |
| 341 | struct nvdimm_drvdata *ndd) |
| 342 | { |
| 343 | return to_namespace_index(ndd, ndd->ns_current); |
| 344 | } |
| 345 | |
| 346 | static inline struct nd_namespace_index *to_next_namespace_index( |
| 347 | struct nvdimm_drvdata *ndd) |
| 348 | { |
| 349 | return to_namespace_index(ndd, ndd->ns_next); |
| 350 | } |
| 351 | |
Dan Williams | 564e871 | 2017-06-03 18:30:43 +0900 | [diff] [blame] | 352 | unsigned sizeof_namespace_label(struct nvdimm_drvdata *ndd); |
| 353 | |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 354 | #define efi_namespace_label_has(ndd, field) \ |
| 355 | (!ndd->cxl && offsetof(struct nvdimm_efi_label, field) \ |
Dan Williams | 564e871 | 2017-06-03 18:30:43 +0900 | [diff] [blame] | 356 | < sizeof_namespace_label(ndd)) |
| 357 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 358 | #define nd_dbg_dpa(r, d, res, fmt, arg...) \ |
| 359 | dev_dbg((r) ? &(r)->dev : (d)->dev, "%s: %.13s: %#llx @ %#llx " fmt, \ |
| 360 | (r) ? dev_name((d)->dev) : "", res ? res->name : "null", \ |
| 361 | (unsigned long long) (res ? resource_size(res) : 0), \ |
| 362 | (unsigned long long) (res ? res->start : 0), ##arg) |
| 363 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 364 | #define for_each_dpa_resource(ndd, res) \ |
| 365 | for (res = (ndd)->dpa.child; res; res = res->sibling) |
| 366 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 367 | #define for_each_dpa_resource_safe(ndd, res, next) \ |
| 368 | for (res = (ndd)->dpa.child, next = res ? res->sibling : NULL; \ |
| 369 | res; res = next, next = next ? next->sibling : NULL) |
| 370 | |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 371 | struct nd_percpu_lane { |
| 372 | int count; |
| 373 | spinlock_t lock; |
| 374 | }; |
| 375 | |
Dan Williams | c4703ce | 2019-04-30 21:51:21 -0700 | [diff] [blame] | 376 | enum nd_label_flags { |
| 377 | ND_LABEL_REAP, |
| 378 | }; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 379 | struct nd_label_ent { |
| 380 | struct list_head list; |
Dan Williams | c4703ce | 2019-04-30 21:51:21 -0700 | [diff] [blame] | 381 | unsigned long flags; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 382 | struct nd_namespace_label *label; |
| 383 | }; |
| 384 | |
| 385 | enum nd_mapping_lock_class { |
| 386 | ND_MAPPING_CLASS0, |
| 387 | ND_MAPPING_UUID_SCAN, |
| 388 | }; |
| 389 | |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 390 | struct nd_mapping { |
| 391 | struct nvdimm *nvdimm; |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 392 | u64 start; |
| 393 | u64 size; |
Dan Williams | 401c0a1 | 2017-08-04 17:20:16 -0700 | [diff] [blame] | 394 | int position; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 395 | struct list_head labels; |
| 396 | struct mutex lock; |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 397 | /* |
| 398 | * @ndd is for private use at region enable / disable time for |
| 399 | * get_ndd() + put_ndd(), all other nd_mapping to ndd |
| 400 | * conversions use to_ndd() which respects enabled state of the |
| 401 | * nvdimm. |
| 402 | */ |
| 403 | struct nvdimm_drvdata *ndd; |
| 404 | }; |
| 405 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 406 | struct nd_region { |
| 407 | struct device dev; |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 408 | struct ida ns_ida; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 409 | struct ida btt_ida; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 410 | struct ida pfn_ida; |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 411 | struct ida dax_ida; |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 412 | unsigned long flags; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 413 | struct device *ns_seed; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 414 | struct device *btt_seed; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 415 | struct device *pfn_seed; |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 416 | struct device *dax_seed; |
Dan Williams | 2522afb | 2020-01-30 12:06:23 -0800 | [diff] [blame] | 417 | unsigned long align; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 418 | u16 ndr_mappings; |
| 419 | u64 ndr_size; |
| 420 | u64 ndr_start; |
Dan Williams | 8fc5c73 | 2018-11-09 12:43:07 -0800 | [diff] [blame] | 421 | int id, num_lanes, ro, numa_node, target_node; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 422 | void *provider_data; |
Toshi Kani | 975750a | 2017-06-12 16:25:11 -0600 | [diff] [blame] | 423 | struct kernfs_node *bb_state; |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 424 | struct badblocks bb; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 425 | struct nd_interleave_set *nd_set; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 426 | struct nd_percpu_lane __percpu *lane; |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 427 | int (*flush)(struct nd_region *nd_region, struct bio *bio); |
Gustavo A. R. Silva | 9106137 | 2020-03-19 18:09:37 -0500 | [diff] [blame] | 428 | struct nd_mapping mapping[]; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 429 | }; |
| 430 | |
Dan Williams | 8172db9 | 2021-09-08 22:11:42 -0700 | [diff] [blame] | 431 | static inline bool nsl_validate_nlabel(struct nd_region *nd_region, |
| 432 | struct nvdimm_drvdata *ndd, |
| 433 | struct nd_namespace_label *nd_label) |
| 434 | { |
Dan Williams | 5af9683 | 2021-09-08 22:12:04 -0700 | [diff] [blame] | 435 | if (ndd->cxl) |
| 436 | return true; |
Dan Williams | 8172db9 | 2021-09-08 22:11:42 -0700 | [diff] [blame] | 437 | return nsl_get_nlabel(ndd, nd_label) == nd_region->ndr_mappings; |
| 438 | } |
| 439 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 440 | struct nd_blk_region { |
| 441 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 442 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
| 443 | void *iobuf, u64 len, int rw); |
| 444 | void *blk_provider_data; |
| 445 | struct nd_region nd_region; |
| 446 | }; |
| 447 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 448 | /* |
| 449 | * Lookup next in the repeating sequence of 01, 10, and 11. |
| 450 | */ |
| 451 | static inline unsigned nd_inc_seq(unsigned seq) |
| 452 | { |
| 453 | static const unsigned next[] = { 0, 2, 3, 1 }; |
| 454 | |
| 455 | return next[seq & 3]; |
| 456 | } |
Dan Williams | f524bf2 | 2015-05-30 12:36:02 -0400 | [diff] [blame] | 457 | |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 458 | struct btt; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 459 | struct nd_btt { |
| 460 | struct device dev; |
| 461 | struct nd_namespace_common *ndns; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 462 | struct btt *btt; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 463 | unsigned long lbasize; |
Vishal Verma | abe8b4e | 2016-07-27 16:38:59 -0600 | [diff] [blame] | 464 | u64 size; |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 465 | uuid_t *uuid; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 466 | int id; |
Vishal Verma | 14e4945 | 2017-06-28 14:25:00 -0600 | [diff] [blame] | 467 | int initial_offset; |
| 468 | u16 version_major; |
| 469 | u16 version_minor; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 470 | }; |
| 471 | |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 472 | enum nd_pfn_mode { |
| 473 | PFN_MODE_NONE, |
| 474 | PFN_MODE_RAM, |
| 475 | PFN_MODE_PMEM, |
| 476 | }; |
| 477 | |
| 478 | struct nd_pfn { |
| 479 | int id; |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 480 | uuid_t *uuid; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 481 | struct device dev; |
Dan Williams | 315c562 | 2015-12-10 14:45:23 -0800 | [diff] [blame] | 482 | unsigned long align; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 483 | unsigned long npfns; |
| 484 | enum nd_pfn_mode mode; |
| 485 | struct nd_pfn_sb *pfn_sb; |
| 486 | struct nd_namespace_common *ndns; |
| 487 | }; |
| 488 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 489 | struct nd_dax { |
| 490 | struct nd_pfn nd_pfn; |
| 491 | }; |
| 492 | |
Aneesh Kumar K.V | 8f4b01f | 2019-10-31 16:27:41 +0530 | [diff] [blame] | 493 | static inline u32 nd_info_block_reserve(void) |
| 494 | { |
| 495 | return ALIGN(SZ_8K, PAGE_SIZE); |
| 496 | } |
| 497 | |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 498 | enum nd_async_mode { |
| 499 | ND_SYNC, |
| 500 | ND_ASYNC, |
| 501 | }; |
| 502 | |
Vishal Verma | 41cd8b7 | 2015-06-25 04:21:52 -0400 | [diff] [blame] | 503 | int nd_integrity_init(struct gendisk *disk, unsigned long meta_size); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 504 | void wait_nvdimm_bus_probe_idle(struct device *dev); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 505 | void nd_device_register(struct device *dev); |
| 506 | void nd_device_unregister(struct device *dev, enum nd_async_mode mode); |
Dan Williams | 7199946 | 2016-02-18 10:29:49 -0800 | [diff] [blame] | 507 | void nd_device_notify(struct device *dev, enum nvdimm_event event); |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 508 | int nd_uuid_store(struct device *dev, uuid_t **uuid_out, const char *buf, |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 509 | size_t len); |
Dan Williams | b2c48f9 | 2017-08-11 17:36:54 -0700 | [diff] [blame] | 510 | ssize_t nd_size_select_show(unsigned long current_size, |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 511 | const unsigned long *supported, char *buf); |
Dan Williams | b2c48f9 | 2017-08-11 17:36:54 -0700 | [diff] [blame] | 512 | ssize_t nd_size_select_store(struct device *dev, const char *buf, |
| 513 | unsigned long *current_size, const unsigned long *supported); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 514 | int __init nvdimm_init(void); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 515 | int __init nd_region_init(void); |
Dan Williams | b3fde74 | 2017-06-04 10:18:39 +0900 | [diff] [blame] | 516 | int __init nd_label_init(void); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 517 | void nvdimm_exit(void); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 518 | void nd_region_exit(void); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 519 | struct nvdimm; |
Dan Williams | adbb682 | 2019-11-12 17:00:24 -0800 | [diff] [blame] | 520 | extern const struct attribute_group nd_device_attribute_group; |
Dan Williams | e2f6a0e | 2019-11-19 09:51:54 -0800 | [diff] [blame] | 521 | extern const struct attribute_group nd_numa_attribute_group; |
Dan Williams | e755799a | 2019-11-12 17:08:56 -0800 | [diff] [blame] | 522 | extern const struct attribute_group *nvdimm_bus_attribute_groups[]; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 523 | struct nvdimm_drvdata *to_ndd(struct nd_mapping *nd_mapping); |
Toshi Kani | aee6598 | 2016-08-16 13:08:40 -0600 | [diff] [blame] | 524 | int nvdimm_check_config_data(struct device *dev); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 525 | int nvdimm_init_nsarea(struct nvdimm_drvdata *ndd); |
| 526 | int nvdimm_init_config_data(struct nvdimm_drvdata *ndd); |
Alexander Duyck | 2d657d1 | 2018-10-10 16:39:20 -0700 | [diff] [blame] | 527 | int nvdimm_get_config_data(struct nvdimm_drvdata *ndd, void *buf, |
| 528 | size_t offset, size_t len); |
Dan Williams | f524bf2 | 2015-05-30 12:36:02 -0400 | [diff] [blame] | 529 | int nvdimm_set_config_data(struct nvdimm_drvdata *ndd, size_t offset, |
| 530 | void *buf, size_t len); |
Dan Williams | 59e6473 | 2016-03-08 07:16:07 -0800 | [diff] [blame] | 531 | long nvdimm_clear_poison(struct device *dev, phys_addr_t phys, |
| 532 | unsigned int len); |
Dan Williams | a0e3745 | 2020-01-30 12:06:18 -0800 | [diff] [blame] | 533 | void nvdimm_set_labeling(struct device *dev); |
Dan Williams | 8f078b3 | 2017-05-04 14:01:24 -0700 | [diff] [blame] | 534 | void nvdimm_set_locked(struct device *dev); |
Dan Williams | d34cb80 | 2017-09-25 11:01:31 -0700 | [diff] [blame] | 535 | void nvdimm_clear_locked(struct device *dev); |
Dan Williams | 1cd7386 | 2019-01-19 08:45:56 -0800 | [diff] [blame] | 536 | int nvdimm_security_setup_events(struct device *dev); |
Dave Jiang | 4c6926a | 2018-12-06 12:40:01 -0800 | [diff] [blame] | 537 | #if IS_ENABLED(CONFIG_NVDIMM_KEYS) |
| 538 | int nvdimm_security_unlock(struct device *dev); |
| 539 | #else |
| 540 | static inline int nvdimm_security_unlock(struct device *dev) |
| 541 | { |
| 542 | return 0; |
| 543 | } |
| 544 | #endif |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 545 | struct nd_btt *to_nd_btt(struct device *dev); |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 546 | |
| 547 | struct nd_gen_sb { |
| 548 | char reserved[SZ_4K - 8]; |
| 549 | __le64 checksum; |
| 550 | }; |
| 551 | |
| 552 | u64 nd_sb_checksum(struct nd_gen_sb *sb); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 553 | #if IS_ENABLED(CONFIG_BTT) |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 554 | int nd_btt_probe(struct device *dev, struct nd_namespace_common *ndns); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 555 | bool is_nd_btt(struct device *dev); |
| 556 | struct device *nd_btt_create(struct nd_region *nd_region); |
| 557 | #else |
Dan Williams | e32bc72 | 2016-03-17 18:23:09 -0700 | [diff] [blame] | 558 | static inline int nd_btt_probe(struct device *dev, |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 559 | struct nd_namespace_common *ndns) |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 560 | { |
| 561 | return -ENODEV; |
| 562 | } |
| 563 | |
| 564 | static inline bool is_nd_btt(struct device *dev) |
| 565 | { |
| 566 | return false; |
| 567 | } |
| 568 | |
| 569 | static inline struct device *nd_btt_create(struct nd_region *nd_region) |
| 570 | { |
| 571 | return NULL; |
| 572 | } |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 573 | #endif |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 574 | |
| 575 | struct nd_pfn *to_nd_pfn(struct device *dev); |
| 576 | #if IS_ENABLED(CONFIG_NVDIMM_PFN) |
Oliver O'Halloran | 0dd6964 | 2017-06-27 19:56:33 +1000 | [diff] [blame] | 577 | |
Aneesh Kumar K.V | f537669 | 2019-09-05 21:16:03 +0530 | [diff] [blame] | 578 | #define MAX_NVDIMM_ALIGN 4 |
Oliver O'Halloran | 0dd6964 | 2017-06-27 19:56:33 +1000 | [diff] [blame] | 579 | |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 580 | int nd_pfn_probe(struct device *dev, struct nd_namespace_common *ndns); |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 581 | bool is_nd_pfn(struct device *dev); |
| 582 | struct device *nd_pfn_create(struct nd_region *nd_region); |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 583 | struct device *nd_pfn_devinit(struct nd_pfn *nd_pfn, |
| 584 | struct nd_namespace_common *ndns); |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 585 | int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig); |
Dan Williams | 78c81cc | 2019-11-06 19:56:41 -0800 | [diff] [blame] | 586 | extern const struct attribute_group *nd_pfn_attribute_groups[]; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 587 | #else |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 588 | static inline int nd_pfn_probe(struct device *dev, |
| 589 | struct nd_namespace_common *ndns) |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 590 | { |
| 591 | return -ENODEV; |
| 592 | } |
| 593 | |
| 594 | static inline bool is_nd_pfn(struct device *dev) |
| 595 | { |
| 596 | return false; |
| 597 | } |
| 598 | |
| 599 | static inline struct device *nd_pfn_create(struct nd_region *nd_region) |
| 600 | { |
| 601 | return NULL; |
| 602 | } |
Dan Williams | 32ab0a3f | 2015-08-01 02:16:37 -0400 | [diff] [blame] | 603 | |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 604 | static inline int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig) |
Dan Williams | 32ab0a3f | 2015-08-01 02:16:37 -0400 | [diff] [blame] | 605 | { |
| 606 | return -ENODEV; |
| 607 | } |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 608 | #endif |
| 609 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 610 | struct nd_dax *to_nd_dax(struct device *dev); |
| 611 | #if IS_ENABLED(CONFIG_NVDIMM_DAX) |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 612 | int nd_dax_probe(struct device *dev, struct nd_namespace_common *ndns); |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 613 | bool is_nd_dax(struct device *dev); |
| 614 | struct device *nd_dax_create(struct nd_region *nd_region); |
| 615 | #else |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 616 | static inline int nd_dax_probe(struct device *dev, |
| 617 | struct nd_namespace_common *ndns) |
| 618 | { |
| 619 | return -ENODEV; |
| 620 | } |
| 621 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 622 | static inline bool is_nd_dax(struct device *dev) |
| 623 | { |
| 624 | return false; |
| 625 | } |
| 626 | |
| 627 | static inline struct device *nd_dax_create(struct nd_region *nd_region) |
| 628 | { |
| 629 | return NULL; |
| 630 | } |
| 631 | #endif |
| 632 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 633 | int nd_region_to_nstype(struct nd_region *nd_region); |
| 634 | int nd_region_register_namespaces(struct nd_region *nd_region, int *err); |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 635 | u64 nd_region_interleave_set_cookie(struct nd_region *nd_region, |
| 636 | struct nd_namespace_index *nsindex); |
Dan Williams | 86ef58a | 2017-02-28 18:32:48 -0800 | [diff] [blame] | 637 | u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 638 | void nvdimm_bus_lock(struct device *dev); |
| 639 | void nvdimm_bus_unlock(struct device *dev); |
| 640 | bool is_nvdimm_bus_locked(struct device *dev); |
Christoph Hellwig | 32f61d6 | 2020-09-01 17:57:47 +0200 | [diff] [blame] | 641 | void nvdimm_check_and_set_ro(struct gendisk *disk); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 642 | void nvdimm_drvdata_release(struct kref *kref); |
| 643 | void put_ndd(struct nvdimm_drvdata *ndd); |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 644 | int nd_label_reserve_dpa(struct nvdimm_drvdata *ndd); |
| 645 | void nvdimm_free_dpa(struct nvdimm_drvdata *ndd, struct resource *res); |
| 646 | struct resource *nvdimm_allocate_dpa(struct nvdimm_drvdata *ndd, |
| 647 | struct nd_label_id *label_id, resource_size_t start, |
| 648 | resource_size_t n); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 649 | resource_size_t nvdimm_namespace_capacity(struct nd_namespace_common *ndns); |
Dan Williams | 08e6b3c | 2018-06-13 09:08:36 -0700 | [diff] [blame] | 650 | bool nvdimm_namespace_locked(struct nd_namespace_common *ndns); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 651 | struct nd_namespace_common *nvdimm_namespace_common_probe(struct device *dev); |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 652 | int nvdimm_namespace_attach_btt(struct nd_namespace_common *ndns); |
Dan Williams | 298f2bc | 2016-03-15 16:41:04 -0700 | [diff] [blame] | 653 | int nvdimm_namespace_detach_btt(struct nd_btt *nd_btt); |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 654 | const char *nvdimm_namespace_disk_name(struct nd_namespace_common *ndns, |
| 655 | char *name); |
Dan Williams | f979b13 | 2017-06-04 12:12:07 +0900 | [diff] [blame] | 656 | unsigned int pmem_sector_size(struct nd_namespace_common *ndns); |
Dan Williams | a4574f6 | 2020-10-13 16:50:29 -0700 | [diff] [blame] | 657 | struct range; |
Dan Williams | a390180 | 2016-04-07 20:02:06 -0700 | [diff] [blame] | 658 | void nvdimm_badblocks_populate(struct nd_region *nd_region, |
Dan Williams | a4574f6 | 2020-10-13 16:50:29 -0700 | [diff] [blame] | 659 | struct badblocks *bb, const struct range *range); |
Aneesh Kumar K.V | 8f4b01f | 2019-10-31 16:27:41 +0530 | [diff] [blame] | 660 | int devm_namespace_enable(struct device *dev, struct nd_namespace_common *ndns, |
| 661 | resource_size_t size); |
| 662 | void devm_namespace_disable(struct device *dev, |
| 663 | struct nd_namespace_common *ndns); |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 664 | #if IS_ENABLED(CONFIG_ND_CLAIM) |
Aneesh Kumar K.V | e96f0bf | 2019-09-05 21:15:59 +0530 | [diff] [blame] | 665 | /* max struct page size independent of kernel config */ |
| 666 | #define MAX_STRUCT_PAGE_SIZE 64 |
Christoph Hellwig | e8d5134 | 2017-12-29 08:54:05 +0100 | [diff] [blame] | 667 | int nvdimm_setup_pfn(struct nd_pfn *nd_pfn, struct dev_pagemap *pgmap); |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 668 | #else |
Christoph Hellwig | e8d5134 | 2017-12-29 08:54:05 +0100 | [diff] [blame] | 669 | static inline int nvdimm_setup_pfn(struct nd_pfn *nd_pfn, |
| 670 | struct dev_pagemap *pgmap) |
Dan Williams | ac515c0 | 2016-03-22 00:29:43 -0700 | [diff] [blame] | 671 | { |
Christoph Hellwig | e8d5134 | 2017-12-29 08:54:05 +0100 | [diff] [blame] | 672 | return -ENXIO; |
Dan Williams | ac515c0 | 2016-03-22 00:29:43 -0700 | [diff] [blame] | 673 | } |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 674 | #endif |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 675 | int nd_blk_region_init(struct nd_region *nd_region); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 676 | int nd_region_activate(struct nd_region *nd_region); |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 677 | static inline bool is_bad_pmem(struct badblocks *bb, sector_t sector, |
| 678 | unsigned int len) |
| 679 | { |
| 680 | if (bb->count) { |
| 681 | sector_t first_bad; |
| 682 | int num_bad; |
| 683 | |
| 684 | return !!badblocks_check(bb, sector, len / 512, &first_bad, |
| 685 | &num_bad); |
| 686 | } |
| 687 | |
| 688 | return false; |
| 689 | } |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 690 | resource_size_t nd_namespace_blk_validate(struct nd_namespace_blk *nsblk); |
Dan Williams | d1c6e08 | 2021-09-08 22:11:37 -0700 | [diff] [blame] | 691 | const uuid_t *nd_dev_to_uuid(struct device *dev); |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 692 | bool pmem_should_map_pages(struct device *dev); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 693 | #endif /* __ND_H__ */ |