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Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +00001// SPDX-License-Identifier: GPL-2.0
Gilad Ben-Yossef03963ca2019-04-18 16:38:53 +03002/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +00003
4#include "cc_driver.h"
5#include "cc_sram_mgr.h"
6
7/**
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +00008 * cc_sram_mgr_init() - Initializes SRAM pool.
9 * The pool starts right at the beginning of SRAM.
10 * Returns zero for success, negative value otherwise.
11 *
12 * @drvdata: Associated device driver context
Geert Uytterhoeven31568ab2020-02-11 19:19:22 +010013 *
14 * Return:
15 * 0 for success, negative error code for failure.
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000016 */
17int cc_sram_mgr_init(struct cc_drvdata *drvdata)
18{
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010019 u32 start = 0;
Gilad Ben-Yossef27b3b222018-02-19 14:51:23 +000020 struct device *dev = drvdata_to_dev(drvdata);
21
22 if (drvdata->hw_rev < CC_HW_REV_712) {
23 /* Pool starts after ROM bytes */
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010024 start = cc_ioread(drvdata, CC_REG(HOST_SEP_SRAM_THRESHOLD));
Gilad Ben-Yossef27b3b222018-02-19 14:51:23 +000025 if ((start & 0x3) != 0) {
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010026 dev_err(dev, "Invalid SRAM offset 0x%x\n", start);
Gilad Ben-Yossef27b3b222018-02-19 14:51:23 +000027 return -EINVAL;
28 }
29 }
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000030
Geert Uytterhoevenf1b19df2020-02-11 19:19:12 +010031 drvdata->sram_free_offset = start;
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000032 return 0;
33}
34
Geert Uytterhoeven31568ab2020-02-11 19:19:22 +010035/**
36 * cc_sram_alloc() - Allocate buffer from SRAM pool.
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000037 *
Geert Uytterhoeven31568ab2020-02-11 19:19:22 +010038 * @drvdata: Associated device driver context
39 * @size: The requested numer of bytes to allocate
40 *
41 * Return:
42 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000043 */
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010044u32 cc_sram_alloc(struct cc_drvdata *drvdata, u32 size)
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000045{
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000046 struct device *dev = drvdata_to_dev(drvdata);
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010047 u32 p;
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000048
49 if ((size & 0x3)) {
50 dev_err(dev, "Requested buffer size (%u) is not multiple of 4",
51 size);
52 return NULL_SRAM_ADDR;
53 }
Geert Uytterhoevenf1b19df2020-02-11 19:19:12 +010054 if (size > (CC_CC_SRAM_SIZE - drvdata->sram_free_offset)) {
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010055 dev_err(dev, "Not enough space to allocate %u B (at offset %u)\n",
Geert Uytterhoevenf1b19df2020-02-11 19:19:12 +010056 size, drvdata->sram_free_offset);
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000057 return NULL_SRAM_ADDR;
58 }
59
Geert Uytterhoevenf1b19df2020-02-11 19:19:12 +010060 p = drvdata->sram_free_offset;
61 drvdata->sram_free_offset += size;
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010062 dev_dbg(dev, "Allocated %u B @ %u\n", size, p);
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000063 return p;
64}
65
66/**
67 * cc_set_sram_desc() - Create const descriptors sequence to
68 * set values in given array into SRAM.
69 * Note: each const value can't exceed word size.
70 *
71 * @src: A pointer to array of words to set as consts.
72 * @dst: The target SRAM buffer to set into
Geert Uytterhoeven31568ab2020-02-11 19:19:22 +010073 * @nelement: The number of words in "src" array
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000074 * @seq: A pointer to the given IN/OUT descriptor sequence
75 * @seq_len: A pointer to the given IN/OUT sequence length
76 */
Geert Uytterhoeven1a895f12020-02-11 19:19:07 +010077void cc_set_sram_desc(const u32 *src, u32 dst, unsigned int nelement,
78 struct cc_hw_desc *seq, unsigned int *seq_len)
Gilad Ben-Yossef4c3f9722018-01-22 09:27:00 +000079{
80 u32 i;
81 unsigned int idx = *seq_len;
82
83 for (i = 0; i < nelement; i++, idx++) {
84 hw_desc_init(&seq[idx]);
85 set_din_const(&seq[idx], src[i], sizeof(u32));
86 set_dout_sram(&seq[idx], dst + (i * sizeof(u32)), sizeof(u32));
87 set_flow_mode(&seq[idx], BYPASS);
88 }
89
90 *seq_len = idx;
91}