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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7270dedc8438c7247474a33a8334f3920816e2c2 / . / arch / arm / boot / dts / r8a7745.dtsi
blob: 0c3f4c5b345b7d95f8e5ce1bbf22bc5907166e21 [file] [log] [blame]
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]1/*
2 * Device Tree Source for the r8a7745 SoC
3 *
Sergei Shtylyov95b94ed2017-04-15 23:18:26 +0300[diff] [blame]4 * Copyright (C) 2016-2017 Cogent Embedded Inc.
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
14#include <dt-bindings/power/r8a7745-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7745";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
Fabrizio Castro282fbf42017-08-22 16:27:02 +0100[diff] [blame]21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
Fabrizio Castro0ee0aff2017-10-23 18:09:30 +0100[diff] [blame]28 i2c6 = &iic0;
29 i2c7 = &iic1;
Fabrizio Castro2391d022017-09-13 18:05:40 +0100[diff] [blame]30 spi0 = &qspi;
Fabrizio Castroe5276492017-09-27 10:57:05 +0100[diff] [blame]31 spi1 = &msiof0;
32 spi2 = &msiof1;
33 spi3 = &msiof2;
Fabrizio Castro1a20f212017-11-16 18:22:51 +0000[diff] [blame]34 vin0 = &vin0;
35 vin1 = &vin1;
Fabrizio Castro282fbf42017-08-22 16:27:02 +0100[diff] [blame]36 };
37
Biju Das44da6312017-12-20 20:01:57 +0000[diff] [blame]38 /*
39 * The external audio clocks are configured as 0 Hz fixed
40 * frequency clocks by default. Boards that provide audio
41 * clocks should override them.
42 */
43 audio_clka: audio_clka {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <0>;
47 };
48 audio_clkb: audio_clkb {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 };
53 audio_clkc: audio_clkc {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <0>;
57 };
58
Simon Hormand913ef12017-12-18 22:50:43 +0100[diff] [blame]59 /* External CAN clock */
60 can_clk: can {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 /* This value must be overridden by the board. */
64 clock-frequency = <0>;
65 };
66
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]67 cpus {
68 #address-cells = <1>;
69 #size-cells = <0>;
Fabrizio Castroaaca1ff2017-12-06 12:05:29 +0000[diff] [blame]70 enable-method = "renesas,apmu";
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]71
72 cpu0: cpu@0 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a7";
75 reg = <0>;
76 clock-frequency = <1000000000>;
77 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
78 power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
79 next-level-cache = <&L2_CA7>;
80 };
81
Fabrizio Castroaaca1ff2017-12-06 12:05:29 +0000[diff] [blame]82 cpu1: cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a7";
85 reg = <1>;
86 clock-frequency = <1000000000>;
Biju Das5b062012017-12-21 14:52:25 +0000[diff] [blame]87 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
Fabrizio Castroaaca1ff2017-12-06 12:05:29 +0000[diff] [blame]88 power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
89 next-level-cache = <&L2_CA7>;
90 };
91
Geert Uytterhoeven51c00a92017-03-06 17:40:38 +0100[diff] [blame]92 L2_CA7: cache-controller-0 {
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]93 compatible = "cache";
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]94 cache-unified;
95 cache-level = <2>;
96 power-domains = <&sysc R8A7745_PD_CA7_SCU>;
97 };
98 };
99
Simon Hormand913ef12017-12-18 22:50:43 +0100[diff] [blame]100 /* External root clock */
101 extal_clk: extal {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 /* This value must be overridden by the board. */
105 clock-frequency = <0>;
106 };
107
108 /* External SCIF clock */
109 scif_clk: scif {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 /* This value must be overridden by the board. */
113 clock-frequency = <0>;
114 };
115
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]116 soc {
117 compatible = "simple-bus";
118 interrupt-parent = <&gic>;
119
120 #address-cells = <2>;
121 #size-cells = <2>;
122 ranges;
123
Biju Das3163c032017-08-18 15:56:01 +0100[diff] [blame]124 gpio0: gpio@e6050000 {
125 compatible = "renesas,gpio-r8a7745",
126 "renesas,rcar-gen2-gpio";
127 reg = <0 0xe6050000 0 0x50>;
128 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
129 #gpio-cells = <2>;
130 gpio-controller;
131 gpio-ranges = <&pfc 0 0 32>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 clocks = <&cpg CPG_MOD 912>;
135 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
136 resets = <&cpg 912>;
137 };
138
139 gpio1: gpio@e6051000 {
140 compatible = "renesas,gpio-r8a7745",
141 "renesas,rcar-gen2-gpio";
142 reg = <0 0xe6051000 0 0x50>;
143 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 32 26>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&cpg CPG_MOD 911>;
150 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
151 resets = <&cpg 911>;
152 };
153
154 gpio2: gpio@e6052000 {
155 compatible = "renesas,gpio-r8a7745",
156 "renesas,rcar-gen2-gpio";
157 reg = <0 0xe6052000 0 0x50>;
158 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
159 #gpio-cells = <2>;
160 gpio-controller;
161 gpio-ranges = <&pfc 0 64 32>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
164 clocks = <&cpg CPG_MOD 910>;
165 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
166 resets = <&cpg 910>;
167 };
168
169 gpio3: gpio@e6053000 {
170 compatible = "renesas,gpio-r8a7745",
171 "renesas,rcar-gen2-gpio";
172 reg = <0 0xe6053000 0 0x50>;
173 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
174 #gpio-cells = <2>;
175 gpio-controller;
176 gpio-ranges = <&pfc 0 96 32>;
177 #interrupt-cells = <2>;
178 interrupt-controller;
179 clocks = <&cpg CPG_MOD 909>;
180 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
181 resets = <&cpg 909>;
182 };
183
184 gpio4: gpio@e6054000 {
185 compatible = "renesas,gpio-r8a7745",
186 "renesas,rcar-gen2-gpio";
187 reg = <0 0xe6054000 0 0x50>;
188 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
189 #gpio-cells = <2>;
190 gpio-controller;
191 gpio-ranges = <&pfc 0 128 32>;
192 #interrupt-cells = <2>;
193 interrupt-controller;
194 clocks = <&cpg CPG_MOD 908>;
195 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
196 resets = <&cpg 908>;
197 };
198
199 gpio5: gpio@e6055000 {
200 compatible = "renesas,gpio-r8a7745",
201 "renesas,rcar-gen2-gpio";
202 reg = <0 0xe6055000 0 0x50>;
203 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
204 #gpio-cells = <2>;
205 gpio-controller;
206 gpio-ranges = <&pfc 0 160 28>;
207 #interrupt-cells = <2>;
208 interrupt-controller;
209 clocks = <&cpg CPG_MOD 907>;
210 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
211 resets = <&cpg 907>;
212 };
213
214 gpio6: gpio@e6055400 {
215 compatible = "renesas,gpio-r8a7745",
216 "renesas,rcar-gen2-gpio";
217 reg = <0 0xe6055400 0 0x50>;
218 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 192 26>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
224 clocks = <&cpg CPG_MOD 905>;
225 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
226 resets = <&cpg 905>;
227 };
228
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]229 pfc: pin-controller@e6060000 {
230 compatible = "renesas,pfc-r8a7745";
231 reg = <0 0xe6060000 0 0x11c>;
232 };
233
234 tpu: pwm@e60f0000 {
235 compatible = "renesas,tpu-r8a7745", "renesas,tpu";
236 reg = <0 0xe60f0000 0 0x148>;
237 clocks = <&cpg CPG_MOD 304>;
238 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
239 resets = <&cpg 304>;
240 #pwm-cells = <3>;
241 status = "disabled";
242 };
243
244 cpg: clock-controller@e6150000 {
245 compatible = "renesas,r8a7745-cpg-mssr";
246 reg = <0 0xe6150000 0 0x1000>;
247 clocks = <&extal_clk>, <&usb_extal_clk>;
248 clock-names = "extal", "usb_extal";
249 #clock-cells = <2>;
250 #power-domain-cells = <0>;
251 #reset-cells = <1>;
252 };
253
254 apmu@e6151000 {
255 compatible = "renesas,r8a7745-apmu", "renesas,apmu";
256 reg = <0 0xe6151000 0 0x188>;
257 cpus = <&cpu0 &cpu1>;
258 };
259
260 rst: reset-controller@e6160000 {
261 compatible = "renesas,r8a7745-rst";
262 reg = <0 0xe6160000 0 0x100>;
263 };
264
265 sysc: system-controller@e6180000 {
266 compatible = "renesas,r8a7745-sysc";
267 reg = <0 0xe6180000 0 0x200>;
268 #power-domain-cells = <1>;
269 };
270
Sergei Shtylyov28c43fb2016-11-05 00:59:37 +0300[diff] [blame]271 irqc: interrupt-controller@e61c0000 {
272 compatible = "renesas,irqc-r8a7745", "renesas,irqc";
273 #interrupt-cells = <2>;
274 interrupt-controller;
275 reg = <0 0xe61c0000 0 0x200>;
276 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cpg CPG_MOD 407>;
287 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]288 resets = <&cpg 407>;
Sergei Shtylyov28c43fb2016-11-05 00:59:37 +0300[diff] [blame]289 };
290
Biju Das0dcba3d2018-01-24 15:42:02 +0000[diff] [blame]291 ipmmu_sy0: mmu@e6280000 {
292 compatible = "renesas,ipmmu-r8a7745",
293 "renesas,ipmmu-vmsa";
294 reg = <0 0xe6280000 0 0x1000>;
295 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
297 #iommu-cells = <1>;
298 status = "disabled";
299 };
300
301 ipmmu_sy1: mmu@e6290000 {
302 compatible = "renesas,ipmmu-r8a7745",
303 "renesas,ipmmu-vmsa";
304 reg = <0 0xe6290000 0 0x1000>;
305 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
306 #iommu-cells = <1>;
307 status = "disabled";
308 };
309
310 ipmmu_ds: mmu@e6740000 {
311 compatible = "renesas,ipmmu-r8a7745",
312 "renesas,ipmmu-vmsa";
313 reg = <0 0xe6740000 0 0x1000>;
314 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
316 #iommu-cells = <1>;
317 status = "disabled";
318 };
319
320 ipmmu_mp: mmu@ec680000 {
321 compatible = "renesas,ipmmu-r8a7745",
322 "renesas,ipmmu-vmsa";
323 reg = <0 0xec680000 0 0x1000>;
324 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
325 #iommu-cells = <1>;
326 status = "disabled";
327 };
328
329 ipmmu_mx: mmu@fe951000 {
330 compatible = "renesas,ipmmu-r8a7745",
331 "renesas,ipmmu-vmsa";
332 reg = <0 0xfe951000 0 0x1000>;
333 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
335 #iommu-cells = <1>;
336 status = "disabled";
337 };
338
339 ipmmu_gp: mmu@e62a0000 {
340 compatible = "renesas,ipmmu-r8a7745",
341 "renesas,ipmmu-vmsa";
342 reg = <0 0xe62a0000 0 0x1000>;
343 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
345 #iommu-cells = <1>;
346 status = "disabled";
347 };
348
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]349 icram0: sram@e63a0000 {
350 compatible = "mmio-sram";
351 reg = <0 0xe63a0000 0 0x12000>;
352 };
353
354 icram1: sram@e63c0000 {
355 compatible = "mmio-sram";
356 reg = <0 0xe63c0000 0 0x1000>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges = <0 0 0xe63c0000 0x1000>;
360
361 smp-sram@0 {
362 compatible = "renesas,smp-sram";
Fabrizio Castro7270ded2018-02-12 17:44:12 +0000[diff] [blame^]363 reg = <0 0x100>;
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]364 };
365 };
366
367 icram2: sram@e6300000 {
368 compatible = "mmio-sram";
369 reg = <0 0xe6300000 0 0x40000>;
370 };
371 i2c0: i2c@e6508000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "renesas,i2c-r8a7745",
375 "renesas,rcar-gen2-i2c";
376 reg = <0 0xe6508000 0 0x40>;
377 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&cpg CPG_MOD 931>;
Fabrizio Castro9680c972017-12-18 17:39:03 +0000[diff] [blame]379 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]380 resets = <&cpg 931>;
381 i2c-scl-internal-delay-ns = <6>;
Fabrizio Castro9680c972017-12-18 17:39:03 +0000[diff] [blame]382 status = "disabled";
383 };
384
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]385 i2c1: i2c@e6518000 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "renesas,i2c-r8a7745",
389 "renesas,rcar-gen2-i2c";
390 reg = <0 0xe6518000 0 0x40>;
391 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cpg CPG_MOD 930>;
Fabrizio Castro9680c972017-12-18 17:39:03 +0000[diff] [blame]393 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]394 resets = <&cpg 930>;
395 i2c-scl-internal-delay-ns = <6>;
Fabrizio Castro9680c972017-12-18 17:39:03 +0000[diff] [blame]396 status = "disabled";
397 };
398
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]399 i2c2: i2c@e6530000 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "renesas,i2c-r8a7745",
403 "renesas,rcar-gen2-i2c";
404 reg = <0 0xe6530000 0 0x40>;
405 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cpg CPG_MOD 929>;
407 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
408 resets = <&cpg 929>;
409 i2c-scl-internal-delay-ns = <6>;
410 status = "disabled";
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]411 };
412
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]413 i2c3: i2c@e6540000 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "renesas,i2c-r8a7745",
417 "renesas,rcar-gen2-i2c";
418 reg = <0 0xe6540000 0 0x40>;
419 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cpg CPG_MOD 928>;
421 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
422 resets = <&cpg 928>;
423 i2c-scl-internal-delay-ns = <6>;
424 status = "disabled";
Geert Uytterhoeven8916c7b2016-11-18 11:37:43 +0100[diff] [blame]425 };
426
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]427 i2c4: i2c@e6520000 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "renesas,i2c-r8a7745",
431 "renesas,rcar-gen2-i2c";
432 reg = <0 0xe6520000 0 0x40>;
433 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&cpg CPG_MOD 927>;
435 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
436 resets = <&cpg 927>;
437 i2c-scl-internal-delay-ns = <6>;
438 status = "disabled";
Geert Uytterhoeven13ae6ac2016-11-18 11:24:23 +0100[diff] [blame]439 };
440
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]441 i2c5: i2c@e6528000 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "renesas,i2c-r8a7745",
445 "renesas,rcar-gen2-i2c";
446 reg = <0 0xe6528000 0 0x40>;
447 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cpg CPG_MOD 925>;
449 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
450 resets = <&cpg 925>;
451 i2c-scl-internal-delay-ns = <6>;
452 status = "disabled";
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]453 };
454
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]455 iic0: i2c@e6500000 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 compatible = "renesas,iic-r8a7745",
459 "renesas,rcar-gen2-iic",
460 "renesas,rmobile-iic";
461 reg = <0 0xe6500000 0 0x425>;
462 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cpg CPG_MOD 318>;
464 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
465 <&dmac1 0x61>, <&dmac1 0x62>;
466 dma-names = "tx", "rx", "tx", "rx";
467 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
468 resets = <&cpg 318>;
469 status = "disabled";
470 };
471
472 iic1: i2c@e6510000 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "renesas,iic-r8a7745",
476 "renesas,rcar-gen2-iic",
477 "renesas,rmobile-iic";
478 reg = <0 0xe6510000 0 0x425>;
479 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&cpg CPG_MOD 323>;
481 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
482 <&dmac1 0x65>, <&dmac1 0x66>;
483 dma-names = "tx", "rx", "tx", "rx";
484 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
485 resets = <&cpg 323>;
486 status = "disabled";
487 };
488
489 hsusb: usb@e6590000 {
490 compatible = "renesas,usbhs-r8a7745",
491 "renesas,rcar-gen2-usbhs";
492 reg = <0 0xe6590000 0 0x100>;
493 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 704>;
495 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
496 <&usb_dmac1 0>, <&usb_dmac1 1>;
497 dma-names = "ch0", "ch1", "ch2", "ch3";
498 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
499 resets = <&cpg 704>;
500 renesas,buswait = <4>;
501 phys = <&usb0 1>;
502 phy-names = "usb";
503 status = "disabled";
504 };
505
506 usbphy: usb-phy@e6590100 {
507 compatible = "renesas,usb-phy-r8a7745",
508 "renesas,rcar-gen2-usb-phy";
509 reg = <0 0xe6590100 0 0x100>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 clocks = <&cpg CPG_MOD 704>;
513 clock-names = "usbhs";
514 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
515 resets = <&cpg 704>;
516 status = "disabled";
517
518 usb0: usb-channel@0 {
519 reg = <0>;
520 #phy-cells = <1>;
521 };
522 usb2: usb-channel@2 {
523 reg = <2>;
524 #phy-cells = <1>;
525 };
526 };
527
528 usb_dmac0: dma-controller@e65a0000 {
529 compatible = "renesas,r8a7745-usb-dmac",
530 "renesas,usb-dmac";
531 reg = <0 0xe65a0000 0 0x100>;
532 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
533 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-names = "ch0", "ch1";
535 clocks = <&cpg CPG_MOD 330>;
536 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
537 resets = <&cpg 330>;
538 #dma-cells = <1>;
539 dma-channels = <2>;
540 };
541
542 usb_dmac1: dma-controller@e65b0000 {
543 compatible = "renesas,r8a7745-usb-dmac",
544 "renesas,usb-dmac";
545 reg = <0 0xe65b0000 0 0x100>;
546 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
547 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "ch0", "ch1";
549 clocks = <&cpg CPG_MOD 331>;
550 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
551 resets = <&cpg 331>;
552 #dma-cells = <1>;
553 dma-channels = <2>;
Sergei Shtylyov95b94ed2017-04-15 23:18:26 +0300[diff] [blame]554 };
555
Sergei Shtylyov06a80ba2016-11-05 00:54:51 +0300[diff] [blame]556 dmac0: dma-controller@e6700000 {
557 compatible = "renesas,dmac-r8a7745",
558 "renesas,rcar-dmac";
559 reg = <0 0xe6700000 0 0x20000>;
560 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
561 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
562 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
563 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
564 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
565 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
566 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
567 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
568 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
569 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
570 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
571 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
572 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
573 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
574 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
575 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-names = "error",
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]577 "ch0", "ch1", "ch2", "ch3",
578 "ch4", "ch5", "ch6", "ch7",
579 "ch8", "ch9", "ch10", "ch11",
580 "ch12", "ch13", "ch14";
Sergei Shtylyov06a80ba2016-11-05 00:54:51 +0300[diff] [blame]581 clocks = <&cpg CPG_MOD 219>;
582 clock-names = "fck";
583 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]584 resets = <&cpg 219>;
Sergei Shtylyov06a80ba2016-11-05 00:54:51 +0300[diff] [blame]585 #dma-cells = <1>;
586 dma-channels = <15>;
587 };
588
589 dmac1: dma-controller@e6720000 {
590 compatible = "renesas,dmac-r8a7745",
591 "renesas,rcar-dmac";
592 reg = <0 0xe6720000 0 0x20000>;
593 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
594 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
595 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
596 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
597 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
598 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
599 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
600 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
601 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
602 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
603 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
604 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
605 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
606 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
607 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
608 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
609 interrupt-names = "error",
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]610 "ch0", "ch1", "ch2", "ch3",
611 "ch4", "ch5", "ch6", "ch7",
612 "ch8", "ch9", "ch10", "ch11",
613 "ch12", "ch13", "ch14";
Sergei Shtylyov06a80ba2016-11-05 00:54:51 +0300[diff] [blame]614 clocks = <&cpg CPG_MOD 218>;
615 clock-names = "fck";
616 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]617 resets = <&cpg 218>;
Sergei Shtylyov06a80ba2016-11-05 00:54:51 +0300[diff] [blame]618 #dma-cells = <1>;
619 dma-channels = <15>;
620 };
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]621
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]622 avb: ethernet@e6800000 {
623 compatible = "renesas,etheravb-r8a7745",
624 "renesas,etheravb-rcar-gen2";
625 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
626 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cpg CPG_MOD 812>;
Biju Dasa14a05c2017-12-20 20:01:58 +0000[diff] [blame]628 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]629 resets = <&cpg 812>;
630 #address-cells = <1>;
631 #size-cells = <0>;
632 status = "disabled";
Biju Dasa14a05c2017-12-20 20:01:58 +0000[diff] [blame]633 };
634
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]635 qspi: spi@e6b10000 {
636 compatible = "renesas,qspi-r8a7745", "renesas,qspi";
637 reg = <0 0xe6b10000 0 0x2c>;
638 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&cpg CPG_MOD 917>;
640 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
641 <&dmac1 0x17>, <&dmac1 0x18>;
642 dma-names = "tx", "rx", "tx", "rx";
Biju Dasfbdf17b2017-10-23 18:09:27 +0100[diff] [blame]643 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]644 num-cs = <1>;
645 #address-cells = <1>;
646 #size-cells = <0>;
647 resets = <&cpg 917>;
648 status = "disabled";
Biju Dasfbdf17b2017-10-23 18:09:27 +0100[diff] [blame]649 };
650
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]651 scifa0: serial@e6c40000 {
652 compatible = "renesas,scifa-r8a7745",
653 "renesas,rcar-gen2-scifa", "renesas,scifa";
654 reg = <0 0xe6c40000 0 0x40>;
655 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&cpg CPG_MOD 204>;
657 clock-names = "fck";
658 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
659 <&dmac1 0x21>, <&dmac1 0x22>;
660 dma-names = "tx", "rx", "tx", "rx";
661 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]662 resets = <&cpg 204>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]663 status = "disabled";
664 };
665
666 scifa1: serial@e6c50000 {
667 compatible = "renesas,scifa-r8a7745",
668 "renesas,rcar-gen2-scifa", "renesas,scifa";
669 reg = <0 0xe6c50000 0 0x40>;
670 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 203>;
672 clock-names = "fck";
673 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
674 <&dmac1 0x25>, <&dmac1 0x26>;
675 dma-names = "tx", "rx", "tx", "rx";
676 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]677 resets = <&cpg 203>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]678 status = "disabled";
679 };
680
681 scifa2: serial@e6c60000 {
682 compatible = "renesas,scifa-r8a7745",
683 "renesas,rcar-gen2-scifa", "renesas,scifa";
684 reg = <0 0xe6c60000 0 0x40>;
685 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&cpg CPG_MOD 202>;
687 clock-names = "fck";
688 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
689 <&dmac1 0x27>, <&dmac1 0x28>;
690 dma-names = "tx", "rx", "tx", "rx";
691 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]692 resets = <&cpg 202>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]693 status = "disabled";
694 };
695
696 scifa3: serial@e6c70000 {
697 compatible = "renesas,scifa-r8a7745",
698 "renesas,rcar-gen2-scifa", "renesas,scifa";
699 reg = <0 0xe6c70000 0 0x40>;
700 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&cpg CPG_MOD 1106>;
702 clock-names = "fck";
703 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
704 <&dmac1 0x1b>, <&dmac1 0x1c>;
705 dma-names = "tx", "rx", "tx", "rx";
706 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]707 resets = <&cpg 1106>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]708 status = "disabled";
709 };
710
711 scifa4: serial@e6c78000 {
712 compatible = "renesas,scifa-r8a7745",
713 "renesas,rcar-gen2-scifa", "renesas,scifa";
714 reg = <0 0xe6c78000 0 0x40>;
715 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&cpg CPG_MOD 1107>;
717 clock-names = "fck";
718 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
719 <&dmac1 0x1f>, <&dmac1 0x20>;
720 dma-names = "tx", "rx", "tx", "rx";
721 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]722 resets = <&cpg 1107>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]723 status = "disabled";
724 };
725
726 scifa5: serial@e6c80000 {
727 compatible = "renesas,scifa-r8a7745",
728 "renesas,rcar-gen2-scifa", "renesas,scifa";
729 reg = <0 0xe6c80000 0 0x40>;
730 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cpg CPG_MOD 1108>;
732 clock-names = "fck";
733 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
734 <&dmac1 0x23>, <&dmac1 0x24>;
735 dma-names = "tx", "rx", "tx", "rx";
736 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]737 resets = <&cpg 1108>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]738 status = "disabled";
739 };
740
741 scifb0: serial@e6c20000 {
742 compatible = "renesas,scifb-r8a7745",
743 "renesas,rcar-gen2-scifb", "renesas,scifb";
744 reg = <0 0xe6c20000 0 0x100>;
745 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&cpg CPG_MOD 206>;
747 clock-names = "fck";
748 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
Geert Uytterhoevenad20bb62017-02-08 19:00:44 +0100[diff] [blame]749 <&dmac1 0x3d>, <&dmac1 0x3e>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]750 dma-names = "tx", "rx", "tx", "rx";
751 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]752 resets = <&cpg 206>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]753 status = "disabled";
754 };
755
756 scifb1: serial@e6c30000 {
757 compatible = "renesas,scifb-r8a7745",
758 "renesas,rcar-gen2-scifb", "renesas,scifb";
759 reg = <0 0xe6c30000 0 0x100>;
760 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&cpg CPG_MOD 207>;
762 clock-names = "fck";
763 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
764 <&dmac1 0x19>, <&dmac1 0x1a>;
765 dma-names = "tx", "rx", "tx", "rx";
766 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]767 resets = <&cpg 207>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]768 status = "disabled";
769 };
770
771 scifb2: serial@e6ce0000 {
772 compatible = "renesas,scifb-r8a7745",
773 "renesas,rcar-gen2-scifb", "renesas,scifb";
774 reg = <0 0xe6ce0000 0 0x100>;
775 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&cpg CPG_MOD 216>;
777 clock-names = "fck";
778 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
779 <&dmac1 0x1d>, <&dmac1 0x1e>;
780 dma-names = "tx", "rx", "tx", "rx";
781 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]782 resets = <&cpg 216>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]783 status = "disabled";
784 };
785
786 scif0: serial@e6e60000 {
787 compatible = "renesas,scif-r8a7745",
788 "renesas,rcar-gen2-scif", "renesas,scif";
789 reg = <0 0xe6e60000 0 0x40>;
790 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 721>,
792 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
793 clock-names = "fck", "brg_int", "scif_clk";
794 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
795 <&dmac1 0x29>, <&dmac1 0x2a>;
796 dma-names = "tx", "rx", "tx", "rx";
797 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]798 resets = <&cpg 721>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]799 status = "disabled";
800 };
801
802 scif1: serial@e6e68000 {
803 compatible = "renesas,scif-r8a7745",
804 "renesas,rcar-gen2-scif", "renesas,scif";
805 reg = <0 0xe6e68000 0 0x40>;
806 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&cpg CPG_MOD 720>,
808 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
809 clock-names = "fck", "brg_int", "scif_clk";
810 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
811 <&dmac1 0x2d>, <&dmac1 0x2e>;
812 dma-names = "tx", "rx", "tx", "rx";
813 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]814 resets = <&cpg 720>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]815 status = "disabled";
816 };
817
818 scif2: serial@e6e58000 {
819 compatible = "renesas,scif-r8a7745",
820 "renesas,rcar-gen2-scif", "renesas,scif";
821 reg = <0 0xe6e58000 0 0x40>;
822 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&cpg CPG_MOD 719>,
824 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
825 clock-names = "fck", "brg_int", "scif_clk";
826 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
827 <&dmac1 0x2b>, <&dmac1 0x2c>;
828 dma-names = "tx", "rx", "tx", "rx";
829 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]830 resets = <&cpg 719>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]831 status = "disabled";
832 };
833
834 scif3: serial@e6ea8000 {
835 compatible = "renesas,scif-r8a7745",
836 "renesas,rcar-gen2-scif", "renesas,scif";
837 reg = <0 0xe6ea8000 0 0x40>;
838 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&cpg CPG_MOD 718>,
840 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
841 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
843 <&dmac1 0x2f>, <&dmac1 0x30>;
844 dma-names = "tx", "rx", "tx", "rx";
845 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]846 resets = <&cpg 718>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]847 status = "disabled";
848 };
849
850 scif4: serial@e6ee0000 {
851 compatible = "renesas,scif-r8a7745",
852 "renesas,rcar-gen2-scif", "renesas,scif";
853 reg = <0 0xe6ee0000 0 0x40>;
854 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 715>,
856 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
857 clock-names = "fck", "brg_int", "scif_clk";
858 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
859 <&dmac1 0xfb>, <&dmac1 0xfc>;
860 dma-names = "tx", "rx", "tx", "rx";
861 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]862 resets = <&cpg 715>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]863 status = "disabled";
864 };
865
866 scif5: serial@e6ee8000 {
867 compatible = "renesas,scif-r8a7745",
868 "renesas,rcar-gen2-scif", "renesas,scif";
869 reg = <0 0xe6ee8000 0 0x40>;
870 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 714>,
872 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
873 clock-names = "fck", "brg_int", "scif_clk";
874 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
875 <&dmac1 0xfd>, <&dmac1 0xfe>;
876 dma-names = "tx", "rx", "tx", "rx";
877 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]878 resets = <&cpg 714>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]879 status = "disabled";
880 };
881
882 hscif0: serial@e62c0000 {
883 compatible = "renesas,hscif-r8a7745",
884 "renesas,rcar-gen2-hscif", "renesas,hscif";
885 reg = <0 0xe62c0000 0 0x60>;
886 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&cpg CPG_MOD 717>,
888 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
889 clock-names = "fck", "brg_int", "scif_clk";
890 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
891 <&dmac1 0x39>, <&dmac1 0x3a>;
892 dma-names = "tx", "rx", "tx", "rx";
893 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]894 resets = <&cpg 717>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]895 status = "disabled";
896 };
897
898 hscif1: serial@e62c8000 {
899 compatible = "renesas,hscif-r8a7745",
900 "renesas,rcar-gen2-hscif", "renesas,hscif";
901 reg = <0 0xe62c8000 0 0x60>;
902 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&cpg CPG_MOD 716>,
904 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
905 clock-names = "fck", "brg_int", "scif_clk";
906 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
907 <&dmac1 0x4d>, <&dmac1 0x4e>;
908 dma-names = "tx", "rx", "tx", "rx";
909 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]910 resets = <&cpg 716>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]911 status = "disabled";
912 };
913
914 hscif2: serial@e62d0000 {
915 compatible = "renesas,hscif-r8a7745",
916 "renesas,rcar-gen2-hscif", "renesas,hscif";
917 reg = <0 0xe62d0000 0 0x60>;
918 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&cpg CPG_MOD 713>,
920 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
921 clock-names = "fck", "brg_int", "scif_clk";
922 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
923 <&dmac1 0x3b>, <&dmac1 0x3c>;
924 dma-names = "tx", "rx", "tx", "rx";
925 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
Geert Uytterhoeven1efab6e2017-03-16 15:07:26 +0100[diff] [blame]926 resets = <&cpg 713>;
Sergei Shtylyove0d2da52016-11-05 00:55:52 +0300[diff] [blame]927 status = "disabled";
928 };
Sergei Shtylyovbed98a52016-11-04 14:57:01 -0700[diff] [blame]929
Fabrizio Castroe5276492017-09-27 10:57:05 +0100[diff] [blame]930 msiof0: spi@e6e20000 {
931 compatible = "renesas,msiof-r8a7745",
932 "renesas,rcar-gen2-msiof";
933 reg = <0 0xe6e20000 0 0x0064>;
934 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&cpg CPG_MOD 000>;
936 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
937 <&dmac1 0x51>, <&dmac1 0x52>;
938 dma-names = "tx", "rx", "tx", "rx";
939 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
940 #address-cells = <1>;
941 #size-cells = <0>;
942 resets = <&cpg 000>;
943 status = "disabled";
944 };
945
946 msiof1: spi@e6e10000 {
947 compatible = "renesas,msiof-r8a7745",
948 "renesas,rcar-gen2-msiof";
949 reg = <0 0xe6e10000 0 0x0064>;
950 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
951 clocks = <&cpg CPG_MOD 208>;
952 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
953 <&dmac1 0x55>, <&dmac1 0x56>;
954 dma-names = "tx", "rx", "tx", "rx";
955 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
956 #address-cells = <1>;
957 #size-cells = <0>;
958 resets = <&cpg 208>;
959 status = "disabled";
960 };
961
962 msiof2: spi@e6e00000 {
963 compatible = "renesas,msiof-r8a7745",
964 "renesas,rcar-gen2-msiof";
965 reg = <0 0xe6e00000 0 0x0064>;
966 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&cpg CPG_MOD 205>;
968 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
969 <&dmac1 0x41>, <&dmac1 0x42>;
970 dma-names = "tx", "rx", "tx", "rx";
971 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
972 #address-cells = <1>;
973 #size-cells = <0>;
974 resets = <&cpg 205>;
975 status = "disabled";
976 };
977
Fabrizio Castro3711d0e2017-12-18 18:06:49 +0000[diff] [blame]978 pwm0: pwm@e6e30000 {
979 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
980 reg = <0 0xe6e30000 0 0x8>;
981 clocks = <&cpg CPG_MOD 523>;
982 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
983 resets = <&cpg 523>;
984 #pwm-cells = <2>;
985 status = "disabled";
986 };
987
988 pwm1: pwm@e6e31000 {
989 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
990 reg = <0 0xe6e31000 0 0x8>;
991 clocks = <&cpg CPG_MOD 523>;
992 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
993 resets = <&cpg 523>;
994 #pwm-cells = <2>;
995 status = "disabled";
996 };
997
998 pwm2: pwm@e6e32000 {
999 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1000 reg = <0 0xe6e32000 0 0x8>;
1001 clocks = <&cpg CPG_MOD 523>;
1002 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1003 resets = <&cpg 523>;
1004 #pwm-cells = <2>;
1005 status = "disabled";
1006 };
1007
1008 pwm3: pwm@e6e33000 {
1009 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1010 reg = <0 0xe6e33000 0 0x8>;
1011 clocks = <&cpg CPG_MOD 523>;
1012 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1013 resets = <&cpg 523>;
1014 #pwm-cells = <2>;
1015 status = "disabled";
1016 };
1017
1018 pwm4: pwm@e6e34000 {
1019 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1020 reg = <0 0xe6e34000 0 0x8>;
1021 clocks = <&cpg CPG_MOD 523>;
1022 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1023 resets = <&cpg 523>;
1024 #pwm-cells = <2>;
1025 status = "disabled";
1026 };
1027
1028 pwm5: pwm@e6e35000 {
1029 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1030 reg = <0 0xe6e35000 0 0x8>;
1031 clocks = <&cpg CPG_MOD 523>;
1032 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1033 resets = <&cpg 523>;
1034 #pwm-cells = <2>;
1035 status = "disabled";
1036 };
1037
1038 pwm6: pwm@e6e36000 {
1039 compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1040 reg = <0 0xe6e36000 0 0x8>;
1041 clocks = <&cpg CPG_MOD 523>;
1042 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1043 resets = <&cpg 523>;
1044 #pwm-cells = <2>;
1045 status = "disabled";
1046 };
1047
Fabrizio Castro85d31222017-11-07 15:10:44 +0000[diff] [blame]1048 can0: can@e6e80000 {
1049 compatible = "renesas,can-r8a7745",
1050 "renesas,rcar-gen2-can";
1051 reg = <0 0xe6e80000 0 0x1000>;
1052 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&cpg CPG_MOD 916>,
1054 <&cpg CPG_CORE R8A7745_CLK_RCAN>,
1055 <&can_clk>;
1056 clock-names = "clkp1", "clkp2", "can_clk";
1057 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1058 resets = <&cpg 916>;
1059 status = "disabled";
1060 };
1061
1062 can1: can@e6e88000 {
1063 compatible = "renesas,can-r8a7745",
1064 "renesas,rcar-gen2-can";
1065 reg = <0 0xe6e88000 0 0x1000>;
1066 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&cpg CPG_MOD 915>,
1068 <&cpg CPG_CORE R8A7745_CLK_RCAN>,
1069 <&can_clk>;
1070 clock-names = "clkp1", "clkp2", "can_clk";
1071 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1072 resets = <&cpg 915>;
1073 status = "disabled";
1074 };
Biju Das17d2e472017-12-20 20:01:59 +0000[diff] [blame]1075
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]1076 vin0: video@e6ef0000 {
1077 compatible = "renesas,vin-r8a7745",
1078 "renesas,rcar-gen2-vin";
1079 reg = <0 0xe6ef0000 0 0x1000>;
1080 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MOD 811>;
1082 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1083 resets = <&cpg 811>;
1084 status = "disabled";
1085 };
1086
1087 vin1: video@e6ef1000 {
1088 compatible = "renesas,vin-r8a7745",
1089 "renesas,rcar-gen2-vin";
1090 reg = <0 0xe6ef1000 0 0x1000>;
1091 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&cpg CPG_MOD 810>;
1093 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1094 resets = <&cpg 810>;
1095 status = "disabled";
1096 };
1097
Biju Das17d2e472017-12-20 20:01:59 +0000[diff] [blame]1098 rcar_sound: sound@ec500000 {
1099 /*
1100 * #sound-dai-cells is required
1101 *
1102 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1103 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1104 */
1105 compatible = "renesas,rcar_sound-r8a7745",
1106 "renesas,rcar_sound-gen2";
1107 reg = <0 0xec500000 0 0x1000>, /* SCU */
1108 <0 0xec5a0000 0 0x100>, /* ADG */
1109 <0 0xec540000 0 0x1000>, /* SSIU */
1110 <0 0xec541000 0 0x280>, /* SSI */
1111 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
1112 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1113
1114 clocks = <&cpg CPG_MOD 1005>,
1115 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1116 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1117 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1118 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1119 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1120 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
1121 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
1122 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
1123 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1124 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1125 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1126 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1127 <&cpg CPG_CORE R8A7745_CLK_M2>;
1128 clock-names = "ssi-all",
1129 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1130 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1131 "ssi.1", "ssi.0",
1132 "src.6", "src.5", "src.4", "src.3",
1133 "src.2", "src.1",
1134 "ctu.0", "ctu.1",
1135 "mix.0", "mix.1",
1136 "dvc.0", "dvc.1",
1137 "clk_a", "clk_b", "clk_c", "clk_i";
1138 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1139 resets = <&cpg 1005>,
1140 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>,
1141 <&cpg 1009>, <&cpg 1010>, <&cpg 1011>,
1142 <&cpg 1012>, <&cpg 1013>, <&cpg 1014>,
1143 <&cpg 1015>;
1144 reset-names = "ssi-all",
1145 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1146 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1147 "ssi.1", "ssi.0";
1148
1149 status = "disabled";
1150
1151 rcar_sound,dvc {
1152 dvc0: dvc-0 {
1153 dmas = <&audma0 0xbc>;
1154 dma-names = "tx";
1155 };
1156 dvc1: dvc-1 {
1157 dmas = <&audma0 0xbe>;
1158 dma-names = "tx";
1159 };
1160 };
1161
1162 rcar_sound,mix {
1163 mix0: mix-0 { };
1164 mix1: mix-1 { };
1165 };
1166
1167 rcar_sound,ctu {
1168 ctu00: ctu-0 { };
1169 ctu01: ctu-1 { };
1170 ctu02: ctu-2 { };
1171 ctu03: ctu-3 { };
1172 ctu10: ctu-4 { };
1173 ctu11: ctu-5 { };
1174 ctu12: ctu-6 { };
1175 ctu13: ctu-7 { };
1176 };
1177
1178 rcar_sound,src {
1179 src-0 {
1180 status = "disabled";
1181 };
1182 src1: src-1 {
1183 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1184 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1185 dma-names = "rx", "tx";
1186 };
1187 src2: src-2 {
1188 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1189 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1190 dma-names = "rx", "tx";
1191 };
1192 src3: src-3 {
1193 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1194 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1195 dma-names = "rx", "tx";
1196 };
1197 src4: src-4 {
1198 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1199 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1200 dma-names = "rx", "tx";
1201 };
1202 src5: src-5 {
1203 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1204 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1205 dma-names = "rx", "tx";
1206 };
1207 src6: src-6 {
1208 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1209 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1210 dma-names = "rx", "tx";
1211 };
1212 };
1213
1214 rcar_sound,ssi {
1215 ssi0: ssi-0 {
1216 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1217 dmas = <&audma0 0x01>, <&audma0 0x02>,
1218 <&audma0 0x15>, <&audma0 0x16>;
1219 dma-names = "rx", "tx", "rxu", "txu";
1220 };
1221 ssi1: ssi-1 {
1222 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1223 dmas = <&audma0 0x03>, <&audma0 0x04>,
1224 <&audma0 0x49>, <&audma0 0x4a>;
1225 dma-names = "rx", "tx", "rxu", "txu";
1226 };
1227 ssi2: ssi-2 {
1228 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1229 dmas = <&audma0 0x05>, <&audma0 0x06>,
1230 <&audma0 0x63>, <&audma0 0x64>;
1231 dma-names = "rx", "tx", "rxu", "txu";
1232 };
1233 ssi3: ssi-3 {
1234 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1235 dmas = <&audma0 0x07>, <&audma0 0x08>,
1236 <&audma0 0x6f>, <&audma0 0x70>;
1237 dma-names = "rx", "tx", "rxu", "txu";
1238 };
1239 ssi4: ssi-4 {
1240 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1241 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1242 <&audma0 0x71>, <&audma0 0x72>;
1243 dma-names = "rx", "tx", "rxu", "txu";
1244 };
1245 ssi5: ssi-5 {
1246 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1248 <&audma0 0x73>, <&audma0 0x74>;
1249 dma-names = "rx", "tx", "rxu", "txu";
1250 };
1251 ssi6: ssi-6 {
1252 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1253 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1254 <&audma0 0x75>, <&audma0 0x76>;
1255 dma-names = "rx", "tx", "rxu", "txu";
1256 };
1257 ssi7: ssi-7 {
1258 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1259 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1260 <&audma0 0x79>, <&audma0 0x7a>;
1261 dma-names = "rx", "tx", "rxu", "txu";
1262 };
1263 ssi8: ssi-8 {
1264 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1265 dmas = <&audma0 0x11>, <&audma0 0x12>,
1266 <&audma0 0x7b>, <&audma0 0x7c>;
1267 dma-names = "rx", "tx", "rxu", "txu";
1268 };
1269 ssi9: ssi-9 {
1270 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1271 dmas = <&audma0 0x13>, <&audma0 0x14>,
1272 <&audma0 0x7d>, <&audma0 0x7e>;
1273 dma-names = "rx", "tx", "rxu", "txu";
1274 };
1275 };
1276 };
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]1277
1278 audma0: dma-controller@ec700000 {
1279 compatible = "renesas,dmac-r8a7745",
1280 "renesas,rcar-dmac";
1281 reg = <0 0xec700000 0 0x10000>;
1282 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1283 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1284 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1285 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1286 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1287 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1288 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1289 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1290 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1291 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1292 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1293 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1294 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1295 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1296 interrupt-names = "error",
1297 "ch0", "ch1", "ch2", "ch3",
1298 "ch4", "ch5", "ch6", "ch7",
1299 "ch8", "ch9", "ch10", "ch11",
1300 "ch12";
1301 clocks = <&cpg CPG_MOD 502>;
1302 clock-names = "fck";
1303 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1304 resets = <&cpg 502>;
1305 #dma-cells = <1>;
1306 dma-channels = <13>;
1307 };
1308
1309 pci0: pci@ee090000 {
1310 compatible = "renesas,pci-r8a7745",
1311 "renesas,pci-rcar-gen2";
1312 device_type = "pci";
1313 reg = <0 0xee090000 0 0xc00>,
1314 <0 0xee080000 0 0x1100>;
1315 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&cpg CPG_MOD 703>;
1317 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1318 resets = <&cpg 703>;
1319 status = "disabled";
1320
1321 bus-range = <0 0>;
1322 #address-cells = <3>;
1323 #size-cells = <2>;
1324 #interrupt-cells = <1>;
1325 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1326 interrupt-map-mask = <0xff00 0 0 0x7>;
1327 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1328 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1329 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1330
1331 usb@1,0 {
1332 reg = <0x800 0 0 0 0>;
1333 phys = <&usb0 0>;
1334 phy-names = "usb";
1335 };
1336
1337 usb@2,0 {
1338 reg = <0x1000 0 0 0 0>;
1339 phys = <&usb0 0>;
1340 phy-names = "usb";
1341 };
1342 };
1343
1344 pci1: pci@ee0d0000 {
1345 compatible = "renesas,pci-r8a7745",
1346 "renesas,pci-rcar-gen2";
1347 device_type = "pci";
1348 reg = <0 0xee0d0000 0 0xc00>,
1349 <0 0xee0c0000 0 0x1100>;
1350 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1351 clocks = <&cpg CPG_MOD 703>;
1352 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1353 resets = <&cpg 703>;
1354 status = "disabled";
1355
1356 bus-range = <1 1>;
1357 #address-cells = <3>;
1358 #size-cells = <2>;
1359 #interrupt-cells = <1>;
1360 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1361 interrupt-map-mask = <0xff00 0 0 0x7>;
1362 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1363 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1364 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1365
1366 usb@1,0 {
1367 reg = <0x10800 0 0 0 0>;
1368 phys = <&usb2 0>;
1369 phy-names = "usb";
1370 };
1371
1372 usb@2,0 {
1373 reg = <0x11000 0 0 0 0>;
1374 phys = <&usb2 0>;
1375 phy-names = "usb";
1376 };
1377 };
1378
1379 sdhi0: sd@ee100000 {
1380 compatible = "renesas,sdhi-r8a7745",
1381 "renesas,rcar-gen2-sdhi";
1382 reg = <0 0xee100000 0 0x328>;
1383 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1384 clocks = <&cpg CPG_MOD 314>;
1385 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1386 <&dmac1 0xcd>, <&dmac1 0xce>;
1387 dma-names = "tx", "rx", "tx", "rx";
1388 max-frequency = <195000000>;
1389 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1390 resets = <&cpg 314>;
1391 status = "disabled";
1392 };
1393
1394 sdhi1: sd@ee140000 {
1395 compatible = "renesas,sdhi-r8a7745",
1396 "renesas,rcar-gen2-sdhi";
1397 reg = <0 0xee140000 0 0x100>;
1398 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1399 clocks = <&cpg CPG_MOD 312>;
1400 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1401 <&dmac1 0xc1>, <&dmac1 0xc2>;
1402 dma-names = "tx", "rx", "tx", "rx";
1403 max-frequency = <97500000>;
1404 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1405 resets = <&cpg 312>;
1406 status = "disabled";
1407 };
1408
1409 sdhi2: sd@ee160000 {
1410 compatible = "renesas,sdhi-r8a7745",
1411 "renesas,rcar-gen2-sdhi";
1412 reg = <0 0xee160000 0 0x100>;
1413 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1414 clocks = <&cpg CPG_MOD 311>;
1415 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1416 <&dmac1 0xd3>, <&dmac1 0xd4>;
1417 dma-names = "tx", "rx", "tx", "rx";
1418 max-frequency = <97500000>;
1419 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1420 resets = <&cpg 311>;
1421 status = "disabled";
1422 };
1423
1424 mmcif0: mmc@ee200000 {
1425 compatible = "renesas,mmcif-r8a7745",
1426 "renesas,sh-mmcif";
1427 reg = <0 0xee200000 0 0x80>;
1428 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MOD 315>;
1430 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1431 <&dmac1 0xd1>, <&dmac1 0xd2>;
1432 dma-names = "tx", "rx", "tx", "rx";
1433 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1434 resets = <&cpg 315>;
1435 reg-io-width = <4>;
1436 max-frequency = <97500000>;
1437 status = "disabled";
1438 };
1439
1440 ether: ethernet@ee700000 {
1441 compatible = "renesas,ether-r8a7745",
1442 "renesas,rcar-gen2-ether";
1443 reg = <0 0xee700000 0 0x400>;
1444 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1445 clocks = <&cpg CPG_MOD 813>;
1446 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1447 resets = <&cpg 813>;
1448 phy-mode = "rmii";
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 status = "disabled";
1452 };
1453
1454 gic: interrupt-controller@f1001000 {
1455 compatible = "arm,gic-400";
1456 #interrupt-cells = <3>;
1457 #address-cells = <0>;
1458 interrupt-controller;
1459 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1460 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1461 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1462 clocks = <&cpg CPG_MOD 408>;
1463 clock-names = "clk";
1464 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1465 resets = <&cpg 408>;
1466 };
1467
Biju Das76a25772018-01-24 16:11:52 +0000[diff] [blame]1468 vsp@fe928000 {
1469 compatible = "renesas,vsp1";
1470 reg = <0 0xfe928000 0 0x8000>;
1471 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&cpg CPG_MOD 131>;
1473 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1474 resets = <&cpg 131>;
1475 };
1476
1477 vsp@fe930000 {
1478 compatible = "renesas,vsp1";
1479 reg = <0 0xfe930000 0 0x8000>;
1480 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cpg CPG_MOD 128>;
1482 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1483 resets = <&cpg 128>;
1484 };
1485
Simon Horman28c07002018-01-26 10:40:52 +0100[diff] [blame]1486 du: display@feb00000 {
1487 compatible = "renesas,du-r8a7745";
1488 reg = <0 0xfeb00000 0 0x40000>;
1489 reg-names = "du";
1490 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1492 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1493 clock-names = "du.0", "du.1";
1494 status = "disabled";
1495
1496 ports {
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1499
1500 port@0 {
1501 reg = <0>;
1502 du_out_rgb0: endpoint {
1503 };
1504 };
1505 port@1 {
1506 reg = <1>;
1507 du_out_rgb1: endpoint {
1508 };
1509 };
1510 };
1511 };
1512
1513 prr: chipid@ff000044 {
1514 compatible = "renesas,prr";
1515 reg = <0 0xff000044 0 4>;
1516 };
1517
1518 cmt0: timer@ffca0000 {
1519 compatible = "renesas,r8a7745-cmt0",
1520 "renesas,rcar-gen2-cmt0";
1521 reg = <0 0xffca0000 0 0x1004>;
1522 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1524 clocks = <&cpg CPG_MOD 124>;
1525 clock-names = "fck";
1526 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1527 resets = <&cpg 124>;
1528 status = "disabled";
1529 };
1530
1531 cmt1: timer@e6130000 {
1532 compatible = "renesas,r8a7745-cmt1",
1533 "renesas,rcar-gen2-cmt1";
1534 reg = <0 0xe6130000 0 0x1004>;
1535 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1543 clocks = <&cpg CPG_MOD 329>;
1544 clock-names = "fck";
1545 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1546 resets = <&cpg 329>;
1547 status = "disabled";
1548 };
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]1549 };
1550
Simon Horman7bee3792017-12-18 22:46:57 +0100[diff] [blame]1551 timer {
1552 compatible = "arm,armv7-timer";
1553 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1554 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1555 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1556 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1557 };
1558
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]1559 /* External USB clock - can be overridden by the board */
1560 usb_extal_clk: usb_extal {
1561 compatible = "fixed-clock";
1562 #clock-cells = <0>;
1563 clock-frequency = <48000000>;
1564 };
Sergei Shtylyovc9536022016-11-05 00:53:38 +0300[diff] [blame]1565};