Sean Wang | e3fd24a | 2017-12-12 14:24:19 +0800 | [diff] [blame] | 1 | menu "MediaTek pinctrl drivers" |
| 2 | depends on ARCH_MEDIATEK || COMPILE_TEST |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 3 | |
Sean Wang | e46df23 | 2018-05-21 01:01:48 +0800 | [diff] [blame] | 4 | config EINT_MTK |
| 5 | bool "MediaTek External Interrupt Support" |
Sean Wang | e78d57b | 2018-09-08 19:07:18 +0800 | [diff] [blame] | 6 | depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST |
Arnd Bergmann | 71a9d39 | 2018-10-08 17:57:43 +0200 | [diff] [blame^] | 7 | select GPIOLIB |
Sean Wang | e46df23 | 2018-05-21 01:01:48 +0800 | [diff] [blame] | 8 | select IRQ_DOMAIN |
| 9 | |
Masahiro Yamada | 4a9e006 | 2016-02-10 18:54:32 +0900 | [diff] [blame] | 10 | config PINCTRL_MTK |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 11 | bool |
Linus Walleij | b99e6fb | 2015-04-15 10:00:35 +0200 | [diff] [blame] | 12 | depends on OF |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 13 | select PINMUX |
| 14 | select GENERIC_PINCONF |
| 15 | select GPIOLIB |
Sean Wang | e46df23 | 2018-05-21 01:01:48 +0800 | [diff] [blame] | 16 | select EINT_MTK |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 17 | select OF_GPIO |
| 18 | |
Sean Wang | e78d57b | 2018-09-08 19:07:18 +0800 | [diff] [blame] | 19 | config PINCTRL_MTK_MOORE |
| 20 | bool "MediaTek Moore Core that implements generic binding" |
| 21 | depends on OF |
| 22 | select GENERIC_PINCONF |
| 23 | select GENERIC_PINCTRL_GROUPS |
| 24 | select GENERIC_PINMUX_FUNCTIONS |
| 25 | select GPIOLIB |
| 26 | select OF_GPIO |
| 27 | |
Zhiyong Tao | 8052509 | 2018-09-08 19:07:33 +0800 | [diff] [blame] | 28 | config PINCTRL_MTK_PARIS |
| 29 | bool "MediaTek Paris Core that implements vendor binding" |
| 30 | depends on OF |
| 31 | select PINMUX |
| 32 | select GENERIC_PINCONF |
| 33 | select GPIOLIB |
| 34 | select EINT_MTK |
| 35 | select OF_GPIO |
| 36 | |
Yingjoe Chen | 4a8ade1 | 2015-03-13 22:40:52 +0800 | [diff] [blame] | 37 | # For ARMv7 SoCs |
Biao Huang | 148b95e | 2016-01-27 09:24:42 +0800 | [diff] [blame] | 38 | config PINCTRL_MT2701 |
Jean Delvare | 79d6208 | 2017-01-25 10:32:09 +0100 | [diff] [blame] | 39 | bool "Mediatek MT2701 pin control" |
Sean Wang | ceba438 | 2017-05-01 15:54:34 +0800 | [diff] [blame] | 40 | depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST |
Biao Huang | 148b95e | 2016-01-27 09:24:42 +0800 | [diff] [blame] | 41 | depends on OF |
| 42 | default MACH_MT2701 |
Masahiro Yamada | 4a9e006 | 2016-02-10 18:54:32 +0900 | [diff] [blame] | 43 | select PINCTRL_MTK |
Biao Huang | 148b95e | 2016-01-27 09:24:42 +0800 | [diff] [blame] | 44 | |
Sean Wang | e7507f5 | 2018-09-08 19:07:28 +0800 | [diff] [blame] | 45 | config PINCTRL_MT7623 |
| 46 | bool "Mediatek MT7623 pin control with generic binding" |
| 47 | depends on MACH_MT7623 || COMPILE_TEST |
| 48 | depends on PINCTRL_MTK_MOORE |
| 49 | default y |
| 50 | |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 51 | config PINCTRL_MT8135 |
Jean Delvare | 79d6208 | 2017-01-25 10:32:09 +0100 | [diff] [blame] | 52 | bool "Mediatek MT8135 pin control" |
| 53 | depends on MACH_MT8135 || COMPILE_TEST |
Linus Walleij | b99e6fb | 2015-04-15 10:00:35 +0200 | [diff] [blame] | 54 | depends on OF |
Yingjoe Chen | 4a8ade1 | 2015-03-13 22:40:52 +0800 | [diff] [blame] | 55 | default MACH_MT8135 |
Masahiro Yamada | 4a9e006 | 2016-02-10 18:54:32 +0900 | [diff] [blame] | 56 | select PINCTRL_MTK |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 57 | |
Yingjoe Chen | 6acdee8 | 2015-05-18 20:01:32 -0700 | [diff] [blame] | 58 | config PINCTRL_MT8127 |
Jean Delvare | 79d6208 | 2017-01-25 10:32:09 +0100 | [diff] [blame] | 59 | bool "Mediatek MT8127 pin control" |
| 60 | depends on MACH_MT8127 || COMPILE_TEST |
Yingjoe Chen | 6acdee8 | 2015-05-18 20:01:32 -0700 | [diff] [blame] | 61 | depends on OF |
| 62 | default MACH_MT8127 |
Masahiro Yamada | 4a9e006 | 2016-02-10 18:54:32 +0900 | [diff] [blame] | 63 | select PINCTRL_MTK |
Yingjoe Chen | 6acdee8 | 2015-05-18 20:01:32 -0700 | [diff] [blame] | 64 | |
Yingjoe Chen | 4a8ade1 | 2015-03-13 22:40:52 +0800 | [diff] [blame] | 65 | # For ARMv8 SoCs |
Zhiyong Tao | 8670710 | 2018-03-22 10:58:41 +0800 | [diff] [blame] | 66 | config PINCTRL_MT2712 |
| 67 | bool "MediaTek MT2712 pin control" |
| 68 | depends on OF |
| 69 | depends on ARM64 || COMPILE_TEST |
| 70 | default ARM64 && ARCH_MEDIATEK |
| 71 | select PINCTRL_MTK |
| 72 | |
ZH Chen | 477fece | 2018-09-21 12:07:37 +0800 | [diff] [blame] | 73 | config PINCTRL_MT6765 |
| 74 | bool "Mediatek MT6765 pin control" |
| 75 | depends on OF |
| 76 | depends on ARM64 || COMPILE_TEST |
| 77 | default ARM64 && ARCH_MEDIATEK |
| 78 | select PINCTRL_MTK_PARIS |
| 79 | |
Sean Wang | d6ed935 | 2017-12-12 14:24:20 +0800 | [diff] [blame] | 80 | config PINCTRL_MT7622 |
| 81 | bool "MediaTek MT7622 pin control" |
Sean Wang | d6ed935 | 2017-12-12 14:24:20 +0800 | [diff] [blame] | 82 | depends on ARM64 || COMPILE_TEST |
Sean Wang | e78d57b | 2018-09-08 19:07:18 +0800 | [diff] [blame] | 83 | depends on PINCTRL_MTK_MOORE |
| 84 | default y |
Sean Wang | d6ed935 | 2017-12-12 14:24:20 +0800 | [diff] [blame] | 85 | |
Hongzhou Yang | 30f010f | 2015-01-27 15:13:55 +0800 | [diff] [blame] | 86 | config PINCTRL_MT8173 |
Yingjoe Chen | 4a8ade1 | 2015-03-13 22:40:52 +0800 | [diff] [blame] | 87 | bool "Mediatek MT8173 pin control" |
Linus Walleij | b99e6fb | 2015-04-15 10:00:35 +0200 | [diff] [blame] | 88 | depends on OF |
Yingjoe Chen | 4a8ade1 | 2015-03-13 22:40:52 +0800 | [diff] [blame] | 89 | depends on ARM64 || COMPILE_TEST |
| 90 | default ARM64 && ARCH_MEDIATEK |
Masahiro Yamada | 4a9e006 | 2016-02-10 18:54:32 +0900 | [diff] [blame] | 91 | select PINCTRL_MTK |
Hongzhou Yang | 30f010f | 2015-01-27 15:13:55 +0800 | [diff] [blame] | 92 | |
Zhiyong Tao | 750cd15 | 2018-09-08 19:07:34 +0800 | [diff] [blame] | 93 | config PINCTRL_MT8183 |
| 94 | bool "Mediatek MT8183 pin control" |
| 95 | depends on OF |
| 96 | depends on ARM64 || COMPILE_TEST |
| 97 | default ARM64 && ARCH_MEDIATEK |
| 98 | select PINCTRL_MTK_PARIS |
| 99 | |
Hongzhou Yang | fc59e66 | 2015-05-18 23:11:17 -0700 | [diff] [blame] | 100 | # For PMIC |
| 101 | config PINCTRL_MT6397 |
Jean Delvare | 79d6208 | 2017-01-25 10:32:09 +0100 | [diff] [blame] | 102 | bool "Mediatek MT6397 pin control" |
| 103 | depends on MFD_MT6397 || COMPILE_TEST |
Linus Walleij | a2202a4 | 2015-05-20 09:11:23 +0200 | [diff] [blame] | 104 | depends on OF |
Hongzhou Yang | fc59e66 | 2015-05-18 23:11:17 -0700 | [diff] [blame] | 105 | default MFD_MT6397 |
Masahiro Yamada | 4a9e006 | 2016-02-10 18:54:32 +0900 | [diff] [blame] | 106 | select PINCTRL_MTK |
Hongzhou Yang | fc59e66 | 2015-05-18 23:11:17 -0700 | [diff] [blame] | 107 | |
Sean Wang | e3fd24a | 2017-12-12 14:24:19 +0800 | [diff] [blame] | 108 | endmenu |