blob: 7bc0a6a7fadf9cf2ec3e828223369262f0474fa8 [file] [log] [blame]
Ben Hoe526c9b2019-05-27 17:04:42 +08001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8/dts-v1/;
9#include "mt8183.dtsi"
Hsin-Hsiung Wang9f887222020-04-21 11:00:12 +080010#include "mt6358.dtsi"
Ben Hoe526c9b2019-05-27 17:04:42 +080011
12/ {
13 model = "MediaTek MT8183 evaluation board";
14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
15
16 aliases {
17 serial0 = &uart0;
18 };
19
20 memory@40000000 {
21 device_type = "memory";
22 reg = <0 0x40000000 0 0x80000000>;
23 };
24
25 chosen {
26 stdout-path = "serial0:921600n8";
27 };
Eddie Huang1652dbf2019-11-12 19:03:27 +080028
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
32 ranges;
33 scp_mem_reserved: scp_mem_region {
34 compatible = "shared-dma-pool";
35 reg = <0 0x50000000 0 0x2900000>;
36 no-map;
37 };
38 };
Ben Hoe526c9b2019-05-27 17:04:42 +080039};
40
Zhiyong Taoeb59b352019-05-27 17:04:45 +080041&auxadc {
42 status = "okay";
43};
44
Nicolas Boichata8168ce2021-05-21 20:00:41 +080045&gpu {
46 mali-supply = <&mt6358_vgpu_reg>;
47 sram-supply = <&mt6358_vsram_gpu_reg>;
48};
49
Qii Wang251137b2019-08-22 20:35:16 +080050&i2c0 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&i2c_pins_0>;
53 status = "okay";
54 clock-frequency = <100000>;
55};
56
57&i2c1 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c_pins_1>;
60 status = "okay";
61 clock-frequency = <100000>;
62};
63
64&i2c2 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c_pins_2>;
67 status = "okay";
68 clock-frequency = <100000>;
69};
70
71&i2c3 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&i2c_pins_3>;
74 status = "okay";
75 clock-frequency = <100000>;
76};
77
78&i2c4 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&i2c_pins_4>;
81 status = "okay";
82 clock-frequency = <1000000>;
83};
84
85&i2c5 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c_pins_5>;
88 status = "okay";
89 clock-frequency = <1000000>;
90};
91
jjian zhou5e6cdf02019-04-10 17:25:41 +080092&mmc0 {
93 status = "okay";
94 pinctrl-names = "default", "state_uhs";
95 pinctrl-0 = <&mmc0_pins_default>;
96 pinctrl-1 = <&mmc0_pins_uhs>;
97 bus-width = <8>;
98 max-frequency = <200000000>;
99 cap-mmc-highspeed;
100 mmc-hs200-1_8v;
101 mmc-hs400-1_8v;
102 cap-mmc-hw-reset;
103 no-sdio;
104 no-sd;
105 hs400-ds-delay = <0x12814>;
106 vmmc-supply = <&mt6358_vemc_reg>;
107 vqmmc-supply = <&mt6358_vio18_reg>;
108 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
109 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
110 non-removable;
111};
112
113&mmc1 {
114 status = "okay";
115 pinctrl-names = "default", "state_uhs";
116 pinctrl-0 = <&mmc1_pins_default>;
117 pinctrl-1 = <&mmc1_pins_uhs>;
118 bus-width = <4>;
119 max-frequency = <200000000>;
120 cap-sd-highspeed;
121 sd-uhs-sdr50;
122 sd-uhs-sdr104;
123 cap-sdio-irq;
124 no-mmc;
125 no-sd;
126 vmmc-supply = <&mt6358_vmch_reg>;
127 vqmmc-supply = <&mt6358_vmc_reg>;
128 keep-power-in-suspend;
129 enable-sdio-wakeup;
130 non-removable;
131};
132
Erin Lo8e2dd0f2019-05-27 17:04:46 +0800133&pio {
Qii Wang251137b2019-08-22 20:35:16 +0800134 i2c_pins_0: i2c0{
135 pins_i2c{
136 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
137 <PINMUX_GPIO83__FUNC_SCL0>;
138 mediatek,pull-up-adv = <3>;
139 mediatek,drive-strength-adv = <00>;
140 };
141 };
142
143 i2c_pins_1: i2c1{
144 pins_i2c{
145 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
146 <PINMUX_GPIO84__FUNC_SCL1>;
147 mediatek,pull-up-adv = <3>;
148 mediatek,drive-strength-adv = <00>;
149 };
150 };
151
152 i2c_pins_2: i2c2{
153 pins_i2c{
154 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
155 <PINMUX_GPIO104__FUNC_SDA2>;
156 mediatek,pull-up-adv = <3>;
157 mediatek,drive-strength-adv = <00>;
158 };
159 };
160
161 i2c_pins_3: i2c3{
162 pins_i2c{
163 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
164 <PINMUX_GPIO51__FUNC_SDA3>;
165 mediatek,pull-up-adv = <3>;
166 mediatek,drive-strength-adv = <00>;
167 };
168 };
169
170 i2c_pins_4: i2c4{
171 pins_i2c{
172 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
173 <PINMUX_GPIO106__FUNC_SDA4>;
174 mediatek,pull-up-adv = <3>;
175 mediatek,drive-strength-adv = <00>;
176 };
177 };
178
179 i2c_pins_5: i2c5{
180 pins_i2c{
181 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
182 <PINMUX_GPIO49__FUNC_SDA5>;
183 mediatek,pull-up-adv = <3>;
184 mediatek,drive-strength-adv = <00>;
185 };
186 };
187
Erin Lo8e2dd0f2019-05-27 17:04:46 +0800188 spi_pins_0: spi0{
189 pins_spi{
190 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
191 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
192 <PINMUX_GPIO87__FUNC_SPI0_MO>,
193 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
194 bias-disable;
195 };
196 };
197
jjian zhou5e6cdf02019-04-10 17:25:41 +0800198 mmc0_pins_default: mmc0default {
199 pins_cmd_dat {
200 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
201 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
202 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
203 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
204 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
205 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
206 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
207 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
208 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
209 input-enable;
210 bias-pull-up;
211 };
212
213 pins_clk {
214 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
215 bias-pull-down;
216 };
217
218 pins_rst {
219 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
220 bias-pull-up;
221 };
222 };
223
Enric Balletbo i Serra4b1b8fd2020-06-25 12:17:55 +0200224 mmc0_pins_uhs: mmc0 {
jjian zhou5e6cdf02019-04-10 17:25:41 +0800225 pins_cmd_dat {
226 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
227 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
228 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
229 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
230 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
231 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
232 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
233 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
234 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
235 input-enable;
236 drive-strength = <MTK_DRIVE_10mA>;
237 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
238 };
239
240 pins_clk {
241 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
242 drive-strength = <MTK_DRIVE_10mA>;
243 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
244 };
245
246 pins_ds {
247 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
248 drive-strength = <MTK_DRIVE_10mA>;
249 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
250 };
251
252 pins_rst {
253 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
254 drive-strength = <MTK_DRIVE_10mA>;
255 bias-pull-up;
256 };
257 };
258
259 mmc1_pins_default: mmc1default {
260 pins_cmd_dat {
261 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
262 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
263 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
264 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
265 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
266 input-enable;
267 bias-pull-up;
268 };
269
270 pins_clk {
271 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
272 input-enable;
273 bias-pull-down;
274 };
275
276 pins_pmu {
277 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
278 <PINMUX_GPIO166__FUNC_GPIO166>;
279 output-high;
280 };
281 };
282
Enric Balletbo i Serra4b1b8fd2020-06-25 12:17:55 +0200283 mmc1_pins_uhs: mmc1 {
jjian zhou5e6cdf02019-04-10 17:25:41 +0800284 pins_cmd_dat {
285 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
286 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
287 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
288 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
289 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
290 drive-strength = <MTK_DRIVE_6mA>;
291 input-enable;
292 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
293 };
294
295 pins_clk {
296 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
297 drive-strength = <MTK_DRIVE_6mA>;
298 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
299 input-enable;
300 };
301 };
302
Erin Lo8e2dd0f2019-05-27 17:04:46 +0800303 spi_pins_1: spi1{
304 pins_spi{
305 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
306 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
307 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
308 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
309 bias-disable;
310 };
311 };
312
313 spi_pins_2: spi2{
314 pins_spi{
315 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
316 <PINMUX_GPIO1__FUNC_SPI2_MO>,
317 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
318 <PINMUX_GPIO94__FUNC_SPI2_MI>;
319 bias-disable;
320 };
321 };
322
323 spi_pins_3: spi3{
324 pins_spi{
325 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
326 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
327 <PINMUX_GPIO23__FUNC_SPI3_MO>,
328 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
329 bias-disable;
330 };
331 };
332
333 spi_pins_4: spi4{
334 pins_spi{
335 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
336 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
337 <PINMUX_GPIO19__FUNC_SPI4_MO>,
338 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
339 bias-disable;
340 };
341 };
342
343 spi_pins_5: spi5{
344 pins_spi{
345 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
346 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
347 <PINMUX_GPIO15__FUNC_SPI5_MO>,
348 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
349 bias-disable;
350 };
351 };
Fabien Parent06ec50e2020-12-09 13:03:21 +0100352
353 pwm_pins_1: pwm1 {
354 pins_pwm {
355 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
356 };
357 };
Erin Lo8e2dd0f2019-05-27 17:04:46 +0800358};
359
Hsin-Yi Wang2d7ee692021-02-01 17:30:49 +0800360&mfg {
361 domain-supply = <&mt6358_vgpu_reg>;
362};
363
Erin Lo8e2dd0f2019-05-27 17:04:46 +0800364&spi0 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&spi_pins_0>;
367 mediatek,pad-select = <0>;
368 status = "okay";
369};
370
371&spi1 {
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi_pins_1>;
374 mediatek,pad-select = <0>;
375 status = "okay";
376};
377
378&spi2 {
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi_pins_2>;
381 mediatek,pad-select = <0>;
382 status = "okay";
383};
384
385&spi3 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi_pins_3>;
388 mediatek,pad-select = <0>;
389 status = "okay";
390};
391
392&spi4 {
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi_pins_4>;
395 mediatek,pad-select = <0>;
396 status = "okay";
397};
398
399&spi5 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&spi_pins_5>;
402 mediatek,pad-select = <0>;
403 status = "okay";
404
405};
406
Ben Hoe526c9b2019-05-27 17:04:42 +0800407&uart0 {
408 status = "okay";
409};
Fabien Parent06ec50e2020-12-09 13:03:21 +0100410
411&pwm1 {
412 status = "okay";
413 pinctrl-0 = <&pwm_pins_1>;
414 pinctrl-names = "default";
415};