| Thomas Gleixner | 9c92ab6 | 2019-05-29 07:17:56 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2017 Texas Instruments, Inc. |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __DT_BINDINGS_CLK_DRA7_H |
| 6 | #define __DT_BINDINGS_CLK_DRA7_H |
| 7 | |
| 8 | #define DRA7_CLKCTRL_OFFSET 0x20 |
| 9 | #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) |
| 10 | |
| Tero Kristo | 8fa4509 | 2018-08-31 17:44:09 +0300 | [diff] [blame] | 11 | /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ |
| 12 | |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 13 | /* mpu clocks */ |
| 14 | #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 15 | |
| 16 | /* ipu clocks */ |
| Tero Kristo | 8fa4509 | 2018-08-31 17:44:09 +0300 | [diff] [blame] | 17 | #define _DRA7_IPU_CLKCTRL_OFFSET 0x40 |
| 18 | #define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) |
| 19 | #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) |
| 20 | #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) |
| 21 | #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) |
| 22 | #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) |
| 23 | #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) |
| 24 | #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) |
| 25 | #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 26 | |
| 27 | /* rtc clocks */ |
| 28 | #define DRA7_RTC_CLKCTRL_OFFSET 0x40 |
| 29 | #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) |
| 30 | #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) |
| 31 | |
| Benoit Parrot | 7054c14 | 2019-12-11 08:05:49 -0600 | [diff] [blame^] | 32 | /* vip clocks */ |
| 33 | #define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 34 | #define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 35 | #define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 36 | |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 37 | /* coreaon clocks */ |
| 38 | #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 39 | #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) |
| 40 | |
| 41 | /* l3main1 clocks */ |
| 42 | #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 43 | #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 44 | #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) |
| 45 | #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) |
| 46 | #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) |
| 47 | #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 48 | #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) |
| 49 | |
| 50 | /* dma clocks */ |
| 51 | #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 52 | |
| 53 | /* emif clocks */ |
| 54 | #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 55 | |
| 56 | /* atl clocks */ |
| 57 | #define DRA7_ATL_CLKCTRL_OFFSET 0x0 |
| 58 | #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) |
| 59 | #define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) |
| 60 | |
| 61 | /* l4cfg clocks */ |
| 62 | #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 63 | #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 64 | #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 65 | #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) |
| 66 | #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) |
| 67 | #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) |
| 68 | #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) |
| 69 | #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) |
| 70 | #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) |
| 71 | #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) |
| 72 | #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) |
| 73 | #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 74 | #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) |
| 75 | #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) |
| 76 | #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) |
| 77 | |
| 78 | /* l3instr clocks */ |
| 79 | #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 80 | #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 81 | |
| 82 | /* dss clocks */ |
| 83 | #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 84 | #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 85 | |
| 86 | /* l3init clocks */ |
| 87 | #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 88 | #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 89 | #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) |
| 90 | #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) |
| 91 | #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) |
| 92 | #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 93 | #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) |
| 94 | #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) |
| 95 | #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) |
| 96 | #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) |
| 97 | #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) |
| 98 | #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) |
| 99 | |
| 100 | /* l4per clocks */ |
| Tero Kristo | 8fa4509 | 2018-08-31 17:44:09 +0300 | [diff] [blame] | 101 | #define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 |
| 102 | #define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) |
| 103 | #define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) |
| 104 | #define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) |
| 105 | #define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) |
| 106 | #define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) |
| 107 | #define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) |
| 108 | #define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) |
| 109 | #define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) |
| 110 | #define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) |
| 111 | #define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) |
| 112 | #define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) |
| 113 | #define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) |
| 114 | #define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) |
| 115 | #define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) |
| 116 | #define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) |
| 117 | #define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) |
| 118 | #define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) |
| 119 | #define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) |
| 120 | #define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) |
| 121 | #define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) |
| 122 | #define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) |
| 123 | #define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) |
| 124 | #define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) |
| 125 | #define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) |
| 126 | #define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) |
| 127 | #define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) |
| 128 | #define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) |
| 129 | #define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) |
| 130 | #define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) |
| 131 | #define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) |
| 132 | #define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) |
| 133 | #define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) |
| 134 | #define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) |
| 135 | #define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) |
| 136 | #define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) |
| 137 | #define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) |
| 138 | #define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) |
| 139 | #define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) |
| 140 | #define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) |
| 141 | #define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) |
| 142 | #define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) |
| 143 | #define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) |
| 144 | #define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) |
| 145 | #define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) |
| 146 | #define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) |
| 147 | #define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) |
| 148 | #define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) |
| 149 | #define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) |
| 150 | #define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) |
| 151 | #define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) |
| 152 | #define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) |
| 153 | #define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) |
| 154 | #define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) |
| 155 | #define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) |
| 156 | #define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) |
| 157 | #define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) |
| 158 | #define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) |
| 159 | #define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 160 | |
| 161 | /* wkupaon clocks */ |
| 162 | #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 163 | #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 164 | #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) |
| 165 | #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) |
| 166 | #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) |
| 167 | #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) |
| 168 | #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) |
| 169 | #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| Faiz Abbas | 91c17a7 | 2018-07-09 22:18:37 +0530 | [diff] [blame] | 170 | #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 171 | |
| Tero Kristo | 8fa4509 | 2018-08-31 17:44:09 +0300 | [diff] [blame] | 172 | /* XXX: Compatibility part end. */ |
| 173 | |
| 174 | /* mpu clocks */ |
| 175 | #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 176 | |
| 177 | /* dsp1 clocks */ |
| 178 | #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 179 | |
| 180 | /* ipu1 clocks */ |
| 181 | #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 182 | |
| 183 | /* ipu clocks */ |
| 184 | #define DRA7_IPU_CLKCTRL_OFFSET 0x50 |
| 185 | #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) |
| 186 | #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) |
| 187 | #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) |
| 188 | #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) |
| 189 | #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) |
| 190 | #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) |
| 191 | #define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) |
| 192 | #define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) |
| 193 | |
| 194 | /* dsp2 clocks */ |
| 195 | #define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 196 | |
| 197 | /* rtc clocks */ |
| 198 | #define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) |
| 199 | |
| Benoit Parrot | 7054c14 | 2019-12-11 08:05:49 -0600 | [diff] [blame^] | 200 | /* vip clocks */ |
| 201 | #define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 202 | #define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 203 | #define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 204 | |
| Tero Kristo | 8fa4509 | 2018-08-31 17:44:09 +0300 | [diff] [blame] | 205 | /* coreaon clocks */ |
| 206 | #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 207 | #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) |
| 208 | |
| 209 | /* l3main1 clocks */ |
| 210 | #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 211 | #define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 212 | #define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) |
| 213 | #define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) |
| 214 | #define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) |
| 215 | #define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 216 | #define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) |
| 217 | |
| 218 | /* ipu2 clocks */ |
| 219 | #define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 220 | |
| 221 | /* dma clocks */ |
| 222 | #define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 223 | |
| 224 | /* emif clocks */ |
| 225 | #define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 226 | |
| 227 | /* atl clocks */ |
| 228 | #define DRA7_ATL_CLKCTRL_OFFSET 0x0 |
| 229 | #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) |
| 230 | #define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) |
| 231 | |
| 232 | /* l4cfg clocks */ |
| 233 | #define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 234 | #define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 235 | #define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 236 | #define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) |
| 237 | #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) |
| 238 | #define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) |
| 239 | #define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) |
| 240 | #define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) |
| 241 | #define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) |
| 242 | #define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) |
| 243 | #define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) |
| 244 | #define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 245 | #define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) |
| 246 | #define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) |
| 247 | #define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) |
| 248 | |
| 249 | /* l3instr clocks */ |
| 250 | #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 251 | #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 252 | |
| 253 | /* dss clocks */ |
| 254 | #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 255 | #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 256 | |
| 257 | /* l3init clocks */ |
| 258 | #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) |
| 259 | #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 260 | #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) |
| 261 | #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) |
| 262 | #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) |
| 263 | #define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 264 | #define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) |
| 265 | #define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) |
| 266 | #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) |
| 267 | |
| 268 | /* pcie clocks */ |
| 269 | #define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 |
| 270 | #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) |
| 271 | #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) |
| 272 | #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) |
| 273 | |
| 274 | /* gmac clocks */ |
| 275 | #define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 |
| 276 | #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) |
| 277 | #define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) |
| 278 | |
| 279 | /* l4per clocks */ |
| 280 | #define DRA7_L4PER_CLKCTRL_OFFSET 0x28 |
| 281 | #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) |
| 282 | #define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) |
| 283 | #define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) |
| 284 | #define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) |
| 285 | #define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) |
| 286 | #define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) |
| 287 | #define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) |
| 288 | #define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) |
| 289 | #define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) |
| 290 | #define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) |
| 291 | #define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) |
| 292 | #define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) |
| 293 | #define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) |
| 294 | #define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) |
| 295 | #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) |
| 296 | #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) |
| 297 | #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) |
| 298 | #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) |
| 299 | #define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) |
| 300 | #define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) |
| 301 | #define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) |
| 302 | #define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) |
| 303 | #define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) |
| 304 | #define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) |
| 305 | #define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) |
| 306 | #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) |
| 307 | #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) |
| 308 | #define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) |
| 309 | #define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) |
| 310 | #define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) |
| 311 | #define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) |
| 312 | #define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) |
| 313 | |
| 314 | /* l4sec clocks */ |
| 315 | #define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 |
| 316 | #define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) |
| 317 | #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) |
| 318 | #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) |
| 319 | #define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) |
| 320 | #define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) |
| 321 | #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) |
| 322 | |
| 323 | /* l4per2 clocks */ |
| 324 | #define DRA7_L4PER2_CLKCTRL_OFFSET 0xc |
| 325 | #define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) |
| 326 | #define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) |
| 327 | #define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) |
| 328 | #define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) |
| 329 | #define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) |
| 330 | #define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) |
| 331 | #define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) |
| 332 | #define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) |
| 333 | #define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) |
| 334 | #define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) |
| 335 | #define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) |
| 336 | #define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) |
| 337 | #define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) |
| 338 | #define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) |
| 339 | #define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) |
| 340 | #define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) |
| 341 | #define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) |
| 342 | #define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) |
| 343 | #define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) |
| 344 | |
| 345 | /* l4per3 clocks */ |
| 346 | #define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 |
| 347 | #define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) |
| 348 | #define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) |
| 349 | #define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) |
| 350 | #define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) |
| 351 | #define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) |
| 352 | #define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) |
| 353 | |
| 354 | /* wkupaon clocks */ |
| 355 | #define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) |
| 356 | #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) |
| 357 | #define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) |
| 358 | #define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) |
| 359 | #define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) |
| 360 | #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) |
| 361 | #define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) |
| 362 | #define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) |
| 363 | #define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) |
| 364 | |
| Tero Kristo | ae263d5 | 2017-08-16 11:48:24 +0300 | [diff] [blame] | 365 | #endif |