blob: 0edebf3355fa51e2128413f726f2ccfb5cd0ba9c [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Paul Walmsley0fd0c212011-02-25 15:49:53 -07002/*
3 * OMAP2-specific DPLL control functions
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Paul Walmsley
Paul Walmsley0fd0c212011-02-25 15:49:53 -07007 */
8
9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13
Paul Walmsley0fd0c212011-02-25 15:49:53 -070014#include "clock.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -060015#include "cm2xxx.h"
Paul Walmsley0fd0c212011-02-25 15:49:53 -070016#include "cm-regbits-24xx.h"
17
18/* Private functions */
19
20/**
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
23 *
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
25 * stop when its downstream clocks are gated. No return value.
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
27 * instead. Add some mechanism to optionally enter this mode.
28 */
Rajendra Nayaked1ebc42012-04-27 15:59:32 +053029static void _allow_idle(struct clk_hw_omap *clk)
Paul Walmsley0fd0c212011-02-25 15:49:53 -070030{
31 if (!clk || !clk->dpll_data)
32 return;
33
34 omap2xxx_cm_set_dpll_auto_low_power_stop();
35}
36
37/**
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
40 *
41 * Disable DPLL automatic idle control. No return value.
42 */
Rajendra Nayaked1ebc42012-04-27 15:59:32 +053043static void _deny_idle(struct clk_hw_omap *clk)
Paul Walmsley0fd0c212011-02-25 15:49:53 -070044{
45 if (!clk || !clk->dpll_data)
46 return;
47
48 omap2xxx_cm_set_dpll_disable_autoidle();
49}
50
51
52/* Public data */
Rajendra Nayaked1ebc42012-04-27 15:59:32 +053053const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
54 .allow_idle = _allow_idle,
55 .deny_idle = _deny_idle,
56};