Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005 Cisco Systems. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #ifndef IB_SRP_H |
| 34 | #define IB_SRP_H |
| 35 | |
| 36 | #include <linux/types.h> |
| 37 | #include <linux/list.h> |
Ingo Molnar | 8e9e5f4f | 2006-01-30 15:21:21 -0800 | [diff] [blame] | 38 | #include <linux/mutex.h> |
Roland Dreier | cf36871 | 2006-03-24 15:47:26 -0800 | [diff] [blame] | 39 | #include <linux/scatterlist.h> |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 40 | |
| 41 | #include <scsi/scsi_host.h> |
| 42 | #include <scsi/scsi_cmnd.h> |
| 43 | |
| 44 | #include <rdma/ib_verbs.h> |
| 45 | #include <rdma/ib_sa.h> |
| 46 | #include <rdma/ib_cm.h> |
Bart Van Assche | 19f3134 | 2018-01-22 14:27:12 -0800 | [diff] [blame] | 47 | #include <rdma/rdma_cm.h> |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 48 | |
| 49 | enum { |
| 50 | SRP_PATH_REC_TIMEOUT_MS = 1000, |
| 51 | SRP_ABORT_TIMEOUT_MS = 5000, |
| 52 | |
| 53 | SRP_PORT_REDIRECT = 1, |
| 54 | SRP_DLID_REDIRECT = 2, |
David Dillow | 9fe4bcf | 2008-01-08 17:08:52 -0500 | [diff] [blame] | 55 | SRP_STALE_CONN = 3, |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 56 | |
Vu Pham | 74b0a15 | 2006-06-17 20:37:32 -0700 | [diff] [blame] | 57 | SRP_DEF_SG_TABLESIZE = 12, |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 58 | |
Bart Van Assche | 4d73f95 | 2013-10-26 14:40:37 +0200 | [diff] [blame] | 59 | SRP_DEFAULT_QUEUE_SIZE = 1 << 6, |
Bart Van Assche | dd5e6e3 | 2010-08-30 19:27:20 +0000 | [diff] [blame] | 60 | SRP_RSP_SQ_SIZE = 1, |
Bart Van Assche | dd5e6e3 | 2010-08-30 19:27:20 +0000 | [diff] [blame] | 61 | SRP_TSK_MGMT_SQ_SIZE = 1, |
Bart Van Assche | 4d73f95 | 2013-10-26 14:40:37 +0200 | [diff] [blame] | 62 | SRP_DEFAULT_CMD_SQ_SIZE = SRP_DEFAULT_QUEUE_SIZE - SRP_RSP_SQ_SIZE - |
| 63 | SRP_TSK_MGMT_SQ_SIZE, |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 64 | |
David Dillow | f8b6e31 | 2010-11-26 13:02:21 -0500 | [diff] [blame] | 65 | SRP_TAG_NO_REQ = ~0U, |
| 66 | SRP_TAG_TSK_MGMT = 1U << 31, |
Roland Dreier | f5358a1 | 2006-06-17 20:37:29 -0700 | [diff] [blame] | 67 | |
Bart Van Assche | 52ede08 | 2014-05-20 15:07:45 +0200 | [diff] [blame] | 68 | SRP_MAX_PAGES_PER_MR = 512, |
Bart Van Assche | 482fffc | 2018-12-17 13:20:35 -0800 | [diff] [blame] | 69 | |
| 70 | SRP_MAX_ADD_CDB_LEN = 16, |
Bart Van Assche | 882981f | 2018-12-17 13:20:39 -0800 | [diff] [blame] | 71 | |
| 72 | SRP_MAX_IMM_SGE = 2, |
| 73 | SRP_MAX_SGE = SRP_MAX_IMM_SGE + 1, |
| 74 | /* |
| 75 | * Choose the immediate data offset such that a 32 byte CDB still fits. |
| 76 | */ |
| 77 | SRP_IMM_DATA_OFFSET = sizeof(struct srp_cmd) + |
| 78 | SRP_MAX_ADD_CDB_LEN + |
| 79 | sizeof(struct srp_imm_buf), |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 80 | }; |
| 81 | |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 82 | enum srp_target_state { |
Bart Van Assche | 34aa654 | 2014-10-30 14:47:22 +0100 | [diff] [blame] | 83 | SRP_TARGET_SCANNING, |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 84 | SRP_TARGET_LIVE, |
Bart Van Assche | ef6c49d | 2011-12-26 16:49:18 +0000 | [diff] [blame] | 85 | SRP_TARGET_REMOVED, |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 86 | }; |
| 87 | |
David Dillow | bb12588 | 2010-10-08 14:40:47 -0400 | [diff] [blame] | 88 | enum srp_iu_type { |
| 89 | SRP_IU_CMD, |
| 90 | SRP_IU_TSK_MGMT, |
| 91 | SRP_IU_RSP, |
David Dillow | 8cba207 | 2007-12-19 17:08:43 -0500 | [diff] [blame] | 92 | }; |
| 93 | |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 94 | /* |
| 95 | * @mr_page_mask: HCA memory registration page mask. |
| 96 | * @mr_page_size: HCA memory registration page size. |
Max Gurtovoy | f273ad4 | 2020-05-28 16:45:44 -0300 | [diff] [blame] | 97 | * @mr_max_size: Maximum size in bytes of a single FR registration request. |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 98 | */ |
Roland Dreier | f5358a1 | 2006-06-17 20:37:29 -0700 | [diff] [blame] | 99 | struct srp_device { |
| 100 | struct list_head dev_list; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 101 | struct ib_device *dev; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 102 | struct ib_pd *pd; |
Bart Van Assche | cee687b | 2017-10-11 10:27:28 -0700 | [diff] [blame] | 103 | u32 global_rkey; |
Bart Van Assche | 52ede08 | 2014-05-20 15:07:45 +0200 | [diff] [blame] | 104 | u64 mr_page_mask; |
| 105 | int mr_page_size; |
| 106 | int mr_max_size; |
| 107 | int max_pages_per_mr; |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 108 | bool has_fr; |
| 109 | bool use_fast_reg; |
Roland Dreier | f5358a1 | 2006-06-17 20:37:29 -0700 | [diff] [blame] | 110 | }; |
| 111 | |
| 112 | struct srp_host { |
Greg Kroah-Hartman | 0532193 | 2008-03-06 00:13:36 +0100 | [diff] [blame] | 113 | struct srp_device *srp_dev; |
Roland Dreier | f5358a1 | 2006-06-17 20:37:29 -0700 | [diff] [blame] | 114 | u8 port; |
Tony Jones | ee959b0 | 2008-02-22 00:13:36 +0100 | [diff] [blame] | 115 | struct device dev; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 116 | struct list_head target_list; |
Matthew Wilcox | b3589fd | 2006-06-17 20:37:30 -0700 | [diff] [blame] | 117 | spinlock_t target_lock; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 118 | struct completion released; |
| 119 | struct list_head list; |
Bart Van Assche | 2d7091b | 2014-03-14 13:52:45 +0100 | [diff] [blame] | 120 | struct mutex add_target_mutex; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | struct srp_request { |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 124 | struct scsi_cmnd *scmnd; |
| 125 | struct srp_iu *cmd; |
Max Gurtovoy | f273ad4 | 2020-05-28 16:45:44 -0300 | [diff] [blame] | 126 | struct srp_fr_desc **fr_list; |
David Dillow | c07d424 | 2011-01-16 13:57:10 -0500 | [diff] [blame] | 127 | struct srp_direct_buf *indirect_desc; |
| 128 | dma_addr_t indirect_dma_addr; |
Bart Van Assche | 52ede08 | 2014-05-20 15:07:45 +0200 | [diff] [blame] | 129 | short nmdesc; |
Christoph Hellwig | 1dc7b1f | 2015-11-13 12:57:13 +0100 | [diff] [blame] | 130 | struct ib_cqe reg_cqe; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 131 | }; |
| 132 | |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 133 | /** |
| 134 | * struct srp_rdma_ch |
| 135 | * @comp_vector: Completion vector used by this RDMA channel. |
Bart Van Assche | 513d564 | 2018-12-17 13:20:38 -0800 | [diff] [blame] | 136 | * @max_it_iu_len: Maximum initiator-to-target information unit length. |
Bart Van Assche | 4f6d498 | 2018-12-17 13:20:37 -0800 | [diff] [blame] | 137 | * @max_ti_iu_len: Maximum target-to-initiator information unit length. |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 138 | */ |
| 139 | struct srp_rdma_ch { |
David Dillow | 9af7627 | 2010-11-26 15:34:46 -0500 | [diff] [blame] | 140 | /* These are RW in the hot path, and commonly used together */ |
| 141 | struct list_head free_tx; |
David Dillow | 9af7627 | 2010-11-26 15:34:46 -0500 | [diff] [blame] | 142 | spinlock_t lock; |
| 143 | s32 req_lim; |
| 144 | |
| 145 | /* These are read-only in the hot path */ |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 146 | struct srp_target_port *target ____cacheline_aligned_in_smp; |
| 147 | struct ib_cq *send_cq; |
David Dillow | 9af7627 | 2010-11-26 15:34:46 -0500 | [diff] [blame] | 148 | struct ib_cq *recv_cq; |
| 149 | struct ib_qp *qp; |
Max Gurtovoy | f273ad4 | 2020-05-28 16:45:44 -0300 | [diff] [blame] | 150 | struct srp_fr_pool *fr_pool; |
Bart Van Assche | 513d564 | 2018-12-17 13:20:38 -0800 | [diff] [blame] | 151 | uint32_t max_it_iu_len; |
Bart Van Assche | 4f6d498 | 2018-12-17 13:20:37 -0800 | [diff] [blame] | 152 | uint32_t max_ti_iu_len; |
Bart Van Assche | bf58347 | 2019-09-30 16:16:59 -0700 | [diff] [blame] | 153 | u8 max_imm_sge; |
Bart Van Assche | 882981f | 2018-12-17 13:20:39 -0800 | [diff] [blame] | 154 | bool use_imm_data; |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 155 | |
| 156 | /* Everything above this point is used in the hot path of |
| 157 | * command processing. Try to keep them packed into cachelines. |
| 158 | */ |
| 159 | |
| 160 | struct completion done; |
| 161 | int status; |
| 162 | |
Bart Van Assche | 19f3134 | 2018-01-22 14:27:12 -0800 | [diff] [blame] | 163 | union { |
| 164 | struct ib_cm { |
| 165 | struct sa_path_rec path; |
| 166 | struct ib_sa_query *path_query; |
| 167 | int path_query_id; |
| 168 | struct ib_cm_id *cm_id; |
| 169 | } ib_cm; |
| 170 | struct rdma_cm { |
| 171 | struct rdma_cm_id *cm_id; |
| 172 | } rdma_cm; |
| 173 | }; |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 174 | |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 175 | struct srp_iu **tx_ring; |
| 176 | struct srp_iu **rx_ring; |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 177 | int comp_vector; |
| 178 | |
Bart Van Assche | 0a6fdbd | 2017-02-14 10:56:31 -0800 | [diff] [blame] | 179 | u64 tsk_mgmt_tag; |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 180 | struct completion tsk_mgmt_done; |
| 181 | u8 tsk_mgmt_status; |
Bart Van Assche | c014c8c | 2015-05-18 13:23:57 +0200 | [diff] [blame] | 182 | bool connected; |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 183 | }; |
| 184 | |
| 185 | /** |
| 186 | * struct srp_target_port |
| 187 | * @comp_vector: Completion vector used by the first RDMA channel created for |
| 188 | * this target port. |
| 189 | */ |
| 190 | struct srp_target_port { |
| 191 | /* read and written in the hot path */ |
| 192 | spinlock_t lock; |
| 193 | |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 194 | /* read only in the hot path */ |
Bart Van Assche | cee687b | 2017-10-11 10:27:28 -0700 | [diff] [blame] | 195 | u32 global_rkey; |
Bart Van Assche | d92c0da | 2014-10-06 17:14:36 +0200 | [diff] [blame] | 196 | struct srp_rdma_ch *ch; |
Bart Van Assche | 19f3134 | 2018-01-22 14:27:12 -0800 | [diff] [blame] | 197 | struct net *net; |
Bart Van Assche | d92c0da | 2014-10-06 17:14:36 +0200 | [diff] [blame] | 198 | u32 ch_count; |
David Dillow | 9af7627 | 2010-11-26 15:34:46 -0500 | [diff] [blame] | 199 | u32 lkey; |
David Dillow | 9af7627 | 2010-11-26 15:34:46 -0500 | [diff] [blame] | 200 | enum srp_target_state state; |
Honggang Li | 547ed33 | 2019-09-28 01:43:51 +0800 | [diff] [blame] | 201 | uint32_t max_it_iu_size; |
David Dillow | 4924864 | 2011-01-14 18:23:24 -0500 | [diff] [blame] | 202 | unsigned int cmd_sg_cnt; |
David Dillow | c07d424 | 2011-01-16 13:57:10 -0500 | [diff] [blame] | 203 | unsigned int indirect_size; |
| 204 | bool allow_ext_sg; |
David Dillow | 9af7627 | 2010-11-26 15:34:46 -0500 | [diff] [blame] | 205 | |
Bart Van Assche | 509c07b | 2014-10-30 14:48:30 +0100 | [diff] [blame] | 206 | /* other member variables */ |
Bart Van Assche | 747fe00 | 2014-10-30 14:48:05 +0100 | [diff] [blame] | 207 | union ib_gid sgid; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 208 | __be64 id_ext; |
| 209 | __be64 ioc_guid; |
Ishai Rabinovitz | 01cb9bc | 2006-10-04 15:28:56 +0200 | [diff] [blame] | 210 | __be64 initiator_ext; |
Ramachandra K | 0c0450db | 2006-06-17 20:37:38 -0700 | [diff] [blame] | 211 | u16 io_class; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 212 | struct srp_host *srp_host; |
| 213 | struct Scsi_Host *scsi_host; |
Bart Van Assche | 9dd69a6 | 2013-10-26 14:32:30 +0200 | [diff] [blame] | 214 | struct srp_rport *rport; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 215 | char target_name[32]; |
| 216 | unsigned int scsi_id; |
David Dillow | c07d424 | 2011-01-16 13:57:10 -0500 | [diff] [blame] | 217 | unsigned int sg_tablesize; |
Bart Van Assche | b0780ee | 2018-01-22 14:27:13 -0800 | [diff] [blame] | 218 | unsigned int target_can_queue; |
Bart Van Assche | fa9863f | 2016-04-22 14:13:57 -0700 | [diff] [blame] | 219 | int mr_pool_size; |
Bart Van Assche | 509c5f3 | 2016-05-12 10:50:35 -0700 | [diff] [blame] | 220 | int mr_per_cmd; |
Bart Van Assche | 4d73f95 | 2013-10-26 14:40:37 +0200 | [diff] [blame] | 221 | int queue_size; |
Bart Van Assche | 4b5e5f4 | 2013-06-28 14:57:42 +0200 | [diff] [blame] | 222 | int comp_vector; |
Vu Pham | 7bb312e | 2013-10-26 14:31:27 +0200 | [diff] [blame] | 223 | int tl_retry_count; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 224 | |
Bart Van Assche | 19f3134 | 2018-01-22 14:27:12 -0800 | [diff] [blame] | 225 | bool using_rdma_cm; |
| 226 | |
| 227 | union { |
| 228 | struct { |
| 229 | __be64 service_id; |
| 230 | union ib_gid orig_dgid; |
| 231 | __be16 pkey; |
| 232 | } ib_cm; |
| 233 | struct { |
| 234 | union { |
| 235 | struct sockaddr_in ip4; |
| 236 | struct sockaddr_in6 ip6; |
Bart Van Assche | 1467377 | 2019-09-30 16:16:58 -0700 | [diff] [blame] | 237 | struct sockaddr sa; |
Bart Van Assche | 19f3134 | 2018-01-22 14:27:12 -0800 | [diff] [blame] | 238 | struct sockaddr_storage ss; |
| 239 | } src; |
| 240 | union { |
| 241 | struct sockaddr_in ip4; |
| 242 | struct sockaddr_in6 ip6; |
Bart Van Assche | 1467377 | 2019-09-30 16:16:58 -0700 | [diff] [blame] | 243 | struct sockaddr sa; |
Bart Van Assche | 19f3134 | 2018-01-22 14:27:12 -0800 | [diff] [blame] | 244 | struct sockaddr_storage ss; |
| 245 | } dst; |
| 246 | bool src_specified; |
| 247 | } rdma_cm; |
| 248 | }; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 249 | |
Bart Van Assche | c9b03c1 | 2011-09-03 09:34:48 +0200 | [diff] [blame] | 250 | u32 rq_tmo_jiffies; |
| 251 | |
Roland Dreier | 6bfa24f | 2006-06-17 20:37:33 -0700 | [diff] [blame] | 252 | int zero_req_lim; |
| 253 | |
Bart Van Assche | c1120f8 | 2013-10-26 14:35:08 +0200 | [diff] [blame] | 254 | struct work_struct tl_err_work; |
Bart Van Assche | ef6c49d | 2011-12-26 16:49:18 +0000 | [diff] [blame] | 255 | struct work_struct remove_work; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 256 | |
| 257 | struct list_head list; |
Bart Van Assche | 948d1e8 | 2011-09-03 09:25:42 +0200 | [diff] [blame] | 258 | bool qp_in_error; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | struct srp_iu { |
Bart Van Assche | dcb4cb8 | 2010-11-26 13:22:48 -0500 | [diff] [blame] | 262 | struct list_head list; |
Ralph Campbell | 85507bc | 2006-12-12 14:30:55 -0800 | [diff] [blame] | 263 | u64 dma; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 264 | void *buf; |
| 265 | size_t size; |
| 266 | enum dma_data_direction direction; |
Bart Van Assche | 882981f | 2018-12-17 13:20:39 -0800 | [diff] [blame] | 267 | u32 num_sge; |
| 268 | struct ib_sge sge[SRP_MAX_SGE]; |
Christoph Hellwig | 1dc7b1f | 2015-11-13 12:57:13 +0100 | [diff] [blame] | 269 | struct ib_cqe cqe; |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 270 | }; |
| 271 | |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 272 | /** |
| 273 | * struct srp_fr_desc - fast registration work request arguments |
| 274 | * @entry: Entry in srp_fr_pool.free_list. |
| 275 | * @mr: Memory region. |
| 276 | * @frpl: Fast registration page list. |
| 277 | */ |
| 278 | struct srp_fr_desc { |
| 279 | struct list_head entry; |
| 280 | struct ib_mr *mr; |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | /** |
| 284 | * struct srp_fr_pool - pool of fast registration descriptors |
| 285 | * |
| 286 | * An entry is available for allocation if and only if it occurs in @free_list. |
| 287 | * |
| 288 | * @size: Number of descriptors in this pool. |
| 289 | * @max_page_list_len: Maximum fast registration work request page list length. |
| 290 | * @lock: Protects free_list. |
| 291 | * @free_list: List of free descriptors. |
| 292 | * @desc: Fast registration descriptor pool. |
| 293 | */ |
| 294 | struct srp_fr_pool { |
| 295 | int size; |
| 296 | int max_page_list_len; |
| 297 | spinlock_t lock; |
| 298 | struct list_head free_list; |
Gustavo A. R. Silva | 5b36132 | 2020-02-12 19:04:25 -0600 | [diff] [blame] | 299 | struct srp_fr_desc desc[]; |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 300 | }; |
| 301 | |
| 302 | /** |
| 303 | * struct srp_map_state - per-request DMA memory mapping state |
| 304 | * @desc: Pointer to the element of the SRP buffer descriptor array |
| 305 | * that is being filled in. |
| 306 | * @pages: Array with DMA addresses of pages being considered for |
| 307 | * memory registration. |
| 308 | * @base_dma_addr: DMA address of the first page that has not yet been mapped. |
Max Gurtovoy | f273ad4 | 2020-05-28 16:45:44 -0300 | [diff] [blame] | 309 | * @dma_len: Number of bytes that will be registered with the next FR |
| 310 | * memory registration call. |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 311 | * @total_len: Total number of bytes in the sg-list being mapped. |
| 312 | * @npages: Number of page addresses in the pages[] array. |
Max Gurtovoy | f273ad4 | 2020-05-28 16:45:44 -0300 | [diff] [blame] | 313 | * @nmdesc: Number of FR memory descriptors used for mapping. |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 314 | * @ndesc: Number of SRP buffer descriptors that have been filled in. |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 315 | */ |
David Dillow | 8f26c9f | 2011-01-14 19:45:50 -0500 | [diff] [blame] | 316 | struct srp_map_state { |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 317 | union { |
Bart Van Assche | f731ed6 | 2015-08-10 17:07:27 -0700 | [diff] [blame] | 318 | struct { |
Bart Van Assche | f731ed6 | 2015-08-10 17:07:27 -0700 | [diff] [blame] | 319 | struct srp_fr_desc **next; |
| 320 | struct srp_fr_desc **end; |
| 321 | } fr; |
Bart Van Assche | 330179f | 2015-08-10 17:09:05 -0700 | [diff] [blame] | 322 | struct { |
| 323 | void **next; |
| 324 | void **end; |
| 325 | } gen; |
Bart Van Assche | 5cfb178 | 2014-05-20 15:08:34 +0200 | [diff] [blame] | 326 | }; |
David Dillow | 8f26c9f | 2011-01-14 19:45:50 -0500 | [diff] [blame] | 327 | struct srp_direct_buf *desc; |
Sagi Grimberg | f7f7aab | 2015-10-13 19:11:39 +0300 | [diff] [blame] | 328 | union { |
| 329 | u64 *pages; |
| 330 | struct scatterlist *sg; |
| 331 | }; |
David Dillow | 8f26c9f | 2011-01-14 19:45:50 -0500 | [diff] [blame] | 332 | dma_addr_t base_dma_addr; |
Bart Van Assche | 52ede08 | 2014-05-20 15:07:45 +0200 | [diff] [blame] | 333 | u32 dma_len; |
David Dillow | 8f26c9f | 2011-01-14 19:45:50 -0500 | [diff] [blame] | 334 | u32 total_len; |
Bart Van Assche | 57b0be9 | 2015-12-01 10:19:38 -0800 | [diff] [blame] | 335 | unsigned int npages; |
Bart Van Assche | 52ede08 | 2014-05-20 15:07:45 +0200 | [diff] [blame] | 336 | unsigned int nmdesc; |
David Dillow | 8f26c9f | 2011-01-14 19:45:50 -0500 | [diff] [blame] | 337 | unsigned int ndesc; |
David Dillow | 8f26c9f | 2011-01-14 19:45:50 -0500 | [diff] [blame] | 338 | }; |
| 339 | |
Roland Dreier | aef9ec3 | 2005-11-02 14:07:13 -0800 | [diff] [blame] | 340 | #endif /* IB_SRP_H */ |