Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 2 | menuconfig PM_DEVFREQ |
| 3 | bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support" |
Pranith Kumar | 83fe27e | 2014-12-05 11:24:45 -0500 | [diff] [blame] | 4 | select SRCU |
Chanwoo Choi | b9c69e0 | 2017-08-24 10:42:51 +0900 | [diff] [blame] | 5 | select PM_OPP |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 6 | help |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 7 | A device may have a list of frequencies and voltages available. |
| 8 | devfreq, a generic DVFS framework can be registered for a device |
| 9 | in order to let the governor provided to devfreq choose an |
| 10 | operating frequency based on the device driver's policy. |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 11 | |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 12 | Each device may have its own governor and policy. Devfreq can |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 13 | reevaluate the device state periodically and/or based on the |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 14 | notification to "nb", a notifier block, of devfreq. |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 15 | |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 16 | Like some CPUs with CPUfreq, a device may have multiple clocks. |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 17 | However, because the clock frequencies of a single device are |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 18 | determined by the single device's state, an instance of devfreq |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 19 | is attached to a single device and returns a "representative" |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 20 | clock frequency of the device, which is also attached |
| 21 | to a device by 1-to-1. The device registering devfreq takes the |
Masanari Iida | 6b2aac4 | 2012-04-14 00:14:11 +0900 | [diff] [blame] | 22 | responsibility to "interpret" the representative frequency and |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 23 | to set its every clock accordingly with the "target" callback |
MyungJoo Ham | 6c81f90 | 2011-11-14 23:31:35 +0100 | [diff] [blame] | 24 | given to devfreq. |
| 25 | |
| 26 | When OPP is used with the devfreq device, it is recommended to |
| 27 | register devfreq's nb to the OPP's notifier head. If OPP is |
| 28 | used with the devfreq device, you may use OPP helper |
| 29 | functions defined in devfreq.h. |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 30 | |
| 31 | if PM_DEVFREQ |
| 32 | |
MyungJoo Ham | ce26c5b | 2011-10-02 00:19:34 +0200 | [diff] [blame] | 33 | comment "DEVFREQ Governors" |
| 34 | |
| 35 | config DEVFREQ_GOV_SIMPLE_ONDEMAND |
Nishanth Menon | eff607f | 2012-10-29 15:01:46 -0500 | [diff] [blame] | 36 | tristate "Simple Ondemand" |
MyungJoo Ham | ce26c5b | 2011-10-02 00:19:34 +0200 | [diff] [blame] | 37 | help |
| 38 | Chooses frequency based on the recent load on the device. Works |
| 39 | similar as ONDEMAND governor of CPUFREQ does. A device with |
| 40 | Simple-Ondemand should be able to provide busy/total counter |
| 41 | values that imply the usage rate. A device may provide tuned |
| 42 | values to the governor with data field at devfreq_add_device(). |
| 43 | |
| 44 | config DEVFREQ_GOV_PERFORMANCE |
Nishanth Menon | eff607f | 2012-10-29 15:01:46 -0500 | [diff] [blame] | 45 | tristate "Performance" |
MyungJoo Ham | ce26c5b | 2011-10-02 00:19:34 +0200 | [diff] [blame] | 46 | help |
| 47 | Sets the frequency at the maximum available frequency. |
| 48 | This governor always returns UINT_MAX as frequency so that |
| 49 | the DEVFREQ framework returns the highest frequency available |
| 50 | at any time. |
| 51 | |
| 52 | config DEVFREQ_GOV_POWERSAVE |
Nishanth Menon | eff607f | 2012-10-29 15:01:46 -0500 | [diff] [blame] | 53 | tristate "Powersave" |
MyungJoo Ham | ce26c5b | 2011-10-02 00:19:34 +0200 | [diff] [blame] | 54 | help |
| 55 | Sets the frequency at the minimum available frequency. |
| 56 | This governor always returns 0 as frequency so that |
| 57 | the DEVFREQ framework returns the lowest frequency available |
| 58 | at any time. |
| 59 | |
| 60 | config DEVFREQ_GOV_USERSPACE |
Nishanth Menon | eff607f | 2012-10-29 15:01:46 -0500 | [diff] [blame] | 61 | tristate "Userspace" |
MyungJoo Ham | ce26c5b | 2011-10-02 00:19:34 +0200 | [diff] [blame] | 62 | help |
| 63 | Sets the frequency at the user specified one. |
| 64 | This governor returns the user configured frequency if there |
Dong Aisheng | 5f104f9 | 2021-03-09 20:58:33 +0800 | [diff] [blame] | 65 | has been an input to /sys/devices/.../userspace/set_freq. |
Geert Uytterhoeven | 027b693 | 2016-03-14 16:29:02 +0100 | [diff] [blame] | 66 | Otherwise, the governor does not change the frequency |
MyungJoo Ham | ce26c5b | 2011-10-02 00:19:34 +0200 | [diff] [blame] | 67 | given at the initialization. |
| 68 | |
Chanwoo Choi | 9961331 | 2016-03-22 13:44:03 +0900 | [diff] [blame] | 69 | config DEVFREQ_GOV_PASSIVE |
| 70 | tristate "Passive" |
| 71 | help |
| 72 | Sets the frequency based on the frequency of its parent devfreq |
| 73 | device. This governor does not change the frequency by itself |
| 74 | through sysfs entries. The passive governor recommends that |
| 75 | devfreq device uses the OPP table to get the frequency/voltage. |
| 76 | |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 77 | comment "DEVFREQ Drivers" |
| 78 | |
Chanwoo Choi | 0722249 | 2015-11-03 19:04:16 +0900 | [diff] [blame] | 79 | config ARM_EXYNOS_BUS_DEVFREQ |
Krzysztof Kozlowski | 91d7f3f | 2020-01-04 16:21:00 +0100 | [diff] [blame] | 80 | tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver" |
Krzysztof Kozlowski | 797da55 | 2016-08-19 08:36:55 +0200 | [diff] [blame] | 81 | depends on ARCH_EXYNOS || COMPILE_TEST |
Chanwoo Choi | 0722249 | 2015-11-03 19:04:16 +0900 | [diff] [blame] | 82 | select DEVFREQ_GOV_SIMPLE_ONDEMAND |
Chanwoo Choi | 403e068 | 2015-11-05 18:29:27 +0900 | [diff] [blame] | 83 | select DEVFREQ_GOV_PASSIVE |
Chanwoo Choi | 0722249 | 2015-11-03 19:04:16 +0900 | [diff] [blame] | 84 | select DEVFREQ_EVENT_EXYNOS_PPMU |
| 85 | select PM_DEVFREQ_EVENT |
Chanwoo Choi | 0722249 | 2015-11-03 19:04:16 +0900 | [diff] [blame] | 86 | help |
| 87 | This adds the common DEVFREQ driver for Exynos Memory bus. Exynos |
| 88 | Memory bus has one more group of memory bus (e.g, MIF and INT block). |
| 89 | Each memory bus group could contain many memoby bus block. It reads |
| 90 | PPMU counters of memory controllers by using DEVFREQ-event device |
| 91 | and adjusts the operating frequencies and voltages with OPP support. |
| 92 | This does not yet operate with optimal voltages. |
| 93 | |
Leonard Crestez | 5173a97 | 2020-04-06 15:03:07 +0300 | [diff] [blame] | 94 | config ARM_IMX_BUS_DEVFREQ |
| 95 | tristate "i.MX Generic Bus DEVFREQ Driver" |
| 96 | depends on ARCH_MXC || COMPILE_TEST |
| 97 | select DEVFREQ_GOV_USERSPACE |
| 98 | help |
| 99 | This adds the generic DEVFREQ driver for i.MX interconnects. It |
| 100 | allows adjusting NIC/NOC frequency. |
| 101 | |
Leonard Crestez | 5af744e | 2019-11-22 23:45:03 +0200 | [diff] [blame] | 102 | config ARM_IMX8M_DDRC_DEVFREQ |
| 103 | tristate "i.MX8M DDRC DEVFREQ Driver" |
| 104 | depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \ |
| 105 | (COMPILE_TEST && HAVE_ARM_SMCCC) |
Leonard Crestez | 5af744e | 2019-11-22 23:45:03 +0200 | [diff] [blame] | 106 | select DEVFREQ_GOV_USERSPACE |
| 107 | help |
| 108 | This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows |
| 109 | adjusting DRAM frequency. |
| 110 | |
Tomeu Vizoso | 6234f38 | 2014-11-24 13:28:17 +0100 | [diff] [blame] | 111 | config ARM_TEGRA_DEVFREQ |
Dmitry Osipenko | 1ac3474 | 2019-05-02 02:38:12 +0300 | [diff] [blame] | 112 | tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver" |
| 113 | depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \ |
| 114 | ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \ |
Dmitry Osipenko | 35f8dbc | 2019-05-02 02:38:13 +0300 | [diff] [blame] | 115 | ARCH_TEGRA_210_SOC || \ |
| 116 | COMPILE_TEST |
Arnd Bergmann | 5fdb068 | 2019-12-12 10:56:31 +0900 | [diff] [blame] | 117 | depends on COMMON_CLK |
Jisheng Zhang | 989a0fc | 2016-08-25 20:06:14 +0800 | [diff] [blame] | 118 | help |
| 119 | This adds the DEVFREQ driver for the Tegra family of SoCs. |
| 120 | It reads ACTMON counters of memory controllers and adjusts the |
| 121 | operating frequencies and voltages with OPP support. |
Tomeu Vizoso | 6234f38 | 2014-11-24 13:28:17 +0100 | [diff] [blame] | 122 | |
Lin Huang | 5a893e3 | 2016-09-05 13:06:10 +0800 | [diff] [blame] | 123 | config ARM_RK3399_DMC_DEVFREQ |
| 124 | tristate "ARM RK3399 DMC DEVFREQ Driver" |
Chanwoo Choi | eff5d31 | 2019-12-12 11:20:30 +0900 | [diff] [blame] | 125 | depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ |
| 126 | (COMPILE_TEST && HAVE_ARM_SMCCC) |
Lin Huang | 5a893e3 | 2016-09-05 13:06:10 +0800 | [diff] [blame] | 127 | select DEVFREQ_EVENT_ROCKCHIP_DFI |
| 128 | select DEVFREQ_GOV_SIMPLE_ONDEMAND |
Arnd Bergmann | 54dec69 | 2016-09-15 17:44:58 +0200 | [diff] [blame] | 129 | select PM_DEVFREQ_EVENT |
Lin Huang | 5a893e3 | 2016-09-05 13:06:10 +0800 | [diff] [blame] | 130 | help |
Krzysztof Kozlowski | d96c60b | 2019-11-20 21:42:16 +0800 | [diff] [blame] | 131 | This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller). |
| 132 | It sets the frequency for the memory controller and reads the usage counts |
| 133 | from hardware. |
Lin Huang | 5a893e3 | 2016-09-05 13:06:10 +0800 | [diff] [blame] | 134 | |
Samuel Holland | 8bfd485 | 2021-11-17 21:18:41 -0600 | [diff] [blame] | 135 | config ARM_SUN8I_A33_MBUS_DEVFREQ |
| 136 | tristate "sun8i/sun50i MBUS DEVFREQ Driver" |
| 137 | depends on ARCH_SUNXI || COMPILE_TEST |
Arnd Bergmann | a4b3c62 | 2021-12-15 15:03:09 +0100 | [diff] [blame] | 138 | depends on COMMON_CLK |
Samuel Holland | 8bfd485 | 2021-11-17 21:18:41 -0600 | [diff] [blame] | 139 | select DEVFREQ_GOV_SIMPLE_ONDEMAND |
| 140 | help |
| 141 | This adds the DEVFREQ driver for the MBUS controller in some |
| 142 | Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. |
| 143 | |
Chanwoo Choi | f262f28 | 2015-01-26 13:16:27 +0900 | [diff] [blame] | 144 | source "drivers/devfreq/event/Kconfig" |
| 145 | |
MyungJoo Ham | a3c98b8 | 2011-10-02 00:19:15 +0200 | [diff] [blame] | 146 | endif # PM_DEVFREQ |