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Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
MyungJoo Hama3c98b82011-10-02 00:19:15 +02002menuconfig PM_DEVFREQ
3 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
Pranith Kumar83fe27e2014-12-05 11:24:45 -05004 select SRCU
Chanwoo Choib9c69e02017-08-24 10:42:51 +09005 select PM_OPP
MyungJoo Hama3c98b82011-10-02 00:19:15 +02006 help
MyungJoo Ham6c81f902011-11-14 23:31:35 +01007 A device may have a list of frequencies and voltages available.
8 devfreq, a generic DVFS framework can be registered for a device
9 in order to let the governor provided to devfreq choose an
10 operating frequency based on the device driver's policy.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020011
MyungJoo Ham6c81f902011-11-14 23:31:35 +010012 Each device may have its own governor and policy. Devfreq can
MyungJoo Hama3c98b82011-10-02 00:19:15 +020013 reevaluate the device state periodically and/or based on the
MyungJoo Ham6c81f902011-11-14 23:31:35 +010014 notification to "nb", a notifier block, of devfreq.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020015
MyungJoo Ham6c81f902011-11-14 23:31:35 +010016 Like some CPUs with CPUfreq, a device may have multiple clocks.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020017 However, because the clock frequencies of a single device are
MyungJoo Ham6c81f902011-11-14 23:31:35 +010018 determined by the single device's state, an instance of devfreq
MyungJoo Hama3c98b82011-10-02 00:19:15 +020019 is attached to a single device and returns a "representative"
MyungJoo Ham6c81f902011-11-14 23:31:35 +010020 clock frequency of the device, which is also attached
21 to a device by 1-to-1. The device registering devfreq takes the
Masanari Iida6b2aac42012-04-14 00:14:11 +090022 responsibility to "interpret" the representative frequency and
MyungJoo Hama3c98b82011-10-02 00:19:15 +020023 to set its every clock accordingly with the "target" callback
MyungJoo Ham6c81f902011-11-14 23:31:35 +010024 given to devfreq.
25
26 When OPP is used with the devfreq device, it is recommended to
27 register devfreq's nb to the OPP's notifier head. If OPP is
28 used with the devfreq device, you may use OPP helper
29 functions defined in devfreq.h.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020030
31if PM_DEVFREQ
32
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020033comment "DEVFREQ Governors"
34
35config DEVFREQ_GOV_SIMPLE_ONDEMAND
Nishanth Menoneff607f2012-10-29 15:01:46 -050036 tristate "Simple Ondemand"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020037 help
38 Chooses frequency based on the recent load on the device. Works
39 similar as ONDEMAND governor of CPUFREQ does. A device with
40 Simple-Ondemand should be able to provide busy/total counter
41 values that imply the usage rate. A device may provide tuned
42 values to the governor with data field at devfreq_add_device().
43
44config DEVFREQ_GOV_PERFORMANCE
Nishanth Menoneff607f2012-10-29 15:01:46 -050045 tristate "Performance"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020046 help
47 Sets the frequency at the maximum available frequency.
48 This governor always returns UINT_MAX as frequency so that
49 the DEVFREQ framework returns the highest frequency available
50 at any time.
51
52config DEVFREQ_GOV_POWERSAVE
Nishanth Menoneff607f2012-10-29 15:01:46 -050053 tristate "Powersave"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020054 help
55 Sets the frequency at the minimum available frequency.
56 This governor always returns 0 as frequency so that
57 the DEVFREQ framework returns the lowest frequency available
58 at any time.
59
60config DEVFREQ_GOV_USERSPACE
Nishanth Menoneff607f2012-10-29 15:01:46 -050061 tristate "Userspace"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020062 help
63 Sets the frequency at the user specified one.
64 This governor returns the user configured frequency if there
Dong Aisheng5f104f92021-03-09 20:58:33 +080065 has been an input to /sys/devices/.../userspace/set_freq.
Geert Uytterhoeven027b6932016-03-14 16:29:02 +010066 Otherwise, the governor does not change the frequency
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020067 given at the initialization.
68
Chanwoo Choi99613312016-03-22 13:44:03 +090069config DEVFREQ_GOV_PASSIVE
70 tristate "Passive"
71 help
72 Sets the frequency based on the frequency of its parent devfreq
73 device. This governor does not change the frequency by itself
74 through sysfs entries. The passive governor recommends that
75 devfreq device uses the OPP table to get the frequency/voltage.
76
MyungJoo Hama3c98b82011-10-02 00:19:15 +020077comment "DEVFREQ Drivers"
78
Chanwoo Choi07222492015-11-03 19:04:16 +090079config ARM_EXYNOS_BUS_DEVFREQ
Krzysztof Kozlowski91d7f3f2020-01-04 16:21:00 +010080 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
Krzysztof Kozlowski797da552016-08-19 08:36:55 +020081 depends on ARCH_EXYNOS || COMPILE_TEST
Chanwoo Choi07222492015-11-03 19:04:16 +090082 select DEVFREQ_GOV_SIMPLE_ONDEMAND
Chanwoo Choi403e0682015-11-05 18:29:27 +090083 select DEVFREQ_GOV_PASSIVE
Chanwoo Choi07222492015-11-03 19:04:16 +090084 select DEVFREQ_EVENT_EXYNOS_PPMU
85 select PM_DEVFREQ_EVENT
Chanwoo Choi07222492015-11-03 19:04:16 +090086 help
87 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
88 Memory bus has one more group of memory bus (e.g, MIF and INT block).
89 Each memory bus group could contain many memoby bus block. It reads
90 PPMU counters of memory controllers by using DEVFREQ-event device
91 and adjusts the operating frequencies and voltages with OPP support.
92 This does not yet operate with optimal voltages.
93
Leonard Crestez5173a972020-04-06 15:03:07 +030094config ARM_IMX_BUS_DEVFREQ
95 tristate "i.MX Generic Bus DEVFREQ Driver"
96 depends on ARCH_MXC || COMPILE_TEST
97 select DEVFREQ_GOV_USERSPACE
98 help
99 This adds the generic DEVFREQ driver for i.MX interconnects. It
100 allows adjusting NIC/NOC frequency.
101
Leonard Crestez5af744e2019-11-22 23:45:03 +0200102config ARM_IMX8M_DDRC_DEVFREQ
103 tristate "i.MX8M DDRC DEVFREQ Driver"
104 depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
105 (COMPILE_TEST && HAVE_ARM_SMCCC)
Leonard Crestez5af744e2019-11-22 23:45:03 +0200106 select DEVFREQ_GOV_USERSPACE
107 help
108 This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
109 adjusting DRAM frequency.
110
Tomeu Vizoso6234f382014-11-24 13:28:17 +0100111config ARM_TEGRA_DEVFREQ
Dmitry Osipenko1ac34742019-05-02 02:38:12 +0300112 tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
113 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
114 ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
Dmitry Osipenko35f8dbc2019-05-02 02:38:13 +0300115 ARCH_TEGRA_210_SOC || \
116 COMPILE_TEST
Arnd Bergmann5fdb0682019-12-12 10:56:31 +0900117 depends on COMMON_CLK
Jisheng Zhang989a0fc2016-08-25 20:06:14 +0800118 help
119 This adds the DEVFREQ driver for the Tegra family of SoCs.
120 It reads ACTMON counters of memory controllers and adjusts the
121 operating frequencies and voltages with OPP support.
Tomeu Vizoso6234f382014-11-24 13:28:17 +0100122
Lin Huang5a893e32016-09-05 13:06:10 +0800123config ARM_RK3399_DMC_DEVFREQ
124 tristate "ARM RK3399 DMC DEVFREQ Driver"
Chanwoo Choieff5d312019-12-12 11:20:30 +0900125 depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
126 (COMPILE_TEST && HAVE_ARM_SMCCC)
Lin Huang5a893e32016-09-05 13:06:10 +0800127 select DEVFREQ_EVENT_ROCKCHIP_DFI
128 select DEVFREQ_GOV_SIMPLE_ONDEMAND
Arnd Bergmann54dec692016-09-15 17:44:58 +0200129 select PM_DEVFREQ_EVENT
Lin Huang5a893e32016-09-05 13:06:10 +0800130 help
Krzysztof Kozlowskid96c60b2019-11-20 21:42:16 +0800131 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
132 It sets the frequency for the memory controller and reads the usage counts
133 from hardware.
Lin Huang5a893e32016-09-05 13:06:10 +0800134
Samuel Holland8bfd4852021-11-17 21:18:41 -0600135config ARM_SUN8I_A33_MBUS_DEVFREQ
136 tristate "sun8i/sun50i MBUS DEVFREQ Driver"
137 depends on ARCH_SUNXI || COMPILE_TEST
Arnd Bergmanna4b3c622021-12-15 15:03:09 +0100138 depends on COMMON_CLK
Samuel Holland8bfd4852021-11-17 21:18:41 -0600139 select DEVFREQ_GOV_SIMPLE_ONDEMAND
140 help
141 This adds the DEVFREQ driver for the MBUS controller in some
142 Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
143
Chanwoo Choif262f282015-01-26 13:16:27 +0900144source "drivers/devfreq/event/Kconfig"
145
MyungJoo Hama3c98b82011-10-02 00:19:15 +0200146endif # PM_DEVFREQ