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Hannes Reinecke3a7e7be2014-11-24 15:37:25 +01001/*
2 * AMD am53c974 driver.
3 * Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/init.h>
9#include <linux/delay.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12
13#include <scsi/scsi_host.h>
14
15#include "esp_scsi.h"
16
17#define DRV_MODULE_NAME "am53c974"
18#define DRV_MODULE_VERSION "1.00"
19
20static bool am53c974_debug;
21
22#define esp_dma_log(f, a...) \
23 do { \
24 if (am53c974_debug) \
25 shost_printk(KERN_DEBUG, esp->host, f, ##a); \
26 } while (0)
27
28#define ESP_DMA_CMD 0x10
29#define ESP_DMA_STC 0x11
30#define ESP_DMA_SPA 0x12
31#define ESP_DMA_WBC 0x13
32#define ESP_DMA_WAC 0x14
33#define ESP_DMA_STATUS 0x15
34#define ESP_DMA_SMDLA 0x16
35#define ESP_DMA_WMAC 0x17
36
37#define ESP_DMA_CMD_IDLE 0x00
38#define ESP_DMA_CMD_BLAST 0x01
39#define ESP_DMA_CMD_ABORT 0x02
40#define ESP_DMA_CMD_START 0x03
41#define ESP_DMA_CMD_MASK 0x03
42#define ESP_DMA_CMD_DIAG 0x04
43#define ESP_DMA_CMD_MDL 0x10
44#define ESP_DMA_CMD_INTE_P 0x20
45#define ESP_DMA_CMD_INTE_D 0x40
46#define ESP_DMA_CMD_DIR 0x80
47
48#define ESP_DMA_STAT_PWDN 0x01
49#define ESP_DMA_STAT_ERROR 0x02
50#define ESP_DMA_STAT_ABORT 0x04
51#define ESP_DMA_STAT_DONE 0x08
52#define ESP_DMA_STAT_SCSIINT 0x10
53#define ESP_DMA_STAT_BCMPLT 0x20
54
55/* EEPROM is accessed with 16-bit values */
56#define DC390_EEPROM_READ 0x80
57#define DC390_EEPROM_LEN 0x40
58
59/*
60 * DC390 EEPROM
61 *
62 * 8 * 4 bytes of per-device options
63 * followed by HBA specific options
64 */
65
66/* Per-device options */
67#define DC390_EE_MODE1 0x00
68#define DC390_EE_SPEED 0x01
69
70/* HBA-specific options */
71#define DC390_EE_ADAPT_SCSI_ID 0x40
72#define DC390_EE_MODE2 0x41
73#define DC390_EE_DELAY 0x42
74#define DC390_EE_TAG_CMD_NUM 0x43
75
76#define DC390_EE_MODE1_PARITY_CHK 0x01
77#define DC390_EE_MODE1_SYNC_NEGO 0x02
78#define DC390_EE_MODE1_EN_DISC 0x04
79#define DC390_EE_MODE1_SEND_START 0x08
80#define DC390_EE_MODE1_TCQ 0x10
81
82#define DC390_EE_MODE2_MORE_2DRV 0x01
83#define DC390_EE_MODE2_GREATER_1G 0x02
84#define DC390_EE_MODE2_RST_SCSI_BUS 0x04
85#define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
86#define DC390_EE_MODE2_NO_SEEK 0x10
87#define DC390_EE_MODE2_LUN_CHECK 0x20
88
89struct pci_esp_priv {
90 struct esp *esp;
91 u8 dma_status;
92};
93
94static void pci_esp_dma_drain(struct esp *esp);
95
96static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp)
97{
98 struct pci_dev *pdev = esp->dev;
99
100 return pci_get_drvdata(pdev);
101}
102
103static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
104{
105 iowrite8(val, esp->regs + (reg * 4UL));
106}
107
108static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
109{
110 return ioread8(esp->regs + (reg * 4UL));
111}
112
113static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
114{
115 return iowrite32(val, esp->regs + (reg * 4UL));
116}
117
118static dma_addr_t pci_esp_map_single(struct esp *esp, void *buf,
119 size_t sz, int dir)
120{
121 return pci_map_single(esp->dev, buf, sz, dir);
122}
123
124static int pci_esp_map_sg(struct esp *esp, struct scatterlist *sg,
125 int num_sg, int dir)
126{
127 return pci_map_sg(esp->dev, sg, num_sg, dir);
128}
129
130static void pci_esp_unmap_single(struct esp *esp, dma_addr_t addr,
131 size_t sz, int dir)
132{
133 pci_unmap_single(esp->dev, addr, sz, dir);
134}
135
136static void pci_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
137 int num_sg, int dir)
138{
139 pci_unmap_sg(esp->dev, sg, num_sg, dir);
140}
141
142static int pci_esp_irq_pending(struct esp *esp)
143{
144 struct pci_esp_priv *pep = pci_esp_get_priv(esp);
145
146 pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
147 esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);
148
149 if (pep->dma_status & (ESP_DMA_STAT_ERROR |
150 ESP_DMA_STAT_ABORT |
151 ESP_DMA_STAT_DONE |
152 ESP_DMA_STAT_SCSIINT))
153 return 1;
154
155 return 0;
156}
157
158static void pci_esp_reset_dma(struct esp *esp)
159{
160 /* Nothing to do ? */
161}
162
163static void pci_esp_dma_drain(struct esp *esp)
164{
165 u8 resid;
166 int lim = 1000;
167
168
169 if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP ||
170 (esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
171 /* Data-In or Data-Out, nothing to be done */
172 return;
173
174 while (--lim > 0) {
175 resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
176 if (resid <= 1)
177 break;
178 cpu_relax();
179 }
180 if (resid > 1) {
181 /* FIFO not cleared */
182 shost_printk(KERN_INFO, esp->host,
183 "FIFO not cleared, %d bytes left\n",
184 resid);
185 }
186
187 /*
188 * When there is a residual BCMPLT will never be set
189 * (obviously). But we still have to issue the BLAST
190 * command, otherwise the data will not being transferred.
191 * But we'll never know when the BLAST operation is
192 * finished. So check for some time and give up eventually.
193 */
194 lim = 1000;
195 pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
196 while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
197 if (--lim == 0)
198 break;
199 cpu_relax();
200 }
201 pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
202 esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
Hannes Reinecke6df388f2014-11-24 15:37:26 +0100203 /* BLAST residual handling is currently untested */
204 if (WARN_ON_ONCE(resid == 1)) {
205 struct esp_cmd_entry *ent = esp->active_cmd;
206
207 ent->flags |= ESP_CMD_FLAG_RESIDUAL;
208 }
Hannes Reinecke3a7e7be2014-11-24 15:37:25 +0100209}
210
211static void pci_esp_dma_invalidate(struct esp *esp)
212{
213 struct pci_esp_priv *pep = pci_esp_get_priv(esp);
214
215 esp_dma_log("invalidate DMA\n");
216
217 pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
218 pep->dma_status = 0;
219}
220
221static int pci_esp_dma_error(struct esp *esp)
222{
223 struct pci_esp_priv *pep = pci_esp_get_priv(esp);
224
225 if (pep->dma_status & ESP_DMA_STAT_ERROR) {
226 u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);
227
228 if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
229 pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);
230
231 return 1;
232 }
233 if (pep->dma_status & ESP_DMA_STAT_ABORT) {
234 pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
235 pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
236 return 1;
237 }
238 return 0;
239}
240
241static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
242 u32 dma_count, int write, u8 cmd)
243{
244 struct pci_esp_priv *pep = pci_esp_get_priv(esp);
245 u32 val = 0;
246
247 BUG_ON(!(cmd & ESP_CMD_DMA));
248
249 pep->dma_status = 0;
250
251 /* Set DMA engine to IDLE */
252 if (write)
253 /* DMA write direction logic is inverted */
254 val |= ESP_DMA_CMD_DIR;
255 pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD);
256
257 pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
258 pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
259
260 pci_esp_write32(esp, esp_count, ESP_DMA_STC);
261 pci_esp_write32(esp, addr, ESP_DMA_SPA);
262
263 esp_dma_log("start dma addr[%x] count[%d:%d]\n",
264 addr, esp_count, dma_count);
265
266 scsi_esp_cmd(esp, cmd);
267 /* Send DMA Start command */
268 pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD);
269}
270
271static const struct esp_driver_ops pci_esp_ops = {
272 .esp_write8 = pci_esp_write8,
273 .esp_read8 = pci_esp_read8,
274 .map_single = pci_esp_map_single,
275 .map_sg = pci_esp_map_sg,
276 .unmap_single = pci_esp_unmap_single,
277 .unmap_sg = pci_esp_unmap_sg,
278 .irq_pending = pci_esp_irq_pending,
279 .reset_dma = pci_esp_reset_dma,
280 .dma_drain = pci_esp_dma_drain,
281 .dma_invalidate = pci_esp_dma_invalidate,
282 .send_dma_cmd = pci_esp_send_dma_cmd,
283 .dma_error = pci_esp_dma_error,
284};
285
286/*
287 * Read DC-390 eeprom
288 */
289static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd)
290{
291 u8 carry_flag = 1, j = 0x80, bval;
292 int i;
293
294 for (i = 0; i < 9; i++) {
295 if (carry_flag) {
296 pci_write_config_byte(pdev, 0x80, 0x40);
297 bval = 0xc0;
298 } else
299 bval = 0x80;
300
301 udelay(160);
302 pci_write_config_byte(pdev, 0x80, bval);
303 udelay(160);
304 pci_write_config_byte(pdev, 0x80, 0);
305 udelay(160);
306
307 carry_flag = (cmd & j) ? 1 : 0;
308 j >>= 1;
309 }
310}
311
312static u16 dc390_eeprom_get_data(struct pci_dev *pdev)
313{
314 int i;
315 u16 wval = 0;
316 u8 bval;
317
318 for (i = 0; i < 16; i++) {
319 wval <<= 1;
320
321 pci_write_config_byte(pdev, 0x80, 0x80);
322 udelay(160);
323 pci_write_config_byte(pdev, 0x80, 0x40);
324 udelay(160);
325 pci_read_config_byte(pdev, 0x00, &bval);
326
327 if (bval == 0x22)
328 wval |= 1;
329 }
330
331 return wval;
332}
333
334static void dc390_read_eeprom(struct pci_dev *pdev, u16 *ptr)
335{
336 u8 cmd = DC390_EEPROM_READ, i;
337
338 for (i = 0; i < DC390_EEPROM_LEN; i++) {
339 pci_write_config_byte(pdev, 0xc0, 0);
340 udelay(160);
341
342 dc390_eeprom_prepare_read(pdev, cmd++);
343 *ptr++ = dc390_eeprom_get_data(pdev);
344
345 pci_write_config_byte(pdev, 0x80, 0);
346 pci_write_config_byte(pdev, 0x80, 0);
347 udelay(160);
348 }
349}
350
351static void dc390_check_eeprom(struct esp *esp)
352{
353 u8 EEbuf[128];
354 u16 *ptr = (u16 *)EEbuf, wval = 0;
355 int i;
356
357 dc390_read_eeprom((struct pci_dev *)esp->dev, ptr);
358
359 for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++)
360 wval += *ptr;
361
362 /* no Tekram EEprom found */
363 if (wval != 0x1234) {
364 struct pci_dev *pdev = esp->dev;
365 dev_printk(KERN_INFO, &pdev->dev,
366 "No valid Tekram EEprom found\n");
367 return;
368 }
369 esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID];
370 esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM];
371}
372
373static int pci_esp_probe_one(struct pci_dev *pdev,
374 const struct pci_device_id *id)
375{
376 struct scsi_host_template *hostt = &scsi_esp_template;
377 int err = -ENODEV;
378 struct Scsi_Host *shost;
379 struct esp *esp;
380 struct pci_esp_priv *pep;
381
382 if (pci_enable_device(pdev)) {
383 dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n");
384 return -ENODEV;
385 }
386
387 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
388 dev_printk(KERN_INFO, &pdev->dev,
389 "failed to set 32bit DMA mask\n");
390 goto fail_disable_device;
391 }
392
393 shost = scsi_host_alloc(hostt, sizeof(struct esp));
394 if (!shost) {
395 dev_printk(KERN_INFO, &pdev->dev,
396 "failed to allocate scsi host\n");
397 err = -ENOMEM;
398 goto fail_disable_device;
399 }
400
401 pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL);
402 if (!pep) {
403 dev_printk(KERN_INFO, &pdev->dev,
404 "failed to allocate esp_priv\n");
405 err = -ENOMEM;
406 goto fail_host_alloc;
407 }
408
409 esp = shost_priv(shost);
410 esp->host = shost;
411 esp->dev = pdev;
412 esp->ops = &pci_esp_ops;
413 /*
414 * The am53c974 HBA has a design flaw of generating
415 * spurious DMA completion interrupts when using
416 * DMA for command submission.
417 */
418 esp->flags |= ESP_FLAG_USE_FIFO;
419 pep->esp = esp;
420
421 if (pci_request_regions(pdev, DRV_MODULE_NAME)) {
422 dev_printk(KERN_ERR, &pdev->dev,
423 "pci memory selection failed\n");
424 goto fail_priv_alloc;
425 }
426
427 esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
428 if (!esp->regs) {
429 dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n");
430 err = -EINVAL;
431 goto fail_release_regions;
432 }
433 esp->dma_regs = esp->regs;
434
435 pci_set_master(pdev);
436
437 esp->command_block = pci_alloc_consistent(pdev, 16,
438 &esp->command_block_dma);
439 if (!esp->command_block) {
440 dev_printk(KERN_ERR, &pdev->dev,
441 "failed to allocate command block\n");
442 err = -ENOMEM;
443 goto fail_unmap_regs;
444 }
445
446 err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED,
447 DRV_MODULE_NAME, esp);
448 if (err < 0) {
449 dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n");
450 goto fail_unmap_command_block;
451 }
452
453 esp->scsi_id = 7;
454 dc390_check_eeprom(esp);
455
456 shost->this_id = esp->scsi_id;
457 shost->max_id = 8;
458 shost->irq = pdev->irq;
459 shost->io_port = pci_resource_start(pdev, 0);
460 shost->n_io_port = pci_resource_len(pdev, 0);
461 shost->unique_id = shost->io_port;
462 esp->scsi_id_mask = (1 << esp->scsi_id);
463 /* Assume 40MHz clock */
464 esp->cfreq = 40000000;
465
466 pci_set_drvdata(pdev, pep);
467
468 err = scsi_esp_register(esp, &pdev->dev);
469 if (err)
470 goto fail_free_irq;
471
472 return 0;
473
474fail_free_irq:
475 free_irq(pdev->irq, esp);
476fail_unmap_command_block:
477 pci_free_consistent(pdev, 16, esp->command_block,
478 esp->command_block_dma);
479fail_unmap_regs:
480 pci_iounmap(pdev, esp->regs);
481fail_release_regions:
482 pci_release_regions(pdev);
483fail_priv_alloc:
484 kfree(pep);
485fail_host_alloc:
486 scsi_host_put(shost);
487fail_disable_device:
488 pci_disable_device(pdev);
489
490 return err;
491}
492
493static void pci_esp_remove_one(struct pci_dev *pdev)
494{
495 struct pci_esp_priv *pep = pci_get_drvdata(pdev);
496 struct esp *esp = pep->esp;
497
498 scsi_esp_unregister(esp);
499 free_irq(pdev->irq, esp);
500 pci_free_consistent(pdev, 16, esp->command_block,
501 esp->command_block_dma);
502 pci_iounmap(pdev, esp->regs);
503 pci_release_regions(pdev);
504 pci_disable_device(pdev);
505 kfree(pep);
506
507 scsi_host_put(esp->host);
508}
509
510static struct pci_device_id am53c974_pci_tbl[] = {
511 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI,
512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
513 { }
514};
515MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl);
516
517static struct pci_driver am53c974_driver = {
518 .name = DRV_MODULE_NAME,
519 .id_table = am53c974_pci_tbl,
520 .probe = pci_esp_probe_one,
521 .remove = pci_esp_remove_one,
522};
523
524static int __init am53c974_module_init(void)
525{
526 return pci_register_driver(&am53c974_driver);
527}
528
529static void __exit am53c974_module_exit(void)
530{
531 pci_unregister_driver(&am53c974_driver);
532}
533
534MODULE_DESCRIPTION("AM53C974 SCSI driver");
535MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
536MODULE_LICENSE("GPL");
537MODULE_VERSION(DRV_MODULE_VERSION);
538
539module_param(am53c974_debug, bool, 0644);
540MODULE_PARM_DESC(am53c974_debug, "Enable debugging");
541
542module_init(am53c974_module_init);
543module_exit(am53c974_module_exit);