| Andy Shevchenko | b466a37 | 2019-01-07 13:07:41 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 3 | # |
| 4 | # DMA engine configuration for dw |
| 5 | # |
| 6 | |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 7 | config DW_DMAC_CORE |
| Vinod Koul | cdde0e6 | 2015-04-22 12:24:13 +0530 | [diff] [blame] | 8 | tristate |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 9 | select DMA_ENGINE |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 10 | |
| 11 | config DW_DMAC |
| 12 | tristate "Synopsys DesignWare AHB DMA platform driver" |
| Andy Shevchenko | 88cd1d6 | 2021-03-24 16:17:57 +0200 | [diff] [blame] | 13 | depends on HAS_IOMEM |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 14 | select DW_DMAC_CORE |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 15 | help |
| 16 | Support the Synopsys DesignWare AHB DMA controller. This |
| Andy Shevchenko | 14bebd0 | 2017-05-09 19:18:37 +0300 | [diff] [blame] | 17 | can be integrated in chips such as the Intel Cherrytrail. |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 18 | |
| Andy Shevchenko | fed42c1 | 2013-06-05 15:26:46 +0300 | [diff] [blame] | 19 | config DW_DMAC_PCI |
| 20 | tristate "Synopsys DesignWare AHB DMA PCI driver" |
| 21 | depends on PCI |
| Andy Shevchenko | 88cd1d6 | 2021-03-24 16:17:57 +0200 | [diff] [blame] | 22 | depends on HAS_IOMEM |
| Andy Shevchenko | fed42c1 | 2013-06-05 15:26:46 +0300 | [diff] [blame] | 23 | select DW_DMAC_CORE |
| 24 | help |
| 25 | Support the Synopsys DesignWare AHB DMA controller on the |
| Jean Delvare | 1032471 | 2016-12-15 11:43:30 +0100 | [diff] [blame] | 26 | platforms that enumerate it as a PCI device. For example, |
| Andy Shevchenko | fed42c1 | 2013-06-05 15:26:46 +0300 | [diff] [blame] | 27 | Intel Medfield has integrated this GPDMA controller. |