Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2008 Juergen Beisert |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the |
| 16 | * Free Software Foundation |
| 17 | * 51 Franklin Street, Fifth Floor |
| 18 | * Boston, MA 02110-1301, USA. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/completion.h> |
| 23 | #include <linux/delay.h> |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 24 | #include <linux/dmaengine.h> |
| 25 | #include <linux/dma-mapping.h> |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 26 | #include <linux/err.h> |
| 27 | #include <linux/gpio.h> |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/io.h> |
| 30 | #include <linux/irq.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/platform_device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 35 | #include <linux/spi/spi.h> |
| 36 | #include <linux/spi/spi_bitbang.h> |
| 37 | #include <linux/types.h> |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 38 | #include <linux/of.h> |
| 39 | #include <linux/of_device.h> |
| 40 | #include <linux/of_gpio.h> |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 41 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 42 | #include <linux/platform_data/dma-imx.h> |
Arnd Bergmann | 82906b1 | 2012-08-24 15:14:29 +0200 | [diff] [blame] | 43 | #include <linux/platform_data/spi-imx.h> |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 44 | |
| 45 | #define DRIVER_NAME "spi_imx" |
| 46 | |
| 47 | #define MXC_CSPIRXDATA 0x00 |
| 48 | #define MXC_CSPITXDATA 0x04 |
| 49 | #define MXC_CSPICTRL 0x08 |
| 50 | #define MXC_CSPIINT 0x0c |
| 51 | #define MXC_RESET 0x1c |
| 52 | |
| 53 | /* generic defines to abstract from the different register layouts */ |
| 54 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ |
| 55 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ |
| 56 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 57 | /* The maximum bytes that a sdma BD can transfer.*/ |
| 58 | #define MAX_SDMA_BD_BYTES (1 << 15) |
| 59 | #define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000)) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 60 | struct spi_imx_config { |
| 61 | unsigned int speed_hz; |
| 62 | unsigned int bpw; |
| 63 | unsigned int mode; |
Uwe Kleine-König | 3b2aa89 | 2010-09-10 09:42:29 +0200 | [diff] [blame] | 64 | u8 cs; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 65 | }; |
| 66 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 67 | enum spi_imx_devtype { |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 68 | IMX1_CSPI, |
| 69 | IMX21_CSPI, |
| 70 | IMX27_CSPI, |
| 71 | IMX31_CSPI, |
| 72 | IMX35_CSPI, /* CSPI on all i.mx except above */ |
| 73 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | struct spi_imx_data; |
| 77 | |
| 78 | struct spi_imx_devtype_data { |
| 79 | void (*intctrl)(struct spi_imx_data *, int); |
| 80 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); |
| 81 | void (*trigger)(struct spi_imx_data *); |
| 82 | int (*rx_available)(struct spi_imx_data *); |
Uwe Kleine-König | 1723e66 | 2010-09-10 09:19:18 +0200 | [diff] [blame] | 83 | void (*reset)(struct spi_imx_data *); |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 84 | enum spi_imx_devtype devtype; |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 85 | }; |
| 86 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 87 | struct spi_imx_data { |
| 88 | struct spi_bitbang bitbang; |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 89 | struct device *dev; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 90 | |
| 91 | struct completion xfer_done; |
Uwe Kleine-König | cc4d22a | 2012-03-29 21:54:18 +0200 | [diff] [blame] | 92 | void __iomem *base; |
Sascha Hauer | aa29d840 | 2012-03-07 09:30:22 +0100 | [diff] [blame] | 93 | struct clk *clk_per; |
| 94 | struct clk *clk_ipg; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 95 | unsigned long spi_clk; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 96 | |
| 97 | unsigned int count; |
| 98 | void (*tx)(struct spi_imx_data *); |
| 99 | void (*rx)(struct spi_imx_data *); |
| 100 | void *rx_buf; |
| 101 | const void *tx_buf; |
| 102 | unsigned int txfifo; /* number of words pushed in tx FIFO */ |
| 103 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 104 | /* DMA */ |
| 105 | unsigned int dma_is_inited; |
| 106 | unsigned int dma_finished; |
| 107 | bool usedma; |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 108 | u32 wml; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 109 | struct completion dma_rx_completion; |
| 110 | struct completion dma_tx_completion; |
| 111 | |
Uwe Kleine-König | 80023cb | 2012-05-21 21:49:35 +0200 | [diff] [blame] | 112 | const struct spi_imx_devtype_data *devtype_data; |
Shawn Guo | c2387cb | 2011-07-10 01:16:40 +0800 | [diff] [blame] | 113 | int chipselect[0]; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 114 | }; |
| 115 | |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 116 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
| 117 | { |
| 118 | return d->devtype_data->devtype == IMX27_CSPI; |
| 119 | } |
| 120 | |
| 121 | static inline int is_imx35_cspi(struct spi_imx_data *d) |
| 122 | { |
| 123 | return d->devtype_data->devtype == IMX35_CSPI; |
| 124 | } |
| 125 | |
Anton Bondarenko | f8a87617 | 2015-12-05 17:57:02 +0100 | [diff] [blame] | 126 | static inline int is_imx51_ecspi(struct spi_imx_data *d) |
| 127 | { |
| 128 | return d->devtype_data->devtype == IMX51_ECSPI; |
| 129 | } |
| 130 | |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 131 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) |
| 132 | { |
Anton Bondarenko | f8a87617 | 2015-12-05 17:57:02 +0100 | [diff] [blame] | 133 | return is_imx51_ecspi(d) ? 64 : 8; |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 134 | } |
| 135 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 136 | #define MXC_SPI_BUF_RX(type) \ |
| 137 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
| 138 | { \ |
| 139 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
| 140 | \ |
| 141 | if (spi_imx->rx_buf) { \ |
| 142 | *(type *)spi_imx->rx_buf = val; \ |
| 143 | spi_imx->rx_buf += sizeof(type); \ |
| 144 | } \ |
| 145 | } |
| 146 | |
| 147 | #define MXC_SPI_BUF_TX(type) \ |
| 148 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
| 149 | { \ |
| 150 | type val = 0; \ |
| 151 | \ |
| 152 | if (spi_imx->tx_buf) { \ |
| 153 | val = *(type *)spi_imx->tx_buf; \ |
| 154 | spi_imx->tx_buf += sizeof(type); \ |
| 155 | } \ |
| 156 | \ |
| 157 | spi_imx->count -= sizeof(type); \ |
| 158 | \ |
| 159 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
| 160 | } |
| 161 | |
| 162 | MXC_SPI_BUF_RX(u8) |
| 163 | MXC_SPI_BUF_TX(u8) |
| 164 | MXC_SPI_BUF_RX(u16) |
| 165 | MXC_SPI_BUF_TX(u16) |
| 166 | MXC_SPI_BUF_RX(u32) |
| 167 | MXC_SPI_BUF_TX(u32) |
| 168 | |
| 169 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set |
| 170 | * (which is currently not the case in this driver) |
| 171 | */ |
| 172 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, |
| 173 | 256, 384, 512, 768, 1024}; |
| 174 | |
| 175 | /* MX21, MX27 */ |
| 176 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 177 | unsigned int fspi, unsigned int max) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 178 | { |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 179 | int i; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 180 | |
| 181 | for (i = 2; i < max; i++) |
| 182 | if (fspi * mxc_clkdivs[i] >= fin) |
| 183 | return i; |
| 184 | |
| 185 | return max; |
| 186 | } |
| 187 | |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 188 | /* MX1, MX31, MX35, MX51 CSPI */ |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 189 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
| 190 | unsigned int fspi) |
| 191 | { |
| 192 | int i, div = 4; |
| 193 | |
| 194 | for (i = 0; i < 7; i++) { |
| 195 | if (fspi * div >= fin) |
| 196 | return i; |
| 197 | div <<= 1; |
| 198 | } |
| 199 | |
| 200 | return 7; |
| 201 | } |
| 202 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 203 | static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, |
| 204 | struct spi_transfer *transfer) |
| 205 | { |
| 206 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
| 207 | |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 208 | if (spi_imx->dma_is_inited && |
| 209 | transfer->len > spi_imx->wml * sizeof(u32)) |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 210 | return true; |
| 211 | return false; |
| 212 | } |
| 213 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 214 | #define MX51_ECSPI_CTRL 0x08 |
| 215 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) |
| 216 | #define MX51_ECSPI_CTRL_XCH (1 << 2) |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 217 | #define MX51_ECSPI_CTRL_SMC (1 << 3) |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 218 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) |
| 219 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 |
| 220 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 |
| 221 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) |
| 222 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 223 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 224 | #define MX51_ECSPI_CONFIG 0x0c |
| 225 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) |
| 226 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) |
| 227 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) |
| 228 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) |
Knut Wohlrab | c09b890 | 2012-09-25 13:21:57 +0200 | [diff] [blame] | 229 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 230 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 231 | #define MX51_ECSPI_INT 0x10 |
| 232 | #define MX51_ECSPI_INT_TEEN (1 << 0) |
| 233 | #define MX51_ECSPI_INT_RREN (1 << 3) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 234 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 235 | #define MX51_ECSPI_DMA 0x14 |
| 236 | #define MX51_ECSPI_DMA_TX_WML_OFFSET 0 |
| 237 | #define MX51_ECSPI_DMA_TX_WML_MASK 0x3F |
| 238 | #define MX51_ECSPI_DMA_RX_WML_OFFSET 16 |
| 239 | #define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16) |
| 240 | #define MX51_ECSPI_DMA_RXT_WML_OFFSET 24 |
| 241 | #define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24) |
| 242 | |
| 243 | #define MX51_ECSPI_DMA_TEDEN_OFFSET 7 |
| 244 | #define MX51_ECSPI_DMA_RXDEN_OFFSET 23 |
| 245 | #define MX51_ECSPI_DMA_RXTDEN_OFFSET 31 |
| 246 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 247 | #define MX51_ECSPI_STAT 0x18 |
| 248 | #define MX51_ECSPI_STAT_RR (1 << 3) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 249 | |
Fabio Estevam | 9f6aa42 | 2015-12-03 23:23:24 -0200 | [diff] [blame] | 250 | #define MX51_ECSPI_TESTREG 0x20 |
| 251 | #define MX51_ECSPI_TESTREG_LBC BIT(31) |
| 252 | |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 253 | /* MX51 eCSPI */ |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 254 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
| 255 | unsigned int fspi, unsigned int *fres) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 256 | { |
| 257 | /* |
| 258 | * there are two 4-bit dividers, the pre-divider divides by |
| 259 | * $pre, the post-divider by 2^$post |
| 260 | */ |
| 261 | unsigned int pre, post; |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 262 | unsigned int fin = spi_imx->spi_clk; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 263 | |
| 264 | if (unlikely(fspi > fin)) |
| 265 | return 0; |
| 266 | |
| 267 | post = fls(fin) - fls(fspi); |
| 268 | if (fin > fspi << post) |
| 269 | post++; |
| 270 | |
| 271 | /* now we have: (fin <= fspi << post) with post being minimal */ |
| 272 | |
| 273 | post = max(4U, post) - 4; |
| 274 | if (unlikely(post > 0xf)) { |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 275 | dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", |
| 276 | fspi, fin); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 277 | return 0xff; |
| 278 | } |
| 279 | |
| 280 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; |
| 281 | |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 282 | dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 283 | __func__, fin, fspi, post, pre); |
Marek Vasut | 6fd8b85 | 2013-12-18 18:31:47 +0100 | [diff] [blame] | 284 | |
| 285 | /* Resulting frequency for the SCLK line. */ |
| 286 | *fres = (fin / (pre + 1)) >> post; |
| 287 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 288 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
| 289 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 290 | } |
| 291 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 292 | static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 293 | { |
| 294 | unsigned val = 0; |
| 295 | |
| 296 | if (enable & MXC_INT_TE) |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 297 | val |= MX51_ECSPI_INT_TEEN; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 298 | |
| 299 | if (enable & MXC_INT_RR) |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 300 | val |= MX51_ECSPI_INT_RREN; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 301 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 302 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 303 | } |
| 304 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 305 | static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 306 | { |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 307 | u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 308 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 309 | if (!spi_imx->usedma) |
| 310 | reg |= MX51_ECSPI_CTRL_XCH; |
| 311 | else if (!spi_imx->dma_finished) |
| 312 | reg |= MX51_ECSPI_CTRL_SMC; |
| 313 | else |
| 314 | reg &= ~MX51_ECSPI_CTRL_SMC; |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 315 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 316 | } |
| 317 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 318 | static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 319 | struct spi_imx_config *config) |
| 320 | { |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 321 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0; |
| 322 | u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg; |
Fabio Estevam | 9f6aa42 | 2015-12-03 23:23:24 -0200 | [diff] [blame] | 323 | u32 clk = config->speed_hz, delay, reg; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 324 | |
Sascha Hauer | f020c39 | 2011-02-08 21:08:59 +0100 | [diff] [blame] | 325 | /* |
| 326 | * The hardware seems to have a race condition when changing modes. The |
| 327 | * current assumption is that the selection of the channel arrives |
| 328 | * earlier in the hardware than the mode bits when they are written at |
| 329 | * the same time. |
| 330 | * So set master mode for all channels as we do not support slave mode. |
| 331 | */ |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 332 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 333 | |
| 334 | /* set clock speed */ |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 335 | ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 336 | |
| 337 | /* set chip select to use */ |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 338 | ctrl |= MX51_ECSPI_CTRL_CS(config->cs); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 339 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 340 | ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 341 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 342 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 343 | |
| 344 | if (config->mode & SPI_CPHA) |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 345 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
Andrew Y. Kuksov | 1476253 | 2015-07-14 16:23:25 +0300 | [diff] [blame] | 346 | else |
| 347 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 348 | |
Knut Wohlrab | c09b890 | 2012-09-25 13:21:57 +0200 | [diff] [blame] | 349 | if (config->mode & SPI_CPOL) { |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 350 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
Knut Wohlrab | c09b890 | 2012-09-25 13:21:57 +0200 | [diff] [blame] | 351 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); |
Andrew Y. Kuksov | 1476253 | 2015-07-14 16:23:25 +0300 | [diff] [blame] | 352 | } else { |
| 353 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
| 354 | cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); |
Knut Wohlrab | c09b890 | 2012-09-25 13:21:57 +0200 | [diff] [blame] | 355 | } |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 356 | if (config->mode & SPI_CS_HIGH) |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 357 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
Andrew Y. Kuksov | 1476253 | 2015-07-14 16:23:25 +0300 | [diff] [blame] | 358 | else |
| 359 | cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 360 | |
Anton Bondarenko | f677f17 | 2015-12-08 07:43:43 +0100 | [diff] [blame] | 361 | /* CTRL register always go first to bring out controller from reset */ |
| 362 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); |
| 363 | |
Fabio Estevam | 9f6aa42 | 2015-12-03 23:23:24 -0200 | [diff] [blame] | 364 | reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); |
| 365 | if (config->mode & SPI_LOOP) |
| 366 | reg |= MX51_ECSPI_TESTREG_LBC; |
| 367 | else |
| 368 | reg &= ~MX51_ECSPI_TESTREG_LBC; |
| 369 | writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); |
| 370 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 371 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 372 | |
Marek Vasut | 6fd8b85 | 2013-12-18 18:31:47 +0100 | [diff] [blame] | 373 | /* |
| 374 | * Wait until the changes in the configuration register CONFIGREG |
| 375 | * propagate into the hardware. It takes exactly one tick of the |
| 376 | * SCLK clock, but we will wait two SCLK clock just to be sure. The |
| 377 | * effect of the delay it takes for the hardware to apply changes |
| 378 | * is noticable if the SCLK clock run very slow. In such a case, if |
| 379 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might |
| 380 | * be asserted before the SCLK polarity changes, which would disrupt |
| 381 | * the SPI communication as the device on the other end would consider |
| 382 | * the change of SCLK polarity as a clock tick already. |
| 383 | */ |
| 384 | delay = (2 * 1000000) / clk; |
| 385 | if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ |
| 386 | udelay(delay); |
| 387 | else /* SCLK is _very_ slow */ |
| 388 | usleep_range(delay, delay + 10); |
| 389 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 390 | /* |
| 391 | * Configure the DMA register: setup the watermark |
| 392 | * and enable DMA request. |
| 393 | */ |
| 394 | if (spi_imx->dma_is_inited) { |
| 395 | dma = readl(spi_imx->base + MX51_ECSPI_DMA); |
| 396 | |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 397 | rx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET; |
| 398 | tx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET; |
| 399 | rxt_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 400 | dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK |
| 401 | & ~MX51_ECSPI_DMA_RX_WML_MASK |
| 402 | & ~MX51_ECSPI_DMA_RXT_WML_MASK) |
| 403 | | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg |
| 404 | |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET) |
| 405 | |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET) |
| 406 | |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET); |
| 407 | |
| 408 | writel(dma, spi_imx->base + MX51_ECSPI_DMA); |
| 409 | } |
| 410 | |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 411 | return 0; |
| 412 | } |
| 413 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 414 | static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 415 | { |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 416 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 417 | } |
| 418 | |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 419 | static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 420 | { |
| 421 | /* drain receive buffer */ |
Shawn Guo | 66de757 | 2011-07-10 01:16:37 +0800 | [diff] [blame] | 422 | while (mx51_ecspi_rx_available(spi_imx)) |
Uwe Kleine-König | 0b59960 | 2010-09-09 21:02:48 +0200 | [diff] [blame] | 423 | readl(spi_imx->base + MXC_CSPIRXDATA); |
| 424 | } |
| 425 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 426 | #define MX31_INTREG_TEEN (1 << 0) |
| 427 | #define MX31_INTREG_RREN (1 << 3) |
| 428 | |
| 429 | #define MX31_CSPICTRL_ENABLE (1 << 0) |
| 430 | #define MX31_CSPICTRL_MASTER (1 << 1) |
| 431 | #define MX31_CSPICTRL_XCH (1 << 2) |
| 432 | #define MX31_CSPICTRL_POL (1 << 4) |
| 433 | #define MX31_CSPICTRL_PHA (1 << 5) |
| 434 | #define MX31_CSPICTRL_SSCTL (1 << 6) |
| 435 | #define MX31_CSPICTRL_SSPOL (1 << 7) |
| 436 | #define MX31_CSPICTRL_BC_SHIFT 8 |
| 437 | #define MX35_CSPICTRL_BL_SHIFT 20 |
| 438 | #define MX31_CSPICTRL_CS_SHIFT 24 |
| 439 | #define MX35_CSPICTRL_CS_SHIFT 12 |
| 440 | #define MX31_CSPICTRL_DR_SHIFT 16 |
| 441 | |
| 442 | #define MX31_CSPISTATUS 0x14 |
| 443 | #define MX31_STATUS_RR (1 << 3) |
| 444 | |
| 445 | /* These functions also work for the i.MX35, but be aware that |
| 446 | * the i.MX35 has a slightly different register layout for bits |
| 447 | * we do not use here. |
| 448 | */ |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 449 | static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 450 | { |
| 451 | unsigned int val = 0; |
| 452 | |
| 453 | if (enable & MXC_INT_TE) |
| 454 | val |= MX31_INTREG_TEEN; |
| 455 | if (enable & MXC_INT_RR) |
| 456 | val |= MX31_INTREG_RREN; |
| 457 | |
| 458 | writel(val, spi_imx->base + MXC_CSPIINT); |
| 459 | } |
| 460 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 461 | static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 462 | { |
| 463 | unsigned int reg; |
| 464 | |
| 465 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
| 466 | reg |= MX31_CSPICTRL_XCH; |
| 467 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 468 | } |
| 469 | |
Shawn Guo | 2a64a90 | 2011-07-10 01:16:38 +0800 | [diff] [blame] | 470 | static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 471 | struct spi_imx_config *config) |
| 472 | { |
| 473 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; |
Uwe Kleine-König | 3b2aa89 | 2010-09-10 09:42:29 +0200 | [diff] [blame] | 474 | int cs = spi_imx->chipselect[config->cs]; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 475 | |
| 476 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
| 477 | MX31_CSPICTRL_DR_SHIFT; |
| 478 | |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 479 | if (is_imx35_cspi(spi_imx)) { |
Shawn Guo | 2a64a90 | 2011-07-10 01:16:38 +0800 | [diff] [blame] | 480 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
| 481 | reg |= MX31_CSPICTRL_SSCTL; |
| 482 | } else { |
| 483 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; |
| 484 | } |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 485 | |
| 486 | if (config->mode & SPI_CPHA) |
| 487 | reg |= MX31_CSPICTRL_PHA; |
| 488 | if (config->mode & SPI_CPOL) |
| 489 | reg |= MX31_CSPICTRL_POL; |
| 490 | if (config->mode & SPI_CS_HIGH) |
| 491 | reg |= MX31_CSPICTRL_SSPOL; |
Uwe Kleine-König | 3b2aa89 | 2010-09-10 09:42:29 +0200 | [diff] [blame] | 492 | if (cs < 0) |
Shawn Guo | 2a64a90 | 2011-07-10 01:16:38 +0800 | [diff] [blame] | 493 | reg |= (cs + 32) << |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 494 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
| 495 | MX31_CSPICTRL_CS_SHIFT); |
Uwe Kleine-König | 1723e66 | 2010-09-10 09:19:18 +0200 | [diff] [blame] | 496 | |
| 497 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 498 | |
| 499 | return 0; |
| 500 | } |
| 501 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 502 | static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 503 | { |
| 504 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
| 505 | } |
| 506 | |
Shawn Guo | 2a64a90 | 2011-07-10 01:16:38 +0800 | [diff] [blame] | 507 | static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 1723e66 | 2010-09-10 09:19:18 +0200 | [diff] [blame] | 508 | { |
| 509 | /* drain receive buffer */ |
Shawn Guo | 2a64a90 | 2011-07-10 01:16:38 +0800 | [diff] [blame] | 510 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
Uwe Kleine-König | 1723e66 | 2010-09-10 09:19:18 +0200 | [diff] [blame] | 511 | readl(spi_imx->base + MXC_CSPIRXDATA); |
| 512 | } |
| 513 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 514 | #define MX21_INTREG_RR (1 << 4) |
| 515 | #define MX21_INTREG_TEEN (1 << 9) |
| 516 | #define MX21_INTREG_RREN (1 << 13) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 517 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 518 | #define MX21_CSPICTRL_POL (1 << 5) |
| 519 | #define MX21_CSPICTRL_PHA (1 << 6) |
| 520 | #define MX21_CSPICTRL_SSPOL (1 << 8) |
| 521 | #define MX21_CSPICTRL_XCH (1 << 9) |
| 522 | #define MX21_CSPICTRL_ENABLE (1 << 10) |
| 523 | #define MX21_CSPICTRL_MASTER (1 << 11) |
| 524 | #define MX21_CSPICTRL_DR_SHIFT 14 |
| 525 | #define MX21_CSPICTRL_CS_SHIFT 19 |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 526 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 527 | static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 528 | { |
| 529 | unsigned int val = 0; |
| 530 | |
| 531 | if (enable & MXC_INT_TE) |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 532 | val |= MX21_INTREG_TEEN; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 533 | if (enable & MXC_INT_RR) |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 534 | val |= MX21_INTREG_RREN; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 535 | |
| 536 | writel(val, spi_imx->base + MXC_CSPIINT); |
| 537 | } |
| 538 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 539 | static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 540 | { |
| 541 | unsigned int reg; |
| 542 | |
| 543 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 544 | reg |= MX21_CSPICTRL_XCH; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 545 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 546 | } |
| 547 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 548 | static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 549 | struct spi_imx_config *config) |
| 550 | { |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 551 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
Uwe Kleine-König | 3b2aa89 | 2010-09-10 09:42:29 +0200 | [diff] [blame] | 552 | int cs = spi_imx->chipselect[config->cs]; |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 553 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 554 | |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 555 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 556 | MX21_CSPICTRL_DR_SHIFT; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 557 | reg |= config->bpw - 1; |
| 558 | |
| 559 | if (config->mode & SPI_CPHA) |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 560 | reg |= MX21_CSPICTRL_PHA; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 561 | if (config->mode & SPI_CPOL) |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 562 | reg |= MX21_CSPICTRL_POL; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 563 | if (config->mode & SPI_CS_HIGH) |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 564 | reg |= MX21_CSPICTRL_SSPOL; |
Uwe Kleine-König | 3b2aa89 | 2010-09-10 09:42:29 +0200 | [diff] [blame] | 565 | if (cs < 0) |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 566 | reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 567 | |
| 568 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 573 | static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 574 | { |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 575 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 576 | } |
| 577 | |
Shawn Guo | 3451fb1 | 2011-07-10 01:16:36 +0800 | [diff] [blame] | 578 | static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 1723e66 | 2010-09-10 09:19:18 +0200 | [diff] [blame] | 579 | { |
| 580 | writel(1, spi_imx->base + MXC_RESET); |
| 581 | } |
| 582 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 583 | #define MX1_INTREG_RR (1 << 3) |
| 584 | #define MX1_INTREG_TEEN (1 << 8) |
| 585 | #define MX1_INTREG_RREN (1 << 11) |
| 586 | |
| 587 | #define MX1_CSPICTRL_POL (1 << 4) |
| 588 | #define MX1_CSPICTRL_PHA (1 << 5) |
| 589 | #define MX1_CSPICTRL_XCH (1 << 8) |
| 590 | #define MX1_CSPICTRL_ENABLE (1 << 9) |
| 591 | #define MX1_CSPICTRL_MASTER (1 << 10) |
| 592 | #define MX1_CSPICTRL_DR_SHIFT 13 |
| 593 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 594 | static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 595 | { |
| 596 | unsigned int val = 0; |
| 597 | |
| 598 | if (enable & MXC_INT_TE) |
| 599 | val |= MX1_INTREG_TEEN; |
| 600 | if (enable & MXC_INT_RR) |
| 601 | val |= MX1_INTREG_RREN; |
| 602 | |
| 603 | writel(val, spi_imx->base + MXC_CSPIINT); |
| 604 | } |
| 605 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 606 | static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 607 | { |
| 608 | unsigned int reg; |
| 609 | |
| 610 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
| 611 | reg |= MX1_CSPICTRL_XCH; |
| 612 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 613 | } |
| 614 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 615 | static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 616 | struct spi_imx_config *config) |
| 617 | { |
| 618 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; |
| 619 | |
| 620 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
| 621 | MX1_CSPICTRL_DR_SHIFT; |
| 622 | reg |= config->bpw - 1; |
| 623 | |
| 624 | if (config->mode & SPI_CPHA) |
| 625 | reg |= MX1_CSPICTRL_PHA; |
| 626 | if (config->mode & SPI_CPOL) |
| 627 | reg |= MX1_CSPICTRL_POL; |
| 628 | |
| 629 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 634 | static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 635 | { |
| 636 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
| 637 | } |
| 638 | |
Uwe Kleine-König | 1723e66 | 2010-09-10 09:19:18 +0200 | [diff] [blame] | 639 | static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) |
| 640 | { |
| 641 | writel(1, spi_imx->base + MXC_RESET); |
| 642 | } |
| 643 | |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 644 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
| 645 | .intctrl = mx1_intctrl, |
| 646 | .config = mx1_config, |
| 647 | .trigger = mx1_trigger, |
| 648 | .rx_available = mx1_rx_available, |
| 649 | .reset = mx1_reset, |
| 650 | .devtype = IMX1_CSPI, |
| 651 | }; |
| 652 | |
| 653 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { |
| 654 | .intctrl = mx21_intctrl, |
| 655 | .config = mx21_config, |
| 656 | .trigger = mx21_trigger, |
| 657 | .rx_available = mx21_rx_available, |
| 658 | .reset = mx21_reset, |
| 659 | .devtype = IMX21_CSPI, |
| 660 | }; |
| 661 | |
| 662 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { |
| 663 | /* i.mx27 cspi shares the functions with i.mx21 one */ |
| 664 | .intctrl = mx21_intctrl, |
| 665 | .config = mx21_config, |
| 666 | .trigger = mx21_trigger, |
| 667 | .rx_available = mx21_rx_available, |
| 668 | .reset = mx21_reset, |
| 669 | .devtype = IMX27_CSPI, |
| 670 | }; |
| 671 | |
| 672 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { |
| 673 | .intctrl = mx31_intctrl, |
| 674 | .config = mx31_config, |
| 675 | .trigger = mx31_trigger, |
| 676 | .rx_available = mx31_rx_available, |
| 677 | .reset = mx31_reset, |
| 678 | .devtype = IMX31_CSPI, |
| 679 | }; |
| 680 | |
| 681 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { |
| 682 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ |
| 683 | .intctrl = mx31_intctrl, |
| 684 | .config = mx31_config, |
| 685 | .trigger = mx31_trigger, |
| 686 | .rx_available = mx31_rx_available, |
| 687 | .reset = mx31_reset, |
| 688 | .devtype = IMX35_CSPI, |
| 689 | }; |
| 690 | |
| 691 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { |
| 692 | .intctrl = mx51_ecspi_intctrl, |
| 693 | .config = mx51_ecspi_config, |
| 694 | .trigger = mx51_ecspi_trigger, |
| 695 | .rx_available = mx51_ecspi_rx_available, |
| 696 | .reset = mx51_ecspi_reset, |
| 697 | .devtype = IMX51_ECSPI, |
| 698 | }; |
| 699 | |
Krzysztof Kozlowski | db1b820 | 2015-05-02 00:44:04 +0900 | [diff] [blame] | 700 | static const struct platform_device_id spi_imx_devtype[] = { |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 701 | { |
| 702 | .name = "imx1-cspi", |
| 703 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, |
| 704 | }, { |
| 705 | .name = "imx21-cspi", |
| 706 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, |
| 707 | }, { |
| 708 | .name = "imx27-cspi", |
| 709 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, |
| 710 | }, { |
| 711 | .name = "imx31-cspi", |
| 712 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, |
| 713 | }, { |
| 714 | .name = "imx35-cspi", |
| 715 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, |
| 716 | }, { |
| 717 | .name = "imx51-ecspi", |
| 718 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, |
| 719 | }, { |
| 720 | /* sentinel */ |
| 721 | } |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 722 | }; |
| 723 | |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 724 | static const struct of_device_id spi_imx_dt_ids[] = { |
| 725 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, |
| 726 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, |
| 727 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, |
| 728 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, |
| 729 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, |
| 730 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, |
| 731 | { /* sentinel */ } |
| 732 | }; |
Niels de Vos | 27743e0 | 2013-07-29 09:38:05 +0200 | [diff] [blame] | 733 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 734 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 735 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
| 736 | { |
| 737 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 738 | int gpio = spi_imx->chipselect[spi->chip_select]; |
Uwe Kleine-König | e6a0a8b | 2009-10-01 15:44:33 -0700 | [diff] [blame] | 739 | int active = is_active != BITBANG_CS_INACTIVE; |
| 740 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 741 | |
Hui Wang | 8b17e05 | 2012-07-13 10:51:29 +0800 | [diff] [blame] | 742 | if (!gpio_is_valid(gpio)) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 743 | return; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 744 | |
Uwe Kleine-König | e6a0a8b | 2009-10-01 15:44:33 -0700 | [diff] [blame] | 745 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 746 | } |
| 747 | |
| 748 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
| 749 | { |
Shawn Guo | 04ee585 | 2011-07-10 01:16:39 +0800 | [diff] [blame] | 750 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 751 | if (!spi_imx->count) |
| 752 | break; |
| 753 | spi_imx->tx(spi_imx); |
| 754 | spi_imx->txfifo++; |
| 755 | } |
| 756 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 757 | spi_imx->devtype_data->trigger(spi_imx); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 758 | } |
| 759 | |
| 760 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
| 761 | { |
| 762 | struct spi_imx_data *spi_imx = dev_id; |
| 763 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 764 | while (spi_imx->devtype_data->rx_available(spi_imx)) { |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 765 | spi_imx->rx(spi_imx); |
| 766 | spi_imx->txfifo--; |
| 767 | } |
| 768 | |
| 769 | if (spi_imx->count) { |
| 770 | spi_imx_push(spi_imx); |
| 771 | return IRQ_HANDLED; |
| 772 | } |
| 773 | |
| 774 | if (spi_imx->txfifo) { |
| 775 | /* No data left to push, but still waiting for rx data, |
| 776 | * enable receive data available interrupt. |
| 777 | */ |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 778 | spi_imx->devtype_data->intctrl( |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 779 | spi_imx, MXC_INT_RR); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 780 | return IRQ_HANDLED; |
| 781 | } |
| 782 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 783 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 784 | complete(&spi_imx->xfer_done); |
| 785 | |
| 786 | return IRQ_HANDLED; |
| 787 | } |
| 788 | |
| 789 | static int spi_imx_setupxfer(struct spi_device *spi, |
| 790 | struct spi_transfer *t) |
| 791 | { |
| 792 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
| 793 | struct spi_imx_config config; |
| 794 | |
| 795 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; |
| 796 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; |
| 797 | config.mode = spi->mode; |
Uwe Kleine-König | 3b2aa89 | 2010-09-10 09:42:29 +0200 | [diff] [blame] | 798 | config.cs = spi->chip_select; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 799 | |
Sascha Hauer | 462d26b | 2009-10-01 15:44:29 -0700 | [diff] [blame] | 800 | if (!config.speed_hz) |
| 801 | config.speed_hz = spi->max_speed_hz; |
| 802 | if (!config.bpw) |
| 803 | config.bpw = spi->bits_per_word; |
Sascha Hauer | 462d26b | 2009-10-01 15:44:29 -0700 | [diff] [blame] | 804 | |
Uwe Kleine-König | e6a0a8b | 2009-10-01 15:44:33 -0700 | [diff] [blame] | 805 | /* Initialize the functions for transfer */ |
| 806 | if (config.bpw <= 8) { |
| 807 | spi_imx->rx = spi_imx_buf_rx_u8; |
| 808 | spi_imx->tx = spi_imx_buf_tx_u8; |
| 809 | } else if (config.bpw <= 16) { |
| 810 | spi_imx->rx = spi_imx_buf_rx_u16; |
| 811 | spi_imx->tx = spi_imx_buf_tx_u16; |
Sachin Kamat | 6051426 | 2013-05-30 13:38:09 +0530 | [diff] [blame] | 812 | } else { |
Uwe Kleine-König | e6a0a8b | 2009-10-01 15:44:33 -0700 | [diff] [blame] | 813 | spi_imx->rx = spi_imx_buf_rx_u32; |
| 814 | spi_imx->tx = spi_imx_buf_tx_u32; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 815 | } |
Uwe Kleine-König | e6a0a8b | 2009-10-01 15:44:33 -0700 | [diff] [blame] | 816 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 817 | spi_imx->devtype_data->config(spi_imx, &config); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 818 | |
| 819 | return 0; |
| 820 | } |
| 821 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 822 | static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) |
| 823 | { |
| 824 | struct spi_master *master = spi_imx->bitbang.master; |
| 825 | |
| 826 | if (master->dma_rx) { |
| 827 | dma_release_channel(master->dma_rx); |
| 828 | master->dma_rx = NULL; |
| 829 | } |
| 830 | |
| 831 | if (master->dma_tx) { |
| 832 | dma_release_channel(master->dma_tx); |
| 833 | master->dma_tx = NULL; |
| 834 | } |
| 835 | |
| 836 | spi_imx->dma_is_inited = 0; |
| 837 | } |
| 838 | |
| 839 | static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, |
| 840 | struct spi_master *master, |
| 841 | const struct resource *res) |
| 842 | { |
| 843 | struct dma_slave_config slave_config = {}; |
| 844 | int ret; |
| 845 | |
Robin Gong | a02bb40 | 2015-02-03 10:25:53 +0800 | [diff] [blame] | 846 | /* use pio mode for i.mx6dl chip TKT238285 */ |
| 847 | if (of_machine_is_compatible("fsl,imx6dl")) |
| 848 | return 0; |
| 849 | |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 850 | spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; |
| 851 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 852 | /* Prepare for TX DMA: */ |
Anton Bondarenko | 3760047 | 2015-12-08 07:43:45 +0100 | [diff] [blame] | 853 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); |
| 854 | if (IS_ERR(master->dma_tx)) { |
| 855 | ret = PTR_ERR(master->dma_tx); |
| 856 | dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); |
| 857 | master->dma_tx = NULL; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 858 | goto err; |
| 859 | } |
| 860 | |
| 861 | slave_config.direction = DMA_MEM_TO_DEV; |
| 862 | slave_config.dst_addr = res->start + MXC_CSPITXDATA; |
| 863 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 864 | slave_config.dst_maxburst = spi_imx->wml; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 865 | ret = dmaengine_slave_config(master->dma_tx, &slave_config); |
| 866 | if (ret) { |
| 867 | dev_err(dev, "error in TX dma configuration.\n"); |
| 868 | goto err; |
| 869 | } |
| 870 | |
| 871 | /* Prepare for RX : */ |
Anton Bondarenko | 3760047 | 2015-12-08 07:43:45 +0100 | [diff] [blame] | 872 | master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); |
| 873 | if (IS_ERR(master->dma_rx)) { |
| 874 | ret = PTR_ERR(master->dma_rx); |
| 875 | dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); |
| 876 | master->dma_rx = NULL; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 877 | goto err; |
| 878 | } |
| 879 | |
| 880 | slave_config.direction = DMA_DEV_TO_MEM; |
| 881 | slave_config.src_addr = res->start + MXC_CSPIRXDATA; |
| 882 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 883 | slave_config.src_maxburst = spi_imx->wml; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 884 | ret = dmaengine_slave_config(master->dma_rx, &slave_config); |
| 885 | if (ret) { |
| 886 | dev_err(dev, "error in RX dma configuration.\n"); |
| 887 | goto err; |
| 888 | } |
| 889 | |
| 890 | init_completion(&spi_imx->dma_rx_completion); |
| 891 | init_completion(&spi_imx->dma_tx_completion); |
| 892 | master->can_dma = spi_imx_can_dma; |
| 893 | master->max_dma_len = MAX_SDMA_BD_BYTES; |
| 894 | spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | |
| 895 | SPI_MASTER_MUST_TX; |
| 896 | spi_imx->dma_is_inited = 1; |
| 897 | |
| 898 | return 0; |
| 899 | err: |
| 900 | spi_imx_sdma_exit(spi_imx); |
| 901 | return ret; |
| 902 | } |
| 903 | |
| 904 | static void spi_imx_dma_rx_callback(void *cookie) |
| 905 | { |
| 906 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; |
| 907 | |
| 908 | complete(&spi_imx->dma_rx_completion); |
| 909 | } |
| 910 | |
| 911 | static void spi_imx_dma_tx_callback(void *cookie) |
| 912 | { |
| 913 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; |
| 914 | |
| 915 | complete(&spi_imx->dma_tx_completion); |
| 916 | } |
| 917 | |
| 918 | static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
| 919 | struct spi_transfer *transfer) |
| 920 | { |
| 921 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; |
| 922 | int ret; |
Nicholas Mc Guire | 56536a7 | 2015-02-02 03:30:35 -0500 | [diff] [blame] | 923 | unsigned long timeout; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 924 | u32 dma; |
| 925 | int left; |
| 926 | struct spi_master *master = spi_imx->bitbang.master; |
| 927 | struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; |
| 928 | |
| 929 | if (tx) { |
| 930 | desc_tx = dmaengine_prep_slave_sg(master->dma_tx, |
Stefan Agner | e8361f7 | 2015-03-03 00:28:31 +0100 | [diff] [blame] | 931 | tx->sgl, tx->nents, DMA_MEM_TO_DEV, |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 932 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 933 | if (!desc_tx) |
| 934 | goto no_dma; |
| 935 | |
| 936 | desc_tx->callback = spi_imx_dma_tx_callback; |
| 937 | desc_tx->callback_param = (void *)spi_imx; |
| 938 | dmaengine_submit(desc_tx); |
| 939 | } |
| 940 | |
| 941 | if (rx) { |
| 942 | desc_rx = dmaengine_prep_slave_sg(master->dma_rx, |
Stefan Agner | e8361f7 | 2015-03-03 00:28:31 +0100 | [diff] [blame] | 943 | rx->sgl, rx->nents, DMA_DEV_TO_MEM, |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 944 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 945 | if (!desc_rx) |
| 946 | goto no_dma; |
| 947 | |
| 948 | desc_rx->callback = spi_imx_dma_rx_callback; |
| 949 | desc_rx->callback_param = (void *)spi_imx; |
| 950 | dmaengine_submit(desc_rx); |
| 951 | } |
| 952 | |
| 953 | reinit_completion(&spi_imx->dma_rx_completion); |
| 954 | reinit_completion(&spi_imx->dma_tx_completion); |
| 955 | |
| 956 | /* Trigger the cspi module. */ |
| 957 | spi_imx->dma_finished = 0; |
| 958 | |
| 959 | dma = readl(spi_imx->base + MX51_ECSPI_DMA); |
| 960 | dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK); |
| 961 | /* Change RX_DMA_LENGTH trigger dma fetch tail data */ |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 962 | left = transfer->len % spi_imx->wml; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 963 | if (left) |
| 964 | writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET), |
| 965 | spi_imx->base + MX51_ECSPI_DMA); |
Anton Bondarenko | fab44ef | 2015-12-05 17:57:00 +0100 | [diff] [blame] | 966 | /* |
| 967 | * Set these order to avoid potential RX overflow. The overflow may |
| 968 | * happen if we enable SPI HW before starting RX DMA due to rescheduling |
| 969 | * for another task and/or interrupt. |
| 970 | * So RX DMA enabled first to make sure data would be read out from FIFO |
| 971 | * ASAP. TX DMA enabled next to start filling TX FIFO with new data. |
| 972 | * And finaly SPI HW enabled to start actual data transfer. |
| 973 | */ |
| 974 | dma_async_issue_pending(master->dma_rx); |
| 975 | dma_async_issue_pending(master->dma_tx); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 976 | spi_imx->devtype_data->trigger(spi_imx); |
| 977 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 978 | /* Wait SDMA to finish the data transfer.*/ |
Nicholas Mc Guire | 56536a7 | 2015-02-02 03:30:35 -0500 | [diff] [blame] | 979 | timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 980 | IMX_DMA_TIMEOUT); |
Nicholas Mc Guire | 56536a7 | 2015-02-02 03:30:35 -0500 | [diff] [blame] | 981 | if (!timeout) { |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 982 | dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 983 | dmaengine_terminate_all(master->dma_tx); |
Anton Bondarenko | e47b33c | 2015-12-05 17:56:59 +0100 | [diff] [blame] | 984 | dmaengine_terminate_all(master->dma_rx); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 985 | } else { |
Nicholas Mc Guire | 56536a7 | 2015-02-02 03:30:35 -0500 | [diff] [blame] | 986 | timeout = wait_for_completion_timeout( |
| 987 | &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT); |
| 988 | if (!timeout) { |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 989 | dev_err(spi_imx->dev, "I/O Error in DMA RX\n"); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 990 | spi_imx->devtype_data->reset(spi_imx); |
| 991 | dmaengine_terminate_all(master->dma_rx); |
| 992 | } |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 993 | dma &= ~MX51_ECSPI_DMA_RXT_WML_MASK; |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 994 | writel(dma | |
Anton Bondarenko | 0dfbaa8 | 2015-12-05 17:57:01 +0100 | [diff] [blame] | 995 | spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET, |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 996 | spi_imx->base + MX51_ECSPI_DMA); |
| 997 | } |
| 998 | |
| 999 | spi_imx->dma_finished = 1; |
| 1000 | spi_imx->devtype_data->trigger(spi_imx); |
| 1001 | |
Nicholas Mc Guire | 56536a7 | 2015-02-02 03:30:35 -0500 | [diff] [blame] | 1002 | if (!timeout) |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 1003 | ret = -ETIMEDOUT; |
Nicholas Mc Guire | 56536a7 | 2015-02-02 03:30:35 -0500 | [diff] [blame] | 1004 | else |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 1005 | ret = transfer->len; |
| 1006 | |
| 1007 | return ret; |
| 1008 | |
| 1009 | no_dma: |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 1010 | dev_warn_once(spi_imx->dev, "DMA not available, falling back to PIO\n"); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 1011 | return -EAGAIN; |
| 1012 | } |
| 1013 | |
| 1014 | static int spi_imx_pio_transfer(struct spi_device *spi, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1015 | struct spi_transfer *transfer) |
| 1016 | { |
| 1017 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
| 1018 | |
| 1019 | spi_imx->tx_buf = transfer->tx_buf; |
| 1020 | spi_imx->rx_buf = transfer->rx_buf; |
| 1021 | spi_imx->count = transfer->len; |
| 1022 | spi_imx->txfifo = 0; |
| 1023 | |
Axel Lin | aa0fe82 | 2014-02-09 11:06:04 +0800 | [diff] [blame] | 1024 | reinit_completion(&spi_imx->xfer_done); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1025 | |
| 1026 | spi_imx_push(spi_imx); |
| 1027 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 1028 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1029 | |
| 1030 | wait_for_completion(&spi_imx->xfer_done); |
| 1031 | |
| 1032 | return transfer->len; |
| 1033 | } |
| 1034 | |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 1035 | static int spi_imx_transfer(struct spi_device *spi, |
| 1036 | struct spi_transfer *transfer) |
| 1037 | { |
| 1038 | int ret; |
| 1039 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
| 1040 | |
| 1041 | if (spi_imx->bitbang.master->can_dma && |
| 1042 | spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) { |
| 1043 | spi_imx->usedma = true; |
| 1044 | ret = spi_imx_dma_transfer(spi_imx, transfer); |
| 1045 | if (ret != -EAGAIN) |
| 1046 | return ret; |
| 1047 | } |
| 1048 | spi_imx->usedma = false; |
| 1049 | |
| 1050 | return spi_imx_pio_transfer(spi, transfer); |
| 1051 | } |
| 1052 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1053 | static int spi_imx_setup(struct spi_device *spi) |
| 1054 | { |
Sascha Hauer | 6c23e5d | 2009-10-01 15:44:29 -0700 | [diff] [blame] | 1055 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
| 1056 | int gpio = spi_imx->chipselect[spi->chip_select]; |
| 1057 | |
Alberto Panizzo | f4d4ecf | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 1058 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1059 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
| 1060 | |
Hui Wang | 8b17e05 | 2012-07-13 10:51:29 +0800 | [diff] [blame] | 1061 | if (gpio_is_valid(gpio)) |
Sascha Hauer | 6c23e5d | 2009-10-01 15:44:29 -0700 | [diff] [blame] | 1062 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); |
| 1063 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1064 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
| 1065 | |
| 1066 | return 0; |
| 1067 | } |
| 1068 | |
| 1069 | static void spi_imx_cleanup(struct spi_device *spi) |
| 1070 | { |
| 1071 | } |
| 1072 | |
Huang Shijie | 9e556dc | 2013-10-23 16:31:50 +0800 | [diff] [blame] | 1073 | static int |
| 1074 | spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) |
| 1075 | { |
| 1076 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
| 1077 | int ret; |
| 1078 | |
| 1079 | ret = clk_enable(spi_imx->clk_per); |
| 1080 | if (ret) |
| 1081 | return ret; |
| 1082 | |
| 1083 | ret = clk_enable(spi_imx->clk_ipg); |
| 1084 | if (ret) { |
| 1085 | clk_disable(spi_imx->clk_per); |
| 1086 | return ret; |
| 1087 | } |
| 1088 | |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | static int |
| 1093 | spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) |
| 1094 | { |
| 1095 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
| 1096 | |
| 1097 | clk_disable(spi_imx->clk_ipg); |
| 1098 | clk_disable(spi_imx->clk_per); |
| 1099 | return 0; |
| 1100 | } |
| 1101 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1102 | static int spi_imx_probe(struct platform_device *pdev) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1103 | { |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1104 | struct device_node *np = pdev->dev.of_node; |
| 1105 | const struct of_device_id *of_id = |
| 1106 | of_match_device(spi_imx_dt_ids, &pdev->dev); |
| 1107 | struct spi_imx_master *mxc_platform_info = |
| 1108 | dev_get_platdata(&pdev->dev); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1109 | struct spi_master *master; |
| 1110 | struct spi_imx_data *spi_imx; |
| 1111 | struct resource *res; |
Fabio Estevam | 4b5d6aa | 2014-12-29 19:38:51 -0200 | [diff] [blame] | 1112 | int i, ret, num_cs, irq; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1113 | |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1114 | if (!np && !mxc_platform_info) { |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1115 | dev_err(&pdev->dev, "can't get the platform data\n"); |
| 1116 | return -EINVAL; |
| 1117 | } |
| 1118 | |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1119 | ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); |
Lothar Waßmann | 39ec0d3 | 2012-04-03 15:03:44 +0200 | [diff] [blame] | 1120 | if (ret < 0) { |
| 1121 | if (mxc_platform_info) |
| 1122 | num_cs = mxc_platform_info->num_chipselect; |
| 1123 | else |
| 1124 | return ret; |
| 1125 | } |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1126 | |
Shawn Guo | c2387cb | 2011-07-10 01:16:40 +0800 | [diff] [blame] | 1127 | master = spi_alloc_master(&pdev->dev, |
| 1128 | sizeof(struct spi_imx_data) + sizeof(int) * num_cs); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1129 | if (!master) |
| 1130 | return -ENOMEM; |
| 1131 | |
| 1132 | platform_set_drvdata(pdev, master); |
| 1133 | |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 1134 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1135 | master->bus_num = pdev->id; |
Shawn Guo | c2387cb | 2011-07-10 01:16:40 +0800 | [diff] [blame] | 1136 | master->num_chipselect = num_cs; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1137 | |
| 1138 | spi_imx = spi_master_get_devdata(master); |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 1139 | spi_imx->bitbang.master = master; |
Sascha Hauer | 6aa800c | 2016-02-17 14:28:48 +0100 | [diff] [blame^] | 1140 | spi_imx->dev = &pdev->dev; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1141 | |
Anton Bondarenko | 4686d1c | 2015-12-08 07:43:44 +0100 | [diff] [blame] | 1142 | spi_imx->devtype_data = of_id ? of_id->data : |
| 1143 | (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; |
| 1144 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1145 | for (i = 0; i < master->num_chipselect; i++) { |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1146 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
Hui Wang | 8b17e05 | 2012-07-13 10:51:29 +0800 | [diff] [blame] | 1147 | if (!gpio_is_valid(cs_gpio) && mxc_platform_info) |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1148 | cs_gpio = mxc_platform_info->chipselect[i]; |
Fabio Estevam | 4cc122a | 2011-09-15 17:21:15 -0300 | [diff] [blame] | 1149 | |
| 1150 | spi_imx->chipselect[i] = cs_gpio; |
Hui Wang | 8b17e05 | 2012-07-13 10:51:29 +0800 | [diff] [blame] | 1151 | if (!gpio_is_valid(cs_gpio)) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1152 | continue; |
Fabio Estevam | 4cc122a | 2011-09-15 17:21:15 -0300 | [diff] [blame] | 1153 | |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1154 | ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], |
| 1155 | DRIVER_NAME); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1156 | if (ret) { |
John Ogness | bbd050a | 2009-11-24 16:53:07 +0000 | [diff] [blame] | 1157 | dev_err(&pdev->dev, "can't get cs gpios\n"); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1158 | goto out_master_put; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1159 | } |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1160 | } |
| 1161 | |
| 1162 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
| 1163 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; |
| 1164 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; |
| 1165 | spi_imx->bitbang.master->setup = spi_imx_setup; |
| 1166 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; |
Huang Shijie | 9e556dc | 2013-10-23 16:31:50 +0800 | [diff] [blame] | 1167 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
| 1168 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; |
Anton Bondarenko | 4686d1c | 2015-12-08 07:43:44 +0100 | [diff] [blame] | 1169 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1170 | if (is_imx51_ecspi(spi_imx)) |
| 1171 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1172 | |
| 1173 | init_completion(&spi_imx->xfer_done); |
| 1174 | |
| 1175 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1176 | spi_imx->base = devm_ioremap_resource(&pdev->dev, res); |
| 1177 | if (IS_ERR(spi_imx->base)) { |
| 1178 | ret = PTR_ERR(spi_imx->base); |
| 1179 | goto out_master_put; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1180 | } |
| 1181 | |
Fabio Estevam | 4b5d6aa | 2014-12-29 19:38:51 -0200 | [diff] [blame] | 1182 | irq = platform_get_irq(pdev, 0); |
| 1183 | if (irq < 0) { |
| 1184 | ret = irq; |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1185 | goto out_master_put; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1186 | } |
| 1187 | |
Fabio Estevam | 4b5d6aa | 2014-12-29 19:38:51 -0200 | [diff] [blame] | 1188 | ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, |
Alexander Shiyan | 8fc39b5 | 2014-02-22 17:23:46 +0400 | [diff] [blame] | 1189 | dev_name(&pdev->dev), spi_imx); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1190 | if (ret) { |
Fabio Estevam | 4b5d6aa | 2014-12-29 19:38:51 -0200 | [diff] [blame] | 1191 | dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1192 | goto out_master_put; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1193 | } |
| 1194 | |
Sascha Hauer | aa29d840 | 2012-03-07 09:30:22 +0100 | [diff] [blame] | 1195 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
| 1196 | if (IS_ERR(spi_imx->clk_ipg)) { |
| 1197 | ret = PTR_ERR(spi_imx->clk_ipg); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1198 | goto out_master_put; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1199 | } |
| 1200 | |
Sascha Hauer | aa29d840 | 2012-03-07 09:30:22 +0100 | [diff] [blame] | 1201 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
| 1202 | if (IS_ERR(spi_imx->clk_per)) { |
| 1203 | ret = PTR_ERR(spi_imx->clk_per); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1204 | goto out_master_put; |
Sascha Hauer | aa29d840 | 2012-03-07 09:30:22 +0100 | [diff] [blame] | 1205 | } |
| 1206 | |
Fabio Estevam | 8317462 | 2013-07-11 01:26:49 -0300 | [diff] [blame] | 1207 | ret = clk_prepare_enable(spi_imx->clk_per); |
| 1208 | if (ret) |
| 1209 | goto out_master_put; |
| 1210 | |
| 1211 | ret = clk_prepare_enable(spi_imx->clk_ipg); |
| 1212 | if (ret) |
| 1213 | goto out_put_per; |
Sascha Hauer | aa29d840 | 2012-03-07 09:30:22 +0100 | [diff] [blame] | 1214 | |
| 1215 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 1216 | /* |
| 1217 | * Only validated on i.mx6 now, can remove the constrain if validated on |
| 1218 | * other chips. |
| 1219 | */ |
Anton Bondarenko | 3760047 | 2015-12-08 07:43:45 +0100 | [diff] [blame] | 1220 | if (is_imx51_ecspi(spi_imx)) { |
| 1221 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master, res); |
Anton Bondarenko | bf9af08 | 2015-12-08 07:43:46 +0100 | [diff] [blame] | 1222 | if (ret == -EPROBE_DEFER) |
| 1223 | goto out_clk_put; |
| 1224 | |
Anton Bondarenko | 3760047 | 2015-12-08 07:43:45 +0100 | [diff] [blame] | 1225 | if (ret < 0) |
| 1226 | dev_err(&pdev->dev, "dma setup error %d, use pio\n", |
| 1227 | ret); |
| 1228 | } |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1229 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 1230 | spi_imx->devtype_data->reset(spi_imx); |
Daniel Mack | ce1807b | 2009-11-19 19:01:42 +0000 | [diff] [blame] | 1231 | |
Shawn Guo | edd501bb | 2011-07-10 01:16:35 +0800 | [diff] [blame] | 1232 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1233 | |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1234 | master->dev.of_node = pdev->dev.of_node; |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1235 | ret = spi_bitbang_start(&spi_imx->bitbang); |
| 1236 | if (ret) { |
| 1237 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); |
| 1238 | goto out_clk_put; |
| 1239 | } |
| 1240 | |
| 1241 | dev_info(&pdev->dev, "probed\n"); |
| 1242 | |
Huang Shijie | 9e556dc | 2013-10-23 16:31:50 +0800 | [diff] [blame] | 1243 | clk_disable(spi_imx->clk_ipg); |
| 1244 | clk_disable(spi_imx->clk_per); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1245 | return ret; |
| 1246 | |
| 1247 | out_clk_put: |
Sascha Hauer | aa29d840 | 2012-03-07 09:30:22 +0100 | [diff] [blame] | 1248 | clk_disable_unprepare(spi_imx->clk_ipg); |
Fabio Estevam | 8317462 | 2013-07-11 01:26:49 -0300 | [diff] [blame] | 1249 | out_put_per: |
| 1250 | clk_disable_unprepare(spi_imx->clk_per); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1251 | out_master_put: |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1252 | spi_master_put(master); |
Fabio Estevam | 130b82c | 2013-07-11 01:26:48 -0300 | [diff] [blame] | 1253 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1254 | return ret; |
| 1255 | } |
| 1256 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1257 | static int spi_imx_remove(struct platform_device *pdev) |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1258 | { |
| 1259 | struct spi_master *master = platform_get_drvdata(pdev); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1260 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1261 | |
| 1262 | spi_bitbang_stop(&spi_imx->bitbang); |
| 1263 | |
| 1264 | writel(0, spi_imx->base + MXC_CSPICTRL); |
Philippe De Muyter | fd40dcc | 2014-02-27 10:16:15 +0100 | [diff] [blame] | 1265 | clk_unprepare(spi_imx->clk_ipg); |
| 1266 | clk_unprepare(spi_imx->clk_per); |
Robin Gong | f62cacc | 2014-09-11 09:18:44 +0800 | [diff] [blame] | 1267 | spi_imx_sdma_exit(spi_imx); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1268 | spi_master_put(master); |
| 1269 | |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1270 | return 0; |
| 1271 | } |
| 1272 | |
| 1273 | static struct platform_driver spi_imx_driver = { |
| 1274 | .driver = { |
| 1275 | .name = DRIVER_NAME, |
Shawn Guo | 22a85e4 | 2011-07-10 01:16:41 +0800 | [diff] [blame] | 1276 | .of_match_table = spi_imx_dt_ids, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1277 | }, |
Uwe Kleine-König | f4ba631 | 2010-09-09 15:29:01 +0200 | [diff] [blame] | 1278 | .id_table = spi_imx_devtype, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1279 | .probe = spi_imx_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1280 | .remove = spi_imx_remove, |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1281 | }; |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 1282 | module_platform_driver(spi_imx_driver); |
Uwe Kleine-König | 6cdeb00 | 2009-10-01 15:44:28 -0700 | [diff] [blame] | 1283 | |
| 1284 | MODULE_DESCRIPTION("SPI Master Controller driver"); |
| 1285 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
| 1286 | MODULE_LICENSE("GPL"); |
Fabio Estevam | 3133fba3 | 2013-01-07 20:42:55 -0200 | [diff] [blame] | 1287 | MODULE_ALIAS("platform:" DRIVER_NAME); |