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Sascha Hauer9f0749e2012-02-28 21:57:50 +01001/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Shawn Guo36dffd82013-04-07 10:49:34 +080012#include "skeleton.dtsi"
Sascha Hauer9f0749e2012-02-28 21:57:50 +010013
14/ {
15 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +080016 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 gpio4 = &gpio5;
21 gpio5 = &gpio6;
Sascha Hauer6a3c0b32013-06-25 15:51:54 +020022 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
Alexander Shiyana5a641a2013-05-01 14:46:57 +040030 spi0 = &cspi1;
31 spi1 = &cspi2;
32 spi2 = &cspi3;
Sascha Hauer9f0749e2012-02-28 21:57:50 +010033 };
34
Fabio Estevam6189bc32013-06-28 16:50:33 +020035 aitc: aitc-interrupt-controller@e0000000 {
36 compatible = "fsl,imx27-aitc", "fsl,avic";
Sascha Hauer9f0749e2012-02-28 21:57:50 +010037 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0x10040000 0x1000>;
40 };
41
42 clocks {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 osc26m {
47 compatible = "fsl,imx-osc26m", "fixed-clock";
48 clock-frequency = <26000000>;
49 };
50 };
51
52 soc {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "simple-bus";
Fabio Estevam6189bc32013-06-28 16:50:33 +020056 interrupt-parent = <&aitc>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +010057 ranges;
58
59 aipi@10000000 { /* AIPI1 */
60 compatible = "fsl,aipi-bus", "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
Fabio Estevam3e24b052012-11-21 17:19:38 -020063 reg = <0x10000000 0x20000>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +010064 ranges;
65
Alexander Shiyanb858c342013-06-08 18:39:36 +040066 dma: dma@10001000 {
67 compatible = "fsl,imx27-dma";
68 reg = <0x10001000 0x1000>;
69 interrupts = <32>;
70 clocks = <&clks 50>, <&clks 70>;
71 clock-names = "ipg", "ahb";
72 #dma-cells = <1>;
73 #dma-channels = <16>;
74 };
75
Sascha Hauer7b7d6722012-11-15 09:31:52 +010076 wdog: wdog@10002000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +010077 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
Sascha Hauerca26d042013-03-14 13:08:57 +010078 reg = <0x10002000 0x1000>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +010079 interrupts = <27>;
Fabio Estevamc20736f2012-11-28 15:55:30 -020080 clocks = <&clks 0>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +010081 };
82
Sascha Hauerca26d042013-03-14 13:08:57 +010083 gpt1: timer@10003000 {
84 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
85 reg = <0x10003000 0x1000>;
86 interrupts = <26>;
Sascha Hauerb700c112013-03-14 13:09:02 +010087 clocks = <&clks 46>, <&clks 61>;
88 clock-names = "ipg", "per";
Sascha Hauerca26d042013-03-14 13:08:57 +010089 };
90
91 gpt2: timer@10004000 {
92 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
93 reg = <0x10004000 0x1000>;
94 interrupts = <25>;
Sascha Hauerb700c112013-03-14 13:09:02 +010095 clocks = <&clks 45>, <&clks 61>;
96 clock-names = "ipg", "per";
Sascha Hauerca26d042013-03-14 13:08:57 +010097 };
98
99 gpt3: timer@10005000 {
100 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
101 reg = <0x10005000 0x1000>;
102 interrupts = <24>;
Sascha Hauerb700c112013-03-14 13:09:02 +0100103 clocks = <&clks 44>, <&clks 61>;
104 clock-names = "ipg", "per";
Sascha Hauerca26d042013-03-14 13:08:57 +0100105 };
106
Alexander Shiyana392d042013-06-23 10:54:47 +0400107 pwm: pwm@10006000 {
Gwenhael Goavec-Merou08f4881a2013-04-14 09:44:25 +0200108 compatible = "fsl,imx27-pwm";
109 reg = <0x10006000 0x1000>;
110 interrupts = <23>;
111 clocks = <&clks 34>, <&clks 61>;
112 clock-names = "ipg", "per";
113 };
114
Alexander Shiyan6c04ad22013-06-23 10:54:50 +0400115 kpp: kpp@10008000 {
116 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
117 reg = <0x10008000 0x1000>;
118 interrupts = <21>;
119 clocks = <&clks 37>;
120 status = "disabled";
121 };
122
Markus Pargmann6a486b72013-07-01 17:21:22 +0800123 owire: owire@10009000 {
124 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
125 reg = <0x10009000 0x1000>;
126 clocks = <&clks 35>;
127 status = "disabled";
128 };
129
Shawn Guo0c456cf2012-04-02 14:39:26 +0800130 uart1: serial@1000a000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100131 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
132 reg = <0x1000a000 0x1000>;
133 interrupts = <20>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200134 clocks = <&clks 81>, <&clks 61>;
135 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100136 status = "disabled";
137 };
138
Shawn Guo0c456cf2012-04-02 14:39:26 +0800139 uart2: serial@1000b000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100140 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
141 reg = <0x1000b000 0x1000>;
142 interrupts = <19>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200143 clocks = <&clks 80>, <&clks 61>;
144 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100145 status = "disabled";
146 };
147
Shawn Guo0c456cf2012-04-02 14:39:26 +0800148 uart3: serial@1000c000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100149 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
150 reg = <0x1000c000 0x1000>;
151 interrupts = <18>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200152 clocks = <&clks 79>, <&clks 61>;
153 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100154 status = "disabled";
155 };
156
Shawn Guo0c456cf2012-04-02 14:39:26 +0800157 uart4: serial@1000d000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100158 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
159 reg = <0x1000d000 0x1000>;
160 interrupts = <17>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200161 clocks = <&clks 78>, <&clks 61>;
162 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100163 status = "disabled";
164 };
165
166 cspi1: cspi@1000e000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,imx27-cspi";
170 reg = <0x1000e000 0x1000>;
171 interrupts = <16>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200172 clocks = <&clks 53>, <&clks 53>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200173 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100174 status = "disabled";
175 };
176
177 cspi2: cspi@1000f000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx27-cspi";
181 reg = <0x1000f000 0x1000>;
182 interrupts = <15>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200183 clocks = <&clks 52>, <&clks 52>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200184 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100185 status = "disabled";
186 };
187
188 i2c1: i2c@10012000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800191 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100192 reg = <0x10012000 0x1000>;
193 interrupts = <12>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200194 clocks = <&clks 40>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100195 status = "disabled";
196 };
197
Alexander Shiyan0e7b01a2013-06-08 18:39:37 +0400198 sdhci1: sdhci@10013000 {
199 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
200 reg = <0x10013000 0x1000>;
201 interrupts = <11>;
202 clocks = <&clks 30>, <&clks 60>;
203 clock-names = "ipg", "per";
204 dmas = <&dma 7>;
205 dma-names = "rx-tx";
206 status = "disabled";
207 };
208
209 sdhci2: sdhci@10014000 {
210 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
211 reg = <0x10014000 0x1000>;
212 interrupts = <10>;
213 clocks = <&clks 29>, <&clks 60>;
214 clock-names = "ipg", "per";
215 dmas = <&dma 6>;
216 dma-names = "rx-tx";
217 status = "disabled";
218 };
219
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100220 gpio1: gpio@10015000 {
221 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
222 reg = <0x10015000 0x100>;
223 interrupts = <8>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800227 #interrupt-cells = <2>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100228 };
229
230 gpio2: gpio@10015100 {
231 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
232 reg = <0x10015100 0x100>;
233 interrupts = <8>;
234 gpio-controller;
235 #gpio-cells = <2>;
236 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800237 #interrupt-cells = <2>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100238 };
239
240 gpio3: gpio@10015200 {
241 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
242 reg = <0x10015200 0x100>;
243 interrupts = <8>;
244 gpio-controller;
245 #gpio-cells = <2>;
246 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800247 #interrupt-cells = <2>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100248 };
249
250 gpio4: gpio@10015300 {
251 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
252 reg = <0x10015300 0x100>;
253 interrupts = <8>;
254 gpio-controller;
255 #gpio-cells = <2>;
256 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800257 #interrupt-cells = <2>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100258 };
259
260 gpio5: gpio@10015400 {
261 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
262 reg = <0x10015400 0x100>;
263 interrupts = <8>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800267 #interrupt-cells = <2>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100268 };
269
270 gpio6: gpio@10015500 {
271 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
272 reg = <0x10015500 0x100>;
273 interrupts = <8>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800277 #interrupt-cells = <2>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100278 };
279
Alexander Shiyan6e228e82013-06-23 10:54:46 +0400280 audmux: audmux@10016000 {
281 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
282 reg = <0x10016000 0x1000>;
283 clocks = <&clks 0>;
284 clock-names = "audmux";
285 };
286
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100287 cspi3: cspi@10017000 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "fsl,imx27-cspi";
291 reg = <0x10017000 0x1000>;
292 interrupts = <6>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200293 clocks = <&clks 51>, <&clks 51>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200294 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100295 status = "disabled";
296 };
297
Sascha Hauerca26d042013-03-14 13:08:57 +0100298 gpt4: timer@10019000 {
299 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
300 reg = <0x10019000 0x1000>;
301 interrupts = <4>;
Sascha Hauerb700c112013-03-14 13:09:02 +0100302 clocks = <&clks 43>, <&clks 61>;
303 clock-names = "ipg", "per";
Sascha Hauerca26d042013-03-14 13:08:57 +0100304 };
305
306 gpt5: timer@1001a000 {
307 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
308 reg = <0x1001a000 0x1000>;
309 interrupts = <3>;
Sascha Hauerb700c112013-03-14 13:09:02 +0100310 clocks = <&clks 42>, <&clks 61>;
311 clock-names = "ipg", "per";
Sascha Hauerca26d042013-03-14 13:08:57 +0100312 };
313
Shawn Guo0c456cf2012-04-02 14:39:26 +0800314 uart5: serial@1001b000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100315 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
316 reg = <0x1001b000 0x1000>;
317 interrupts = <49>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200318 clocks = <&clks 77>, <&clks 61>;
319 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100320 status = "disabled";
321 };
322
Shawn Guo0c456cf2012-04-02 14:39:26 +0800323 uart6: serial@1001c000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100324 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
325 reg = <0x1001c000 0x1000>;
326 interrupts = <48>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200327 clocks = <&clks 78>, <&clks 61>;
328 clock-names = "ipg", "per";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100329 status = "disabled";
330 };
331
332 i2c2: i2c@1001d000 {
333 #address-cells = <1>;
334 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800335 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100336 reg = <0x1001d000 0x1000>;
337 interrupts = <1>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200338 clocks = <&clks 39>;
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100339 status = "disabled";
340 };
341
Alexander Shiyan0e7b01a2013-06-08 18:39:37 +0400342 sdhci3: sdhci@1001e000 {
343 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
344 reg = <0x1001e000 0x1000>;
345 interrupts = <9>;
346 clocks = <&clks 28>, <&clks 60>;
347 clock-names = "ipg", "per";
348 dmas = <&dma 36>;
349 dma-names = "rx-tx";
350 status = "disabled";
351 };
352
Sascha Hauerca26d042013-03-14 13:08:57 +0100353 gpt6: timer@1001f000 {
354 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
355 reg = <0x1001f000 0x1000>;
356 interrupts = <2>;
Sascha Hauerb700c112013-03-14 13:09:02 +0100357 clocks = <&clks 41>, <&clks 61>;
358 clock-names = "ipg", "per";
Sascha Hauerca26d042013-03-14 13:08:57 +0100359 };
Sascha Hauera82848e2013-06-25 15:51:48 +0200360
361 iim: iim@10028000 {
362 compatible = "fsl,imx27-iim";
363 reg = <0x10028000 0x1000>;
364 interrupts = <62>;
365 clocks = <&clks 38>;
366 };
Fabio Estevam3e24b052012-11-21 17:19:38 -0200367 };
368
369 aipi@10020000 { /* AIPI2 */
370 compatible = "fsl,aipi-bus", "simple-bus";
371 #address-cells = <1>;
372 #size-cells = <1>;
373 reg = <0x10020000 0x20000>;
374 ranges;
375
Markus Pargmann5e57b242013-06-28 16:50:34 +0200376 fb: fb@10021000 {
377 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
378 interrupts = <61>;
379 reg = <0x10021000 0x1000>;
380 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
381 clock-names = "ipg", "ahb", "per";
382 status = "disabled";
383 };
384
Alexander Shiyan93b331c2013-06-15 16:22:58 +0400385 coda: coda@10023000 {
386 compatible = "fsl,imx27-vpu";
387 reg = <0x10023000 0x0200>;
388 interrupts = <53>;
389 clocks = <&clks 57>, <&clks 66>;
390 clock-names = "per", "ahb";
391 iram = <&iram>;
392 };
393
Alexander Shiyane4b6a052013-06-23 10:54:45 +0400394 sahara2: sahara@10025000 {
395 compatible = "fsl,imx27-sahara";
396 reg = <0x10025000 0x1000>;
397 interrupts = <59>;
398 clocks = <&clks 32>, <&clks 64>;
399 clock-names = "ipg", "ahb";
400 };
401
Alexander Shiyan93b331c2013-06-15 16:22:58 +0400402 clks: ccm@10027000{
403 compatible = "fsl,imx27-ccm";
404 reg = <0x10027000 0x1000>;
405 #clock-cells = <1>;
406 };
407
Shawn Guo0c456cf2012-04-02 14:39:26 +0800408 fec: ethernet@1002b000 {
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100409 compatible = "fsl,imx27-fec";
410 reg = <0x1002b000 0x4000>;
411 interrupts = <50>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200412 clocks = <&clks 48>, <&clks 67>, <&clks 0>;
413 clock-names = "ipg", "ahb", "ptp";
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100414 status = "disabled";
415 };
416 };
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100417
418 nfc: nand@d8000000 {
Uwe Kleine-König37787362012-04-23 11:23:42 +0200419 #address-cells = <1>;
420 #size-cells = <1>;
Uwe Kleine-König37787362012-04-23 11:23:42 +0200421 compatible = "fsl,imx27-nand";
422 reg = <0xd8000000 0x1000>;
423 interrupts = <29>;
Fabio Estevamc20736f2012-11-28 15:55:30 -0200424 clocks = <&clks 54>;
Uwe Kleine-König37787362012-04-23 11:23:42 +0200425 status = "disabled";
426 };
Alexander Shiyanff1450f2013-06-23 10:54:48 +0400427
428 iram: iram@ffff4c00 {
429 compatible = "mmio-sram";
430 reg = <0xffff4c00 0xb400>;
431 };
Sascha Hauer9f0749e2012-02-28 21:57:50 +0100432 };
433};