blob: 0127d11d14885e434a31093e064f608b2c042611 [file] [log] [blame]
Lokesh Vutla11e21912013-12-19 18:03:38 +05301/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
Sourav Poddarc540b472013-12-19 18:03:39 +053015#include <dt-bindings/pwm/pwm.h>
Sourav Poddar51724db2013-12-19 18:03:41 +053016#include <dt-bindings/gpio/gpio.h>
Lokesh Vutla11e21912013-12-19 18:03:38 +053017
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
Sourav Poddarc540b472013-12-19 18:03:39 +053021
Sathya Prakash M R0bacb522014-03-24 16:31:56 +053022 aliases {
23 display0 = &lcd0;
24 };
25
Lokesh Vutla24a1eb42017-01-18 09:33:24 +053026 chosen {
27 stdout-path = &uart0;
28 };
29
Peter Ujfalusi390810a2015-07-02 17:06:25 +030030 evm_v3_3d: fixedregulator-v3_3d {
Balaji T K506be3f2014-03-03 20:20:18 +053031 compatible = "regulator-fixed";
Peter Ujfalusi390810a2015-07-02 17:06:25 +030032 regulator-name = "evm_v3_3d";
Balaji T K506be3f2014-03-03 20:20:18 +053033 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 enable-active-high;
36 };
37
Dave Gerlachb2873bf2014-05-05 14:58:28 -050038 vtt_fixed: fixedregulator-vtt {
39 compatible = "regulator-fixed";
40 regulator-name = "vtt_fixed";
41 regulator-min-microvolt = <1500000>;
42 regulator-max-microvolt = <1500000>;
43 regulator-always-on;
44 regulator-boot-on;
45 enable-active-high;
46 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
47 };
48
Eyal Reizerb6bbf592015-05-04 15:24:24 +030049 vmmcwl_fixed: fixedregulator-mmcwl {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmcwl_fixed";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
55 enable-active-high;
56 };
57
Peter Ujfalusifdc223c2017-12-15 14:09:32 +020058 lcd_bl: backlight {
Sourav Poddarc540b472013-12-19 18:03:39 +053059 compatible = "pwm-backlight";
60 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
61 brightness-levels = <0 51 53 56 62 75 101 152 255>;
62 default-brightness-level = <8>;
63 };
Sourav Poddar51724db2013-12-19 18:03:41 +053064
Javier Martinez Canillas18ad99d2016-08-01 12:46:57 -040065 matrix_keypad: matrix_keypad0 {
Sourav Poddar51724db2013-12-19 18:03:41 +053066 compatible = "gpio-matrix-keypad";
67 debounce-delay-ms = <5>;
68 col-scan-delay-us = <2>;
69
Dave Gerlach6a156a02018-11-07 10:34:19 +053070 pinctrl-names = "default", "sleep";
71 pinctrl-0 = <&matrix_keypad_default>;
72 pinctrl-1 = <&matrix_keypad_sleep>;
73
74 linux,wakeup;
75
76 row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
Sourav Poddar51724db2013-12-19 18:03:41 +053077 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
78 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
79
80 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
81 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
82
83 linux,keymap = <0x00000201 /* P1 */
84 0x00010202 /* P2 */
85 0x01000067 /* UP */
86 0x0101006a /* RIGHT */
87 0x02000069 /* LEFT */
88 0x0201006c>; /* DOWN */
89 };
Sathya Prakash M R0bacb522014-03-24 16:31:56 +053090
91 lcd0: display {
92 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
93 label = "lcd";
94
Peter Ujfalusifdc223c2017-12-15 14:09:32 +020095 backlight = <&lcd_bl>;
96
Sathya Prakash M R0bacb522014-03-24 16:31:56 +053097 panel-timing {
98 clock-frequency = <33000000>;
99 hactive = <800>;
100 vactive = <480>;
101 hfront-porch = <210>;
102 hback-porch = <16>;
103 hsync-len = <30>;
104 vback-porch = <10>;
105 vfront-porch = <22>;
106 vsync-len = <13>;
107 hsync-active = <0>;
108 vsync-active = <0>;
109 de-active = <1>;
110 pixelclk-active = <1>;
111 };
112
113 port {
114 lcd_in: endpoint {
115 remote-endpoint = <&dpi_out>;
116 };
117 };
118 };
Lad, Prabhakar3aa59202015-03-12 23:38:21 +0000119
120 /* fixed 12MHz oscillator */
121 refclk: oscillator {
122 #clock-cells = <0>;
123 compatible = "fixed-clock";
124 clock-frequency = <12000000>;
125 };
126
Keerthyfff51e72015-08-18 15:11:14 +0530127 /* fixed 32k external oscillator clock */
128 clk_32k_rtc: clk_32k_rtc {
129 #clock-cells = <0>;
130 compatible = "fixed-clock";
131 clock-frequency = <32768>;
132 };
133
Javier Martinez Canillas4e8603e2016-04-01 16:20:21 -0400134 sound0: sound0 {
Peter Ujfalusicf9a4852015-07-02 17:06:28 +0300135 compatible = "simple-audio-card";
136 simple-audio-card,name = "AM437x-GP-EVM";
137 simple-audio-card,widgets =
138 "Headphone", "Headphone Jack",
139 "Line", "Line In";
140 simple-audio-card,routing =
141 "Headphone Jack", "HPLOUT",
142 "Headphone Jack", "HPROUT",
143 "LINE1L", "Line In",
144 "LINE1R", "Line In";
145 simple-audio-card,format = "dsp_b";
146 simple-audio-card,bitclock-master = <&sound0_master>;
147 simple-audio-card,frame-master = <&sound0_master>;
148 simple-audio-card,bitclock-inversion;
149
150 simple-audio-card,cpu {
151 sound-dai = <&mcasp1>;
152 system-clock-frequency = <12000000>;
153 };
154
155 sound0_master: simple-audio-card,codec {
156 sound-dai = <&tlv320aic3106>;
157 system-clock-frequency = <12000000>;
158 };
159 };
Faiz Abbas092976e2017-06-20 10:39:21 +0530160
161 beeper: beeper {
162 compatible = "gpio-beeper";
163 pinctrl-names = "default";
164 pinctrl-0 = <&beeper_pins>;
165 gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
166 };
Lokesh Vutla11e21912013-12-19 18:03:38 +0530167};
168
169&am43xx_pinmux {
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300170 pinctrl-names = "default", "sleep";
Dave Gerlach7235ed12018-11-07 10:34:17 +0530171 pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300172 pinctrl-1 = <&wlan_pins_sleep>;
173
Dave Gerlach865852a2018-11-07 10:34:15 +0530174 ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
175 pinctrl-single,pins = <
176 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
177 >;
178 };
179
Lokesh Vutla11e21912013-12-19 18:03:38 +0530180 i2c0_pins: i2c0_pins {
181 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300182 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
183 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
Lokesh Vutla11e21912013-12-19 18:03:38 +0530184 >;
185 };
186
187 i2c1_pins: i2c1_pins {
188 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300189 AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
190 AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
Lokesh Vutla11e21912013-12-19 18:03:38 +0530191 >;
192 };
Sourav Poddarc540b472013-12-19 18:03:39 +0530193
Balaji T K506be3f2014-03-03 20:20:18 +0530194 mmc1_pins: pinmux_mmc1_pins {
195 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300196 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
Balaji T K506be3f2014-03-03 20:20:18 +0530197 >;
198 };
199
Sourav Poddarc540b472013-12-19 18:03:39 +0530200 ecap0_pins: backlight_pins {
201 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300202 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
Sourav Poddarc540b472013-12-19 18:03:39 +0530203 >;
204 };
Sekhar Nori0ebc1e22014-04-30 15:43:25 +0300205
206 pixcir_ts_pins: pixcir_ts_pins {
207 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300208 AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
Sekhar Nori0ebc1e22014-04-30 15:43:25 +0300209 >;
210 };
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530211
212 cpsw_default: cpsw_default {
213 pinctrl-single,pins = <
214 /* Slave 1 */
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300215 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
216 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
217 AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
218 AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
219 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
220 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
221 AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
222 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
223 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
224 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
225 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
226 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530227 >;
228 };
229
230 cpsw_sleep: cpsw_sleep {
231 pinctrl-single,pins = <
232 /* Slave 1 reset value */
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300233 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
234 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
235 AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
236 AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
237 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
238 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
239 AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
240 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
241 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
242 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
243 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
244 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530245 >;
246 };
247
248 davinci_mdio_default: davinci_mdio_default {
249 pinctrl-single,pins = <
250 /* MDIO */
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300251 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
252 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530253 >;
254 };
255
256 davinci_mdio_sleep: davinci_mdio_sleep {
257 pinctrl-single,pins = <
258 /* MDIO reset value */
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300259 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
260 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530261 >;
262 };
Pekon Gupta99ffa642014-05-19 14:45:46 +0530263
264 nand_flash_x8: nand_flash_x8 {
265 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300266 AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
267 AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
268 AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
269 AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
270 AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
271 AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
272 AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
273 AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
274 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
275 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
276 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
277 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
278 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
279 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
280 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
Pekon Gupta99ffa642014-05-19 14:45:46 +0530281 >;
282 };
Sathya Prakash M R0bacb522014-03-24 16:31:56 +0530283
284 dss_pins: dss_pins {
285 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300286 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
287 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
288 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
289 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
290 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
291 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
292 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
293 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
294 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
295 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
296 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
297 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
298 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
299 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
300 AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
301 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
302 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
303 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
304 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
305 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
306 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
307 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
308 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
309 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
310 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
311 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
312 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
313 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
Sathya Prakash M R0bacb522014-03-24 16:31:56 +0530314
315 >;
316 };
317
Peter Ujfalusi593113e2015-07-02 17:06:24 +0300318 display_mux_pins: display_mux_pins {
Sathya Prakash M R0bacb522014-03-24 16:31:56 +0530319 pinctrl-single,pins = <
320 /* GPIO 5_8 to select LCD / HDMI */
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300321 AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
Sathya Prakash M R0bacb522014-03-24 16:31:56 +0530322 >;
323 };
Mugunthan V N4b1ce232014-07-18 11:29:11 +0530324
325 dcan0_default: dcan0_default_pins {
326 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300327 AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
328 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
Mugunthan V N4b1ce232014-07-18 11:29:11 +0530329 >;
330 };
331
Roger Quadrosf95b1062015-08-18 17:01:57 +0300332 dcan0_sleep: dcan0_sleep_pins {
333 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300334 AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
335 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
Roger Quadrosf95b1062015-08-18 17:01:57 +0300336 >;
337 };
338
Mugunthan V N4b1ce232014-07-18 11:29:11 +0530339 dcan1_default: dcan1_default_pins {
340 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300341 AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
342 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
Mugunthan V N4b1ce232014-07-18 11:29:11 +0530343 >;
344 };
Benoit Parrotc788a7f2014-12-18 21:54:14 +0530345
Roger Quadrosf95b1062015-08-18 17:01:57 +0300346 dcan1_sleep: dcan1_sleep_pins {
347 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300348 AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
349 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
Roger Quadrosf95b1062015-08-18 17:01:57 +0300350 >;
351 };
352
Benoit Parrotc788a7f2014-12-18 21:54:14 +0530353 vpfe0_pins_default: vpfe0_pins_default {
354 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300355 AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
356 AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
357 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
358 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
359 AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
360 AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
361 AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
362 AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
363 AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
364 AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
365 AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
366 AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
367 AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
Benoit Parrotc788a7f2014-12-18 21:54:14 +0530368 >;
369 };
370
371 vpfe0_pins_sleep: vpfe0_pins_sleep {
372 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300373 AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
374 AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
375 AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
376 AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
377 AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
378 AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
379 AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
380 AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
381 AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
382 AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
383 AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
384 AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
385 AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
Benoit Parrotc788a7f2014-12-18 21:54:14 +0530386 >;
387 };
388
389 vpfe1_pins_default: vpfe1_pins_default {
390 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300391 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
392 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
393 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
394 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
395 AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
396 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
397 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
398 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
399 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
400 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
401 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
402 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
403 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
Benoit Parrotc788a7f2014-12-18 21:54:14 +0530404 >;
405 };
406
407 vpfe1_pins_sleep: vpfe1_pins_sleep {
408 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300409 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
410 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
411 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
412 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
413 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
414 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
415 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
416 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
417 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
418 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
419 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
420 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
421 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
Benoit Parrotc788a7f2014-12-18 21:54:14 +0530422 >;
423 };
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300424
425 mmc3_pins_default: pinmux_mmc3_pins_default {
426 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300427 AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
428 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
429 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
430 AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
431 AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
432 AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300433 >;
434 };
435
436 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
437 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300438 AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
439 AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
440 AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
441 AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
442 AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
443 AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300444 >;
445 };
446
447 wlan_pins_default: pinmux_wlan_pins_default {
448 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300449 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
450 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
451 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300452 >;
453 };
454
455 wlan_pins_sleep: pinmux_wlan_pins_sleep {
456 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300457 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
458 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
459 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300460 >;
461 };
462
463 uart3_pins: uart3_pins {
464 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300465 AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
466 AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
467 AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
468 AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300469 >;
470 };
Peter Ujfalusid3d92af2015-07-02 17:06:27 +0300471
472 mcasp1_pins: mcasp1_pins {
473 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300474 AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
475 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
476 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
477 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
Peter Ujfalusid3d92af2015-07-02 17:06:27 +0300478 >;
479 };
480
481 mcasp1_sleep_pins: mcasp1_sleep_pins {
482 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300483 AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
484 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
485 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
486 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
Peter Ujfalusid3d92af2015-07-02 17:06:27 +0300487 >;
488 };
Roger Quadros50336f52015-08-04 18:34:59 +0300489
490 gpio0_pins: gpio0_pins {
491 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300492 AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
Roger Quadros50336f52015-08-04 18:34:59 +0300493 >;
494 };
Roger Quadroseb157c82015-08-04 18:35:00 +0300495
496 emmc_pins_default: emmc_pins_default {
497 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300498 AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
499 AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
500 AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
501 AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
502 AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
503 AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
504 AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
505 AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
506 AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
507 AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
Roger Quadroseb157c82015-08-04 18:35:00 +0300508 >;
509 };
510
511 emmc_pins_sleep: emmc_pins_sleep {
512 pinctrl-single,pins = <
Javier Martinez Canillas596bad72015-11-13 01:53:54 -0300513 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
514 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
515 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
516 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
517 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
518 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
519 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
520 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
521 AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
522 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
Roger Quadroseb157c82015-08-04 18:35:00 +0300523 >;
524 };
Vignesh Rbb7d9782017-03-22 21:06:34 +0530525
Faiz Abbas092976e2017-06-20 10:39:21 +0530526 beeper_pins: beeper_pins {
527 pinctrl-single,pins = <
528 AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
529 >;
530 };
531
Dave Gerlach88f527d2018-11-07 10:34:16 +0530532 unused_pins: unused_pins {
533 pinctrl-single,pins = <
534 AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
535 AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
536 AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
537 AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
538 AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
539 AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
540 AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)
541 AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7)
542 AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7)
543 AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7)
544 AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7)
545 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
546 AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
547 AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7)
548 AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7)
549 AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7)
550 AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7)
551 AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7)
552 AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
553 AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7)
554 AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
555 AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7)
556 AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7)
557 AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7)
558 AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE)
559 AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
560 AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
561 AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7)
562 AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7)
563 AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7)
564 AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7)
565 AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7)
566 AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7)
567 AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7)
568 AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7)
569 AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7)
570 AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7)
571 AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7)
572 AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7)
573 AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7)
574 AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7)
575 AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7)
576 AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7)
577 AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7)
578 >;
579 };
Dave Gerlach7235ed12018-11-07 10:34:17 +0530580
581 debugss_pins: pinmux_debugss_pins {
582 pinctrl-single,pins = <
583 AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
584 AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
585 AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
586 AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
587 AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
588 AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
589 AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
590 >;
591 };
Dave Gerlach74fe9bf2018-11-07 10:34:18 +0530592
593 uart0_pins_default: uart0_pins_default {
594 pinctrl-single,pins = <
595 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
596 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
597 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
598 AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
599 >;
600 };
601
602 uart0_pins_sleep: uart0_pins_sleep {
603 pinctrl-single,pins = <
604 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
605 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
606 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
607 AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
608 >;
609 };
Dave Gerlach6a156a02018-11-07 10:34:19 +0530610
611 matrix_keypad_default: matrix_keypad_default {
612 pinctrl-single,pins = <
613 AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)
614 AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7)
615 AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
616 AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
617 >;
618 };
619
620 matrix_keypad_sleep: matrix_keypad_sleep {
621 pinctrl-single,pins = <
622 AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7)
623 AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7)
624 AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
625 AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
626 >;
627 };
Vignesh Rbb7d9782017-03-22 21:06:34 +0530628};
629
630&uart0 {
631 status = "okay";
Dave Gerlach74fe9bf2018-11-07 10:34:18 +0530632 pinctrl-names = "default", "sleep";
Vignesh Rbb7d9782017-03-22 21:06:34 +0530633 pinctrl-0 = <&uart0_pins_default>;
Dave Gerlach74fe9bf2018-11-07 10:34:18 +0530634 pinctrl-1 = <&uart0_pins_sleep>;
Lokesh Vutla11e21912013-12-19 18:03:38 +0530635};
636
637&i2c0 {
Keerthy1fc98142014-07-09 11:06:31 +0530638 status = "okay";
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2c0_pins>;
Nishanth Menon93166412014-09-03 13:46:21 -0500641 clock-frequency = <100000>;
Keerthy0e2da5e2014-07-09 11:06:32 +0530642
643 tps65218: tps65218@24 {
644 reg = <0x24>;
645 compatible = "ti,tps65218";
Peter Ujfalusief0ff0a2018-05-08 16:20:50 +0300646 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
Keerthy0e2da5e2014-07-09 11:06:32 +0530647 interrupt-controller;
648 #interrupt-cells = <2>;
649
650 dcdc1: regulator-dcdc1 {
Keerthy0e2da5e2014-07-09 11:06:32 +0530651 regulator-name = "vdd_core";
652 regulator-min-microvolt = <912000>;
653 regulator-max-microvolt = <1144000>;
654 regulator-boot-on;
655 regulator-always-on;
656 };
657
658 dcdc2: regulator-dcdc2 {
Keerthy0e2da5e2014-07-09 11:06:32 +0530659 regulator-name = "vdd_mpu";
660 regulator-min-microvolt = <912000>;
661 regulator-max-microvolt = <1378000>;
662 regulator-boot-on;
663 regulator-always-on;
664 };
665
666 dcdc3: regulator-dcdc3 {
Keerthy0e2da5e2014-07-09 11:06:32 +0530667 regulator-name = "vdcdc3";
Keerthy0e2da5e2014-07-09 11:06:32 +0530668 regulator-boot-on;
669 regulator-always-on;
Keerthy1bc5e132016-08-11 10:57:48 +0530670 regulator-state-mem {
671 regulator-on-in-suspend;
672 };
Tero Kristo7ec32992016-08-11 10:57:49 +0530673 regulator-state-disk {
674 regulator-off-in-suspend;
675 };
Keerthy0e2da5e2014-07-09 11:06:32 +0530676 };
Keerthy1bc5e132016-08-11 10:57:48 +0530677
Keerthy0e2da5e2014-07-09 11:06:32 +0530678 dcdc5: regulator-dcdc5 {
Keerthy0e2da5e2014-07-09 11:06:32 +0530679 regulator-name = "v1_0bat";
680 regulator-min-microvolt = <1000000>;
681 regulator-max-microvolt = <1000000>;
Dave Gerlach1e9f7472015-08-05 16:19:46 +0530682 regulator-boot-on;
683 regulator-always-on;
Keerthy1bc5e132016-08-11 10:57:48 +0530684 regulator-state-mem {
685 regulator-on-in-suspend;
686 };
Keerthy0e2da5e2014-07-09 11:06:32 +0530687 };
688
689 dcdc6: regulator-dcdc6 {
Keerthy0e2da5e2014-07-09 11:06:32 +0530690 regulator-name = "v1_8bat";
691 regulator-min-microvolt = <1800000>;
692 regulator-max-microvolt = <1800000>;
Dave Gerlach1e9f7472015-08-05 16:19:46 +0530693 regulator-boot-on;
694 regulator-always-on;
Keerthy1bc5e132016-08-11 10:57:48 +0530695 regulator-state-mem {
696 regulator-on-in-suspend;
697 };
Keerthy0e2da5e2014-07-09 11:06:32 +0530698 };
699
700 ldo1: regulator-ldo1 {
Keerthy0e2da5e2014-07-09 11:06:32 +0530701 regulator-min-microvolt = <1800000>;
702 regulator-max-microvolt = <1800000>;
703 regulator-boot-on;
704 regulator-always-on;
705 };
706 };
Lad, Prabhakar3aa59202015-03-12 23:38:21 +0000707
708 ov2659@30 {
709 compatible = "ovti,ov2659";
710 reg = <0x30>;
711
712 clocks = <&refclk 0>;
713 clock-names = "xvclk";
714
715 port {
716 ov2659_0: endpoint {
717 remote-endpoint = <&vpfe1_ep>;
718 link-frequencies = /bits/ 64 <70000000>;
719 };
720 };
721 };
Lokesh Vutla11e21912013-12-19 18:03:38 +0530722};
723
724&i2c1 {
Keerthy1fc98142014-07-09 11:06:31 +0530725 status = "okay";
726 pinctrl-names = "default";
727 pinctrl-0 = <&i2c1_pins>;
Sekhar Nori0ebc1e22014-04-30 15:43:25 +0300728 pixcir_ts@5c {
729 compatible = "pixcir,pixcir_tangoc";
730 pinctrl-names = "default";
731 pinctrl-0 = <&pixcir_ts_pins>;
732 reg = <0x5c>;
Sekhar Nori0ebc1e22014-04-30 15:43:25 +0300733
734 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
735
Vignesh Rf513d222015-10-14 19:24:25 +0530736 /*
737 * 0x264 represents the offset of padconf register of
738 * gpio3_22 from am43xx_pinmux base.
739 */
Grygorii Strashko95e7d032015-12-28 15:52:39 +0200740 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
Vignesh Rf513d222015-10-14 19:24:25 +0530741 <&am43xx_pinmux 0x264>;
742 interrupt-names = "tsc", "wakeup";
743
Roger Quadrosf0486152014-07-28 10:11:37 -0700744 touchscreen-size-x = <1024>;
745 touchscreen-size-y = <600>;
Vignesh Rf513d222015-10-14 19:24:25 +0530746 wakeup-source;
Sekhar Nori0ebc1e22014-04-30 15:43:25 +0300747 };
Lad, Prabhakar3aa59202015-03-12 23:38:21 +0000748
749 ov2659@30 {
750 compatible = "ovti,ov2659";
751 reg = <0x30>;
752
753 clocks = <&refclk 0>;
754 clock-names = "xvclk";
755
756 port {
757 ov2659_1: endpoint {
758 remote-endpoint = <&vpfe0_ep>;
759 link-frequencies = /bits/ 64 <70000000>;
760 };
761 };
762 };
Peter Ujfalusi6076b152015-07-02 17:06:26 +0300763
764 tlv320aic3106: tlv320aic3106@1b {
Peter Ujfalusicf9a4852015-07-02 17:06:28 +0300765 #sound-dai-cells = <0>;
Peter Ujfalusi6076b152015-07-02 17:06:26 +0300766 compatible = "ti,tlv320aic3106";
767 reg = <0x1b>;
768 status = "okay";
769
770 /* Regulators */
771 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
772 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
773 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
774 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
775 };
Lokesh Vutla11e21912013-12-19 18:03:38 +0530776};
Sourav Poddarc540b472013-12-19 18:03:39 +0530777
778&epwmss0 {
779 status = "okay";
780};
781
Vignesh R0f39f7b2014-11-21 15:44:22 +0530782&tscadc {
783 status = "okay";
784
785 adc {
786 ti,adc-channels = <0 1 2 3 4 5 6 7>;
787 };
788};
789
Sourav Poddarc540b472013-12-19 18:03:39 +0530790&ecap0 {
791 status = "okay";
792 pinctrl-names = "default";
793 pinctrl-0 = <&ecap0_pins>;
794};
Sourav Poddard3d46cc2013-12-19 18:03:40 +0530795
Balaji T K506be3f2014-03-03 20:20:18 +0530796&gpio0 {
Roger Quadros50336f52015-08-04 18:34:59 +0300797 pinctrl-names = "default";
798 pinctrl-0 = <&gpio0_pins>;
Balaji T K506be3f2014-03-03 20:20:18 +0530799 status = "okay";
Roger Quadros50336f52015-08-04 18:34:59 +0300800
801 p23 {
802 gpio-hog;
803 gpios = <23 GPIO_ACTIVE_HIGH>;
804 /* SelEMMCorNAND selects between eMMC and NAND:
805 * Low: NAND
806 * High: eMMC
807 * When changing this line make sure the newly
808 * selected device node is enabled and the previously
809 * selected device node is disabled.
810 */
811 output-low;
812 line-name = "SelEMMCorNAND";
813 };
Balaji T K506be3f2014-03-03 20:20:18 +0530814};
815
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300816&gpio1 {
817 status = "okay";
818};
819
Sourav Poddard3d46cc2013-12-19 18:03:40 +0530820&gpio3 {
821 status = "okay";
822};
823
824&gpio4 {
825 status = "okay";
826};
Balaji T K506be3f2014-03-03 20:20:18 +0530827
Dave Gerlach1ff3859e2014-03-21 10:50:13 +0530828&gpio5 {
Peter Ujfalusi593113e2015-07-02 17:06:24 +0300829 pinctrl-names = "default";
830 pinctrl-0 = <&display_mux_pins>;
Dave Gerlach1ff3859e2014-03-21 10:50:13 +0530831 status = "okay";
832 ti,no-reset-on-init;
Peter Ujfalusi593113e2015-07-02 17:06:24 +0300833
834 p8 {
835 /*
836 * SelLCDorHDMI selects between display and audio paths:
837 * Low: HDMI display with audio via HDMI
838 * High: LCD display with analog audio via aic3111 codec
839 */
840 gpio-hog;
841 gpios = <8 GPIO_ACTIVE_HIGH>;
842 output-high;
843 line-name = "SelLCDorHDMI";
844 };
Dave Gerlach1ff3859e2014-03-21 10:50:13 +0530845};
846
Balaji T K506be3f2014-03-03 20:20:18 +0530847&mmc1 {
848 status = "okay";
Peter Ujfalusi390810a2015-07-02 17:06:25 +0300849 vmmc-supply = <&evm_v3_3d>;
Balaji T K506be3f2014-03-03 20:20:18 +0530850 bus-width = <4>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&mmc1_pins>;
Mugunthan V N0731cbd2015-10-12 14:37:11 +0530853 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Balaji T K506be3f2014-03-03 20:20:18 +0530854};
George Cherianb5820d32014-03-19 15:40:02 +0530855
Roger Quadroseb157c82015-08-04 18:35:00 +0300856/* eMMC sits on mmc2 */
857&mmc2 {
858 /*
859 * When enabling eMMC, disable GPMC/NAND and set
860 * SelEMMCorNAND to output-high
861 */
862 status = "disabled";
863 vmmc-supply = <&evm_v3_3d>;
864 bus-width = <8>;
865 pinctrl-names = "default", "sleep";
866 pinctrl-0 = <&emmc_pins_default>;
867 pinctrl-1 = <&emmc_pins_sleep>;
868 ti,non-removable;
869};
870
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300871&mmc3 {
872 status = "okay";
873 /* these are on the crossbar and are outlined in the
874 xbar-event-map element */
Peter Ujfalusicce1ee02015-12-17 15:33:37 +0200875 dmas = <&edma_xbar 30 0 1>,
876 <&edma_xbar 31 0 2>;
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300877 dma-names = "tx", "rx";
878 vmmc-supply = <&vmmcwl_fixed>;
879 bus-width = <4>;
880 pinctrl-names = "default", "sleep";
881 pinctrl-0 = <&mmc3_pins_default>;
882 pinctrl-1 = <&mmc3_pins_sleep>;
883 cap-power-off-card;
884 keep-power-in-suspend;
885 ti,non-removable;
886
887 #address-cells = <1>;
888 #size-cells = <0>;
889 wlcore: wlcore@0 {
890 compatible = "ti,wl1835";
891 reg = <2>;
892 interrupt-parent = <&gpio1>;
Tony Lindgren572cf7d2018-07-02 23:57:20 -0700893 interrupts = <23 IRQ_TYPE_EDGE_RISING>;
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300894 };
895};
896
Eyal Reizerb6bbf592015-05-04 15:24:24 +0300897&uart3 {
898 status = "okay";
899 pinctrl-names = "default";
900 pinctrl-0 = <&uart3_pins>;
901};
902
George Cherianb5820d32014-03-19 15:40:02 +0530903&usb2_phy1 {
904 status = "okay";
905};
906
907&usb1 {
Roger Quadros54cab612018-03-16 13:11:43 +0200908 dr_mode = "otg";
George Cherianb5820d32014-03-19 15:40:02 +0530909 status = "okay";
910};
911
912&usb2_phy2 {
913 status = "okay";
914};
915
916&usb2 {
917 dr_mode = "host";
918 status = "okay";
919};
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530920
921&mac {
922 slaves = <1>;
923 pinctrl-names = "default", "sleep";
924 pinctrl-0 = <&cpsw_default>;
925 pinctrl-1 = <&cpsw_sleep>;
926 status = "okay";
927};
928
929&davinci_mdio {
930 pinctrl-names = "default", "sleep";
931 pinctrl-0 = <&davinci_mdio_default>;
932 pinctrl-1 = <&davinci_mdio_sleep>;
933 status = "okay";
Grygorii Strashkocfd91db2018-09-10 17:57:44 -0500934
935 ethphy0: ethernet-phy@0 {
936 reg = <0>;
937 };
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530938};
939
940&cpsw_emac0 {
Grygorii Strashkocfd91db2018-09-10 17:57:44 -0500941 phy-handle = <&ethphy0>;
Mugunthan V N7b25bab2014-05-13 14:14:31 +0530942 phy-mode = "rgmii";
943};
Pekon Gupta99ffa642014-05-19 14:45:46 +0530944
945&elm {
946 status = "okay";
947};
948
949&gpmc {
Roger Quadroseb157c82015-08-04 18:35:00 +0300950 /*
951 * When enabling GPMC, disable eMMC and set
952 * SelEMMCorNAND to output-low
953 */
Pekon Gupta99ffa642014-05-19 14:45:46 +0530954 status = "okay";
955 pinctrl-names = "default";
956 pinctrl-0 = <&nand_flash_x8>;
Roger Quadrosbe3f39c2016-02-23 18:37:19 +0200957 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
Pekon Gupta99ffa642014-05-19 14:45:46 +0530958 nand@0,0 {
Roger Quadrosbe3f39c2016-02-23 18:37:19 +0200959 compatible = "ti,omap2-nand";
Pekon Gupta99ffa642014-05-19 14:45:46 +0530960 reg = <0 0 4>; /* device IO registers */
Roger Quadrosbe3f39c2016-02-23 18:37:19 +0200961 interrupt-parent = <&gpmc>;
962 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
963 <1 IRQ_TYPE_NONE>; /* termcount */
Roger Quadros99a41012016-04-07 13:25:38 +0300964 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
Franklin S Cooper Jr78b02c32017-07-25 21:15:51 -0500965 ti,nand-xfer-type = "prefetch-dma";
Roger Quadros6b869112014-09-02 16:57:03 +0300966 ti,nand-ecc-opt = "bch16";
Pekon Gupta99ffa642014-05-19 14:45:46 +0530967 ti,elm-id = <&elm>;
968 nand-bus-width = <8>;
969 gpmc,device-width = <1>;
970 gpmc,sync-clk-ps = <0>;
971 gpmc,cs-on-ns = <0>;
972 gpmc,cs-rd-off-ns = <40>;
973 gpmc,cs-wr-off-ns = <40>;
974 gpmc,adv-on-ns = <0>;
975 gpmc,adv-rd-off-ns = <25>;
976 gpmc,adv-wr-off-ns = <25>;
977 gpmc,we-on-ns = <0>;
978 gpmc,we-off-ns = <20>;
979 gpmc,oe-on-ns = <3>;
980 gpmc,oe-off-ns = <30>;
981 gpmc,access-ns = <30>;
982 gpmc,rd-cycle-ns = <40>;
983 gpmc,wr-cycle-ns = <40>;
Pekon Gupta99ffa642014-05-19 14:45:46 +0530984 gpmc,bus-turnaround-ns = <0>;
985 gpmc,cycle2cycle-delay-ns = <0>;
986 gpmc,clk-activation-ns = <0>;
Pekon Gupta99ffa642014-05-19 14:45:46 +0530987 gpmc,wr-access-ns = <40>;
988 gpmc,wr-data-mux-bus-ns = <0>;
989 /* MTD partition table */
990 /* All SPL-* partitions are sized to minimal length
991 * which can be independently programmable. For
992 * NAND flash this is equal to size of erase-block */
993 #address-cells = <1>;
994 #size-cells = <1>;
995 partition@0 {
996 label = "NAND.SPL";
997 reg = <0x00000000 0x00040000>;
998 };
999 partition@1 {
1000 label = "NAND.SPL.backup1";
1001 reg = <0x00040000 0x00040000>;
1002 };
1003 partition@2 {
1004 label = "NAND.SPL.backup2";
1005 reg = <0x00080000 0x00040000>;
1006 };
1007 partition@3 {
1008 label = "NAND.SPL.backup3";
1009 reg = <0x000c0000 0x00040000>;
1010 };
1011 partition@4 {
1012 label = "NAND.u-boot-spl-os";
1013 reg = <0x00100000 0x00080000>;
1014 };
1015 partition@5 {
1016 label = "NAND.u-boot";
1017 reg = <0x00180000 0x00100000>;
1018 };
1019 partition@6 {
1020 label = "NAND.u-boot-env";
1021 reg = <0x00280000 0x00040000>;
1022 };
1023 partition@7 {
1024 label = "NAND.u-boot-env.backup1";
1025 reg = <0x002c0000 0x00040000>;
1026 };
1027 partition@8 {
1028 label = "NAND.kernel";
1029 reg = <0x00300000 0x00700000>;
1030 };
1031 partition@9 {
1032 label = "NAND.file-system";
1033 reg = <0x00a00000 0x1f600000>;
1034 };
1035 };
1036};
Sathya Prakash M R0bacb522014-03-24 16:31:56 +05301037
1038&dss {
1039 status = "ok";
1040
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&dss_pins>;
1043
1044 port {
Javier Martinez Canillas7d304f72016-06-27 15:21:04 -04001045 dpi_out: endpoint {
Sathya Prakash M R0bacb522014-03-24 16:31:56 +05301046 remote-endpoint = <&lcd_in>;
1047 data-lines = <24>;
1048 };
1049 };
1050};
Mugunthan V N4b1ce232014-07-18 11:29:11 +05301051
1052&dcan0 {
Roger Quadrosf95b1062015-08-18 17:01:57 +03001053 pinctrl-names = "default", "sleep";
Mugunthan V N4b1ce232014-07-18 11:29:11 +05301054 pinctrl-0 = <&dcan0_default>;
Roger Quadrosf95b1062015-08-18 17:01:57 +03001055 pinctrl-1 = <&dcan0_sleep>;
Mugunthan V N4b1ce232014-07-18 11:29:11 +05301056 status = "okay";
1057};
1058
1059&dcan1 {
Roger Quadrosf95b1062015-08-18 17:01:57 +03001060 pinctrl-names = "default", "sleep";
Mugunthan V N4b1ce232014-07-18 11:29:11 +05301061 pinctrl-0 = <&dcan1_default>;
Roger Quadrosf95b1062015-08-18 17:01:57 +03001062 pinctrl-1 = <&dcan1_sleep>;
Mugunthan V N4b1ce232014-07-18 11:29:11 +05301063 status = "okay";
1064};
Benoit Parrotc788a7f2014-12-18 21:54:14 +05301065
1066&vpfe0 {
1067 status = "okay";
1068 pinctrl-names = "default", "sleep";
1069 pinctrl-0 = <&vpfe0_pins_default>;
1070 pinctrl-1 = <&vpfe0_pins_sleep>;
1071
1072 port {
1073 vpfe0_ep: endpoint {
Lad, Prabhakar3aa59202015-03-12 23:38:21 +00001074 remote-endpoint = <&ov2659_1>;
Benoit Parrotc788a7f2014-12-18 21:54:14 +05301075 ti,am437x-vpfe-interface = <0>;
1076 bus-width = <8>;
1077 hsync-active = <0>;
1078 vsync-active = <0>;
1079 };
1080 };
1081};
1082
1083&vpfe1 {
1084 status = "okay";
1085 pinctrl-names = "default", "sleep";
1086 pinctrl-0 = <&vpfe1_pins_default>;
1087 pinctrl-1 = <&vpfe1_pins_sleep>;
1088
1089 port {
1090 vpfe1_ep: endpoint {
Lad, Prabhakar3aa59202015-03-12 23:38:21 +00001091 remote-endpoint = <&ov2659_0>;
Benoit Parrotc788a7f2014-12-18 21:54:14 +05301092 ti,am437x-vpfe-interface = <0>;
1093 bus-width = <8>;
1094 hsync-active = <0>;
1095 vsync-active = <0>;
1096 };
1097 };
1098};
Peter Ujfalusid3d92af2015-07-02 17:06:27 +03001099
1100&mcasp1 {
Peter Ujfalusicf9a4852015-07-02 17:06:28 +03001101 #sound-dai-cells = <0>;
Peter Ujfalusid3d92af2015-07-02 17:06:27 +03001102 pinctrl-names = "default", "sleep";
1103 pinctrl-0 = <&mcasp1_pins>;
1104 pinctrl-1 = <&mcasp1_sleep_pins>;
1105
1106 status = "okay";
1107
1108 op-mode = <0>; /* MCASP_IIS_MODE */
1109 tdm-slots = <2>;
1110 /* 4 serializers */
1111 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1112 0 0 1 2
1113 >;
1114 tx-num-evt = <32>;
1115 rx-num-evt = <32>;
1116};
Keerthyfff51e72015-08-18 15:11:14 +05301117
1118&rtc {
1119 clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
1120 clock-names = "ext-clk", "int-clk";
1121 status = "okay";
1122};
Dave Gerlach2af84bd2016-05-18 18:36:30 -05001123
1124&cpu {
1125 cpu0-supply = <&dcdc2>;
1126};