Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Randy Dunlap | c94fb63 | 2017-10-16 11:04:33 -0700 | [diff] [blame] | 2 | menu "IRQ chip support" |
| 3 | |
Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 4 | config IRQCHIP |
| 5 | def_bool y |
| 6 | depends on OF_IRQ |
| 7 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 8 | config ARM_GIC |
| 9 | bool |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 10 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | 0c9e498 | 2017-08-18 09:39:16 +0100 | [diff] [blame] | 11 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 12 | |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 13 | config ARM_GIC_PM |
| 14 | bool |
| 15 | depends on PM |
| 16 | select ARM_GIC |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 17 | |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 18 | config ARM_GIC_MAX_NR |
| 19 | int |
Jiangfeng Xiao | 7026552 | 2019-06-14 20:57:09 +0800 | [diff] [blame] | 20 | depends on ARM_GIC |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 21 | default 2 if ARCH_REALVIEW |
| 22 | default 1 |
| 23 | |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 24 | config ARM_GIC_V2M |
| 25 | bool |
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 26 | depends on PCI |
| 27 | select ARM_GIC |
| 28 | select PCI_MSI |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 29 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 30 | config GIC_NON_BANKED |
| 31 | bool |
| 32 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 33 | config ARM_GIC_V3 |
| 34 | bool |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 35 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 36 | select PARTITION_PERCPU |
Marc Zyngier | 956ae91 | 2017-08-18 09:39:17 +0100 | [diff] [blame] | 37 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 38 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 39 | config ARM_GIC_V3_ITS |
| 40 | bool |
Marc Zyngier | 29f4113 | 2017-11-13 17:25:59 +0000 | [diff] [blame] | 41 | select GENERIC_MSI_IRQ_DOMAIN |
| 42 | default ARM_GIC_V3 |
| 43 | |
| 44 | config ARM_GIC_V3_ITS_PCI |
| 45 | bool |
| 46 | depends on ARM_GIC_V3_ITS |
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 47 | depends on PCI |
| 48 | depends on PCI_MSI |
Marc Zyngier | 29f4113 | 2017-11-13 17:25:59 +0000 | [diff] [blame] | 49 | default ARM_GIC_V3_ITS |
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 50 | |
Bogdan Purcareata | 7afe031 | 2018-02-05 08:07:43 -0600 | [diff] [blame] | 51 | config ARM_GIC_V3_ITS_FSL_MC |
| 52 | bool |
| 53 | depends on ARM_GIC_V3_ITS |
| 54 | depends on FSL_MC_BUS |
| 55 | default ARM_GIC_V3_ITS |
| 56 | |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 57 | config ARM_NVIC |
| 58 | bool |
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 59 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 60 | select GENERIC_IRQ_CHIP |
| 61 | |
| 62 | config ARM_VIC |
| 63 | bool |
| 64 | select IRQ_DOMAIN |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 65 | |
| 66 | config ARM_VIC_NR |
| 67 | int |
| 68 | default 4 if ARCH_S5PV210 |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 69 | default 2 |
| 70 | depends on ARM_VIC |
| 71 | help |
| 72 | The maximum number of VICs available in the system, for |
| 73 | power management. |
| 74 | |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 75 | config ARMADA_370_XP_IRQ |
| 76 | bool |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 77 | select GENERIC_IRQ_CHIP |
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 78 | select PCI_MSI if PCI |
Marc Zyngier | e31793a | 2017-08-18 09:39:19 +0100 | [diff] [blame] | 79 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 80 | |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 81 | config ALPINE_MSI |
| 82 | bool |
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 83 | depends on PCI |
| 84 | select PCI_MSI |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 85 | select GENERIC_IRQ_CHIP |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 86 | |
Talel Shenhar | 1eb77c3 | 2019-06-10 11:34:43 +0300 | [diff] [blame] | 87 | config AL_FIC |
| 88 | bool "Amazon's Annapurna Labs Fabric Interrupt Controller" |
| 89 | depends on OF || COMPILE_TEST |
| 90 | select GENERIC_IRQ_CHIP |
| 91 | select IRQ_DOMAIN |
| 92 | help |
| 93 | Support Amazon's Annapurna Labs Fabric Interrupt Controller. |
| 94 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 95 | config ATMEL_AIC_IRQ |
| 96 | bool |
| 97 | select GENERIC_IRQ_CHIP |
| 98 | select IRQ_DOMAIN |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 99 | select SPARSE_IRQ |
| 100 | |
| 101 | config ATMEL_AIC5_IRQ |
| 102 | bool |
| 103 | select GENERIC_IRQ_CHIP |
| 104 | select IRQ_DOMAIN |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 105 | select SPARSE_IRQ |
| 106 | |
Ralf Baechle | 0509cfd | 2015-07-08 14:46:08 +0200 | [diff] [blame] | 107 | config I8259 |
| 108 | bool |
| 109 | select IRQ_DOMAIN |
| 110 | |
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 111 | config BCM6345_L1_IRQ |
| 112 | bool |
| 113 | select GENERIC_IRQ_CHIP |
| 114 | select IRQ_DOMAIN |
Marc Zyngier | d0ed5e8 | 2017-08-18 09:39:20 +0100 | [diff] [blame] | 115 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 116 | |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 117 | config BCM7038_L1_IRQ |
| 118 | bool |
| 119 | select GENERIC_IRQ_CHIP |
| 120 | select IRQ_DOMAIN |
Marc Zyngier | b8d9884 | 2017-08-18 09:39:21 +0100 | [diff] [blame] | 121 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 122 | |
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 123 | config BCM7120_L2_IRQ |
| 124 | bool |
| 125 | select GENERIC_IRQ_CHIP |
| 126 | select IRQ_DOMAIN |
| 127 | |
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 128 | config BRCMSTB_L2_IRQ |
| 129 | bool |
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 130 | select GENERIC_IRQ_CHIP |
| 131 | select IRQ_DOMAIN |
| 132 | |
Bartosz Golaszewski | 0145bee | 2019-02-14 15:52:16 +0100 | [diff] [blame] | 133 | config DAVINCI_AINTC |
| 134 | bool |
| 135 | select GENERIC_IRQ_CHIP |
| 136 | select IRQ_DOMAIN |
| 137 | |
Bartosz Golaszewski | 0fc3d74 | 2019-02-14 15:52:30 +0100 | [diff] [blame] | 138 | config DAVINCI_CP_INTC |
| 139 | bool |
| 140 | select GENERIC_IRQ_CHIP |
| 141 | select IRQ_DOMAIN |
| 142 | |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 143 | config DW_APB_ICTL |
| 144 | bool |
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 145 | select GENERIC_IRQ_CHIP |
Zhen Lei | 54a3844 | 2020-09-24 15:17:51 +0800 | [diff] [blame] | 146 | select IRQ_DOMAIN_HIERARCHY |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 147 | |
Linus Walleij | 6ee532e | 2017-03-18 17:53:24 +0100 | [diff] [blame] | 148 | config FARADAY_FTINTC010 |
| 149 | bool |
| 150 | select IRQ_DOMAIN |
Linus Walleij | 6ee532e | 2017-03-18 17:53:24 +0100 | [diff] [blame] | 151 | select SPARSE_IRQ |
| 152 | |
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 153 | config HISILICON_IRQ_MBIGEN |
| 154 | bool |
| 155 | select ARM_GIC_V3 |
| 156 | select ARM_GIC_V3_ITS |
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 157 | |
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 158 | config IMGPDC_IRQ |
| 159 | bool |
| 160 | select GENERIC_IRQ_CHIP |
| 161 | select IRQ_DOMAIN |
| 162 | |
Linus Walleij | 5b978c1 | 2019-01-25 16:41:25 +0100 | [diff] [blame] | 163 | config IXP4XX_IRQ |
| 164 | bool |
| 165 | select IRQ_DOMAIN |
Linus Walleij | 5b978c1 | 2019-01-25 16:41:25 +0100 | [diff] [blame] | 166 | select SPARSE_IRQ |
| 167 | |
Richard Fitzgerald | da0abe1 | 2018-12-14 14:44:16 +0000 | [diff] [blame] | 168 | config MADERA_IRQ |
| 169 | tristate |
| 170 | |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 171 | config IRQ_MIPS_CPU |
| 172 | bool |
| 173 | select GENERIC_IRQ_CHIP |
Paul Burton | 3838a54 | 2017-03-30 12:06:11 -0700 | [diff] [blame] | 174 | select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 175 | select IRQ_DOMAIN |
Marc Zyngier | 18416e4 | 2017-08-18 09:39:24 +0100 | [diff] [blame] | 176 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 177 | |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 178 | config CLPS711X_IRQCHIP |
| 179 | bool |
| 180 | depends on ARCH_CLPS711X |
| 181 | select IRQ_DOMAIN |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 182 | select SPARSE_IRQ |
| 183 | default y |
| 184 | |
Stafford Horne | 9b54470 | 2017-10-30 21:38:35 +0900 | [diff] [blame] | 185 | config OMPIC |
| 186 | bool |
| 187 | |
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 188 | config OR1K_PIC |
| 189 | bool |
| 190 | select IRQ_DOMAIN |
| 191 | |
Felipe Balbi | 8598066 | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 192 | config OMAP_IRQCHIP |
| 193 | bool |
| 194 | select GENERIC_IRQ_CHIP |
| 195 | select IRQ_DOMAIN |
| 196 | |
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 197 | config ORION_IRQCHIP |
| 198 | bool |
| 199 | select IRQ_DOMAIN |
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 200 | |
Cristian Birsan | aaa8666 | 2016-01-13 18:15:35 -0700 | [diff] [blame] | 201 | config PIC32_EVIC |
| 202 | bool |
| 203 | select GENERIC_IRQ_CHIP |
| 204 | select IRQ_DOMAIN |
| 205 | |
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 206 | config JCORE_AIC |
Rich Felker | 3602ffd | 2016-10-19 17:53:52 +0000 | [diff] [blame] | 207 | bool "J-Core integrated AIC" if COMPILE_TEST |
| 208 | depends on OF |
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 209 | select IRQ_DOMAIN |
| 210 | help |
| 211 | Support for the J-Core integrated AIC. |
| 212 | |
Manivannan Sadhasivam | d852e62 | 2018-12-10 23:05:43 +0530 | [diff] [blame] | 213 | config RDA_INTC |
| 214 | bool |
| 215 | select IRQ_DOMAIN |
| 216 | |
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 217 | config RENESAS_INTC_IRQPIN |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 218 | bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST |
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 219 | select IRQ_DOMAIN |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 220 | help |
| 221 | Enable support for the Renesas Interrupt Controller for external |
| 222 | interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. |
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 223 | |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 224 | config RENESAS_IRQC |
Lad Prabhakar | 72d44c0c | 2020-09-11 11:04:39 +0100 | [diff] [blame] | 225 | bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST |
Magnus Damm | 99c221d | 2015-09-28 18:42:37 +0900 | [diff] [blame] | 226 | select GENERIC_IRQ_CHIP |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 227 | select IRQ_DOMAIN |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 228 | help |
| 229 | Enable support for the Renesas Interrupt Controller for external |
Lad Prabhakar | 72d44c0c | 2020-09-11 11:04:39 +0100 | [diff] [blame] | 230 | devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 231 | |
Geert Uytterhoeven | a644ccb | 2019-05-27 14:17:11 +0200 | [diff] [blame] | 232 | config RENESAS_RZA1_IRQC |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 233 | bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST |
Geert Uytterhoeven | a644ccb | 2019-05-27 14:17:11 +0200 | [diff] [blame] | 234 | select IRQ_DOMAIN_HIERARCHY |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 235 | help |
| 236 | Enable support for the Renesas RZ/A1 Interrupt Controller, to use up |
| 237 | to 8 external interrupts with configurable sense select. |
Geert Uytterhoeven | a644ccb | 2019-05-27 14:17:11 +0200 | [diff] [blame] | 238 | |
Michael Walle | 03ac990 | 2020-09-14 23:43:32 +0200 | [diff] [blame] | 239 | config SL28CPLD_INTC |
| 240 | bool "Kontron sl28cpld IRQ controller" |
| 241 | depends on MFD_SL28CPLD=y || COMPILE_TEST |
| 242 | select REGMAP_IRQ |
| 243 | help |
| 244 | Interrupt controller driver for the board management controller |
| 245 | found on the Kontron sl28 CPLD. |
| 246 | |
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 247 | config ST_IRQCHIP |
| 248 | bool |
| 249 | select REGMAP |
| 250 | select MFD_SYSCON |
| 251 | help |
| 252 | Enables SysCfg Controlled IRQs on STi based platforms. |
| 253 | |
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 254 | config TB10X_IRQC |
| 255 | bool |
| 256 | select IRQ_DOMAIN |
| 257 | select GENERIC_IRQ_CHIP |
| 258 | |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 259 | config TS4800_IRQ |
| 260 | tristate "TS-4800 IRQ controller" |
| 261 | select IRQ_DOMAIN |
Richard Weinberger | 0df337c | 2016-01-25 23:24:17 +0100 | [diff] [blame] | 262 | depends on HAS_IOMEM |
Jean Delvare | d2b383d | 2016-02-09 11:19:20 +0100 | [diff] [blame] | 263 | depends on SOC_IMX51 || COMPILE_TEST |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 264 | help |
| 265 | Support for the TS-4800 FPGA IRQ controller |
| 266 | |
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 267 | config VERSATILE_FPGA_IRQ |
| 268 | bool |
| 269 | select IRQ_DOMAIN |
| 270 | |
| 271 | config VERSATILE_FPGA_IRQ_NR |
| 272 | int |
| 273 | default 4 |
| 274 | depends on VERSATILE_FPGA_IRQ |
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 275 | |
| 276 | config XTENSA_MX |
| 277 | bool |
| 278 | select IRQ_DOMAIN |
Marc Zyngier | 5009121 | 2017-08-18 09:39:25 +0100 | [diff] [blame] | 279 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 280 | |
Zubair Lutfullah Kakakhel | 0547dc7 | 2016-11-14 12:13:45 +0000 | [diff] [blame] | 281 | config XILINX_INTC |
Robert Hancock | debf69c | 2021-04-23 12:58:53 -0600 | [diff] [blame] | 282 | bool "Xilinx Interrupt Controller IP" |
| 283 | depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP |
Zubair Lutfullah Kakakhel | 0547dc7 | 2016-11-14 12:13:45 +0000 | [diff] [blame] | 284 | select IRQ_DOMAIN |
Robert Hancock | debf69c | 2021-04-23 12:58:53 -0600 | [diff] [blame] | 285 | help |
| 286 | Support for the Xilinx Interrupt Controller IP core. |
| 287 | This is used as a primary controller with MicroBlaze and can also |
| 288 | be used as a secondary chained controller on other platforms. |
Zubair Lutfullah Kakakhel | 0547dc7 | 2016-11-14 12:13:45 +0000 | [diff] [blame] | 289 | |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 290 | config IRQ_CROSSBAR |
| 291 | bool |
| 292 | help |
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 293 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 294 | The primary irqchip invokes the crossbar's callback which inturn allocates |
| 295 | a free irq and configures the IP. Thus the peripheral interrupts are |
| 296 | routed to one of the free irqchip interrupt lines. |
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 297 | |
| 298 | config KEYSTONE_IRQ |
| 299 | tristate "Keystone 2 IRQ controller IP" |
| 300 | depends on ARCH_KEYSTONE |
| 301 | help |
| 302 | Support for Texas Instruments Keystone 2 IRQ controller IP which |
| 303 | is part of the Keystone 2 IPC mechanism |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 304 | |
| 305 | config MIPS_GIC |
| 306 | bool |
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 307 | select GENERIC_IRQ_IPI |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 308 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 309 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 310 | config INGENIC_IRQ |
| 311 | bool |
| 312 | depends on MACH_INGENIC |
| 313 | default y |
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 314 | |
Paul Cercueil | 9536eba | 2019-07-24 13:16:08 -0400 | [diff] [blame] | 315 | config INGENIC_TCU_IRQ |
| 316 | bool "Ingenic JZ47xx TCU interrupt controller" |
| 317 | default MACH_INGENIC |
| 318 | depends on MIPS || COMPILE_TEST |
| 319 | select MFD_SYSCON |
YueHaibing | 8084499 | 2019-08-13 09:56:02 +0800 | [diff] [blame] | 320 | select GENERIC_IRQ_CHIP |
Paul Cercueil | 9536eba | 2019-07-24 13:16:08 -0400 | [diff] [blame] | 321 | help |
| 322 | Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic |
| 323 | JZ47xx SoCs. |
| 324 | |
| 325 | If unsure, say N. |
| 326 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 327 | config RENESAS_H8300H_INTC |
| 328 | bool |
| 329 | select IRQ_DOMAIN |
| 330 | |
| 331 | config RENESAS_H8S_INTC |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 332 | bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST |
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 333 | select IRQ_DOMAIN |
Geert Uytterhoeven | 02d7e04 | 2019-06-07 11:50:36 +0200 | [diff] [blame] | 334 | help |
| 335 | Enable support for the Renesas H8/300 Interrupt Controller, as found |
| 336 | on Renesas H8S SoCs. |
Shenwei Wang | e324c4d | 2015-08-24 14:04:15 -0500 | [diff] [blame] | 337 | |
| 338 | config IMX_GPCV2 |
| 339 | bool |
| 340 | select IRQ_DOMAIN |
| 341 | help |
| 342 | Enables the wakeup IRQs for IMX platforms with GPCv2 block |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 343 | |
| 344 | config IRQ_MXS |
| 345 | def_bool y if MACH_ASM9260 || ARCH_MXS |
| 346 | select IRQ_DOMAIN |
| 347 | select STMP_DEVICE |
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 348 | |
Alexandre Belloni | 19d9916 | 2018-03-22 16:15:24 +0100 | [diff] [blame] | 349 | config MSCC_OCELOT_IRQ |
| 350 | bool |
| 351 | select IRQ_DOMAIN |
| 352 | select GENERIC_IRQ_CHIP |
| 353 | |
Thomas Petazzoni | a68a63c | 2017-06-21 15:29:14 +0200 | [diff] [blame] | 354 | config MVEBU_GICP |
| 355 | bool |
| 356 | |
Thomas Petazzoni | e0de91a | 2017-06-21 15:29:15 +0200 | [diff] [blame] | 357 | config MVEBU_ICU |
| 358 | bool |
| 359 | |
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 360 | config MVEBU_ODMI |
| 361 | bool |
Arnd Bergmann | fa23b9d | 2017-03-14 13:54:12 +0100 | [diff] [blame] | 362 | select GENERIC_MSI_IRQ_DOMAIN |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 363 | |
Thomas Petazzoni | a109893 | 2016-08-05 16:55:19 +0200 | [diff] [blame] | 364 | config MVEBU_PIC |
| 365 | bool |
| 366 | |
Miquel Raynal | 61ce8d8 | 2018-10-01 16:13:51 +0200 | [diff] [blame] | 367 | config MVEBU_SEI |
| 368 | bool |
| 369 | |
Rasmus Villemoes | 0dcd9f8 | 2019-11-07 13:21:15 +0100 | [diff] [blame] | 370 | config LS_EXTIRQ |
| 371 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE |
| 372 | select MFD_SYSCON |
| 373 | |
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 374 | config LS_SCFG_MSI |
| 375 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE |
| 376 | depends on PCI && PCI_MSI |
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 377 | |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 378 | config PARTITION_PERCPU |
| 379 | bool |
Linus Torvalds | 0efacbb | 2016-05-19 09:46:18 -0700 | [diff] [blame] | 380 | |
Alexandre TORGUE | e0720416 | 2016-09-20 18:00:57 +0200 | [diff] [blame] | 381 | config STM32_EXTI |
| 382 | bool |
| 383 | select IRQ_DOMAIN |
Ludovic Barre | 0e7d780 | 2017-11-06 18:03:31 +0100 | [diff] [blame] | 384 | select GENERIC_IRQ_CHIP |
Agustin Vega-Frias | f20cc9b | 2017-02-02 18:23:59 -0500 | [diff] [blame] | 385 | |
| 386 | config QCOM_IRQ_COMBINER |
| 387 | bool "QCOM IRQ combiner support" |
| 388 | depends on ARCH_QCOM && ACPI |
Agustin Vega-Frias | f20cc9b | 2017-02-02 18:23:59 -0500 | [diff] [blame] | 389 | select IRQ_DOMAIN_HIERARCHY |
| 390 | help |
| 391 | Say yes here to add support for the IRQ combiner devices embedded |
| 392 | in Qualcomm Technologies chips. |
Masahiro Yamada | 5ed34d3a | 2017-08-23 10:31:47 +0900 | [diff] [blame] | 393 | |
| 394 | config IRQ_UNIPHIER_AIDET |
| 395 | bool "UniPhier AIDET support" if COMPILE_TEST |
| 396 | depends on ARCH_UNIPHIER || COMPILE_TEST |
| 397 | default ARCH_UNIPHIER |
| 398 | select IRQ_DOMAIN_HIERARCHY |
| 399 | help |
| 400 | Support for the UniPhier AIDET (ARM Interrupt Detector). |
Randy Dunlap | c94fb63 | 2017-10-16 11:04:33 -0700 | [diff] [blame] | 401 | |
Jerome Brunet | 215f4cc | 2017-09-18 15:46:10 +0200 | [diff] [blame] | 402 | config MESON_IRQ_GPIO |
| 403 | bool "Meson GPIO Interrupt Multiplexer" |
Thomas Gleixner | d9ee91c | 2017-10-20 11:15:36 +0200 | [diff] [blame] | 404 | depends on ARCH_MESON |
Jerome Brunet | 215f4cc | 2017-09-18 15:46:10 +0200 | [diff] [blame] | 405 | select IRQ_DOMAIN_HIERARCHY |
| 406 | help |
| 407 | Support Meson SoC Family GPIO Interrupt Multiplexer |
| 408 | |
Miodrag Dinic | 4235ff5 | 2017-12-29 16:41:46 +0100 | [diff] [blame] | 409 | config GOLDFISH_PIC |
| 410 | bool "Goldfish programmable interrupt controller" |
| 411 | depends on MIPS && (GOLDFISH || COMPILE_TEST) |
| 412 | select IRQ_DOMAIN |
| 413 | help |
| 414 | Say yes here to enable Goldfish interrupt controller driver used |
| 415 | for Goldfish based virtual platforms. |
| 416 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 417 | config QCOM_PDC |
Saravana Kannan | 4acd8a4 | 2021-05-18 21:19:21 +0000 | [diff] [blame] | 418 | tristate "QCOM PDC" |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 419 | depends on ARCH_QCOM |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 420 | select IRQ_DOMAIN_HIERARCHY |
| 421 | help |
| 422 | Power Domain Controller driver to manage and configure wakeup |
| 423 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. |
| 424 | |
Guo Ren | d8a5f5f | 2018-09-16 15:57:14 +0800 | [diff] [blame] | 425 | config CSKY_MPINTC |
Guo Ren | be1abc5 | 2021-02-04 15:46:08 +0800 | [diff] [blame] | 426 | bool |
Guo Ren | d8a5f5f | 2018-09-16 15:57:14 +0800 | [diff] [blame] | 427 | depends on CSKY |
| 428 | help |
| 429 | Say yes here to enable C-SKY SMP interrupt controller driver used |
| 430 | for C-SKY SMP system. |
Randy Dunlap | 656b42d | 2020-01-28 18:25:14 -0800 | [diff] [blame] | 431 | In fact it's not mmio map in hardware and it uses ld/st to visit the |
Guo Ren | d8a5f5f | 2018-09-16 15:57:14 +0800 | [diff] [blame] | 432 | controller's register inside CPU. |
| 433 | |
Guo Ren | edff1b4 | 2018-09-16 15:57:14 +0800 | [diff] [blame] | 434 | config CSKY_APB_INTC |
| 435 | bool "C-SKY APB Interrupt Controller" |
| 436 | depends on CSKY |
| 437 | help |
| 438 | Say yes here to enable C-SKY APB interrupt controller driver used |
Randy Dunlap | 656b42d | 2020-01-28 18:25:14 -0800 | [diff] [blame] | 439 | by C-SKY single core SOC system. It uses mmio map apb-bus to visit |
Guo Ren | edff1b4 | 2018-09-16 15:57:14 +0800 | [diff] [blame] | 440 | the controller's register. |
| 441 | |
Lucas Stach | 0136afa | 2018-12-17 15:01:20 +0100 | [diff] [blame] | 442 | config IMX_IRQSTEER |
| 443 | bool "i.MX IRQSTEER support" |
| 444 | depends on ARCH_MXC || COMPILE_TEST |
| 445 | default ARCH_MXC |
| 446 | select IRQ_DOMAIN |
| 447 | help |
| 448 | Support for the i.MX IRQSTEER interrupt multiplexer/remapper. |
| 449 | |
Joakim Zhang | 2fbb139 | 2020-01-17 06:10:10 +0000 | [diff] [blame] | 450 | config IMX_INTMUX |
Geert Uytterhoeven | a890cae | 2021-02-08 15:56:05 +0100 | [diff] [blame] | 451 | bool "i.MX INTMUX support" if COMPILE_TEST |
| 452 | default y if ARCH_MXC |
Joakim Zhang | 2fbb139 | 2020-01-17 06:10:10 +0000 | [diff] [blame] | 453 | select IRQ_DOMAIN |
| 454 | help |
| 455 | Support for the i.MX INTMUX interrupt multiplexer. |
| 456 | |
Jiaxun Yang | 9e543e2 | 2019-02-01 14:22:35 +0800 | [diff] [blame] | 457 | config LS1X_IRQ |
| 458 | bool "Loongson-1 Interrupt Controller" |
| 459 | depends on MACH_LOONGSON32 |
| 460 | default y |
| 461 | select IRQ_DOMAIN |
| 462 | select GENERIC_IRQ_CHIP |
| 463 | help |
| 464 | Support for the Loongson-1 platform Interrupt Controller. |
| 465 | |
Lokesh Vutla | cd844b0 | 2019-04-30 15:42:25 +0530 | [diff] [blame] | 466 | config TI_SCI_INTR_IRQCHIP |
| 467 | bool |
| 468 | depends on TI_SCI_PROTOCOL |
| 469 | select IRQ_DOMAIN_HIERARCHY |
| 470 | help |
| 471 | This enables the irqchip driver support for K3 Interrupt router |
| 472 | over TI System Control Interface available on some new TI's SoCs. |
| 473 | If you wish to use interrupt router irq resources managed by the |
| 474 | TI System Controller, say Y here. Otherwise, say N. |
| 475 | |
Lokesh Vutla | 9f1463b | 2019-04-30 15:42:27 +0530 | [diff] [blame] | 476 | config TI_SCI_INTA_IRQCHIP |
| 477 | bool |
| 478 | depends on TI_SCI_PROTOCOL |
| 479 | select IRQ_DOMAIN_HIERARCHY |
Lokesh Vutla | f011df6 | 2019-04-30 15:42:29 +0530 | [diff] [blame] | 480 | select TI_SCI_INTA_MSI_DOMAIN |
Lokesh Vutla | 9f1463b | 2019-04-30 15:42:27 +0530 | [diff] [blame] | 481 | help |
| 482 | This enables the irqchip driver support for K3 Interrupt aggregator |
| 483 | over TI System Control Interface available on some new TI's SoCs. |
| 484 | If you wish to use interrupt aggregator irq resources managed by the |
| 485 | TI System Controller, say Y here. Otherwise, say N. |
| 486 | |
Grzegorz Jaszczyk | 04e2d1e | 2020-09-16 18:36:03 +0200 | [diff] [blame] | 487 | config TI_PRUSS_INTC |
Suman Anna | b8e594f | 2021-01-08 10:29:01 -0600 | [diff] [blame] | 488 | tristate |
| 489 | depends on TI_PRUSS |
| 490 | default TI_PRUSS |
Grzegorz Jaszczyk | 04e2d1e | 2020-09-16 18:36:03 +0200 | [diff] [blame] | 491 | select IRQ_DOMAIN |
| 492 | help |
| 493 | This enables support for the PRU-ICSS Local Interrupt Controller |
| 494 | present within a PRU-ICSS subsystem present on various TI SoCs. |
| 495 | The PRUSS INTC enables various interrupts to be routed to multiple |
| 496 | different processors within the SoC. |
| 497 | |
Anup Patel | 6b7ce892 | 2020-06-01 14:45:40 +0530 | [diff] [blame] | 498 | config RISCV_INTC |
| 499 | bool "RISC-V Local Interrupt Controller" |
| 500 | depends on RISCV |
| 501 | default y |
| 502 | help |
| 503 | This enables support for the per-HART local interrupt controller |
| 504 | found in standard RISC-V systems. The per-HART local interrupt |
| 505 | controller handles timer interrupts, software interrupts, and |
| 506 | hardware interrupts. Without a per-HART local interrupt controller, |
| 507 | a RISC-V system will be unable to handle any interrupts. |
| 508 | |
| 509 | If you don't know what to do here, say Y. |
| 510 | |
Christoph Hellwig | 8237f8b | 2018-07-26 16:27:00 +0200 | [diff] [blame] | 511 | config SIFIVE_PLIC |
| 512 | bool "SiFive Platform-Level Interrupt Controller" |
| 513 | depends on RISCV |
Yash Shah | 466008f | 2019-12-10 16:41:11 +0530 | [diff] [blame] | 514 | select IRQ_DOMAIN_HIERARCHY |
Christoph Hellwig | 8237f8b | 2018-07-26 16:27:00 +0200 | [diff] [blame] | 515 | help |
| 516 | This enables support for the PLIC chip found in SiFive (and |
| 517 | potentially other) RISC-V systems. The PLIC controls devices |
| 518 | interrupts and connects them to each core's local interrupt |
| 519 | controller. Aside from timer and software interrupts, all other |
| 520 | interrupt sources are subordinate to the PLIC. |
| 521 | |
| 522 | If you don't know what to do here, say Y. |
Jonathan Neuschäfer | 0149385 | 2019-10-02 16:44:52 +0200 | [diff] [blame] | 523 | |
Hyunki Koo | b74416d | 2019-12-25 06:11:07 +0900 | [diff] [blame] | 524 | config EXYNOS_IRQ_COMBINER |
| 525 | bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST |
| 526 | depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST |
| 527 | help |
| 528 | Say yes here to add support for the IRQ combiner devices embedded |
| 529 | in Samsung Exynos chips. |
| 530 | |
Jiaxun Yang | dbb1522 | 2020-03-25 11:54:54 +0800 | [diff] [blame] | 531 | config LOONGSON_LIOINTC |
| 532 | bool "Loongson Local I/O Interrupt Controller" |
| 533 | depends on MACH_LOONGSON64 |
| 534 | default y |
| 535 | select IRQ_DOMAIN |
| 536 | select GENERIC_IRQ_CHIP |
| 537 | help |
| 538 | Support for the Loongson Local I/O Interrupt Controller. |
| 539 | |
Jiaxun Yang | a93f1d9 | 2020-03-25 11:54:57 +0800 | [diff] [blame] | 540 | config LOONGSON_HTPIC |
| 541 | bool "Loongson3 HyperTransport PIC Controller" |
| 542 | depends on MACH_LOONGSON64 |
| 543 | default y |
| 544 | select IRQ_DOMAIN |
| 545 | select GENERIC_IRQ_CHIP |
Jiaxun Yang | a93f1d9 | 2020-03-25 11:54:57 +0800 | [diff] [blame] | 546 | help |
| 547 | Support for the Loongson-3 HyperTransport PIC Controller. |
| 548 | |
Jiaxun Yang | 818e915 | 2020-05-28 23:27:49 +0800 | [diff] [blame] | 549 | config LOONGSON_HTVEC |
| 550 | bool "Loongson3 HyperTransport Interrupt Vector Controller" |
Ingo Molnar | d77aeb5 | 2020-06-01 09:45:27 +0200 | [diff] [blame] | 551 | depends on MACH_LOONGSON64 |
Jiaxun Yang | 818e915 | 2020-05-28 23:27:49 +0800 | [diff] [blame] | 552 | default MACH_LOONGSON64 |
| 553 | select IRQ_DOMAIN_HIERARCHY |
| 554 | help |
| 555 | Support for the Loongson3 HyperTransport Interrupt Vector Controller. |
| 556 | |
Jiaxun Yang | ef8c01e | 2020-05-28 23:27:51 +0800 | [diff] [blame] | 557 | config LOONGSON_PCH_PIC |
| 558 | bool "Loongson PCH PIC Controller" |
| 559 | depends on MACH_LOONGSON64 || COMPILE_TEST |
| 560 | default MACH_LOONGSON64 |
| 561 | select IRQ_DOMAIN_HIERARCHY |
| 562 | select IRQ_FASTEOI_HIERARCHY_HANDLERS |
| 563 | help |
| 564 | Support for the Loongson PCH PIC Controller. |
| 565 | |
Jiaxun Yang | 632dcc2 | 2020-05-28 23:27:53 +0800 | [diff] [blame] | 566 | config LOONGSON_PCH_MSI |
Jiaxun Yang | a23df9a | 2020-05-30 20:11:12 +0800 | [diff] [blame] | 567 | bool "Loongson PCH MSI Controller" |
Jiaxun Yang | 632dcc2 | 2020-05-28 23:27:53 +0800 | [diff] [blame] | 568 | depends on MACH_LOONGSON64 || COMPILE_TEST |
| 569 | depends on PCI |
| 570 | default MACH_LOONGSON64 |
| 571 | select IRQ_DOMAIN_HIERARCHY |
| 572 | select PCI_MSI |
| 573 | help |
| 574 | Support for the Loongson PCH MSI Controller. |
| 575 | |
Mark-PK Tsai | ad4c938 | 2020-09-02 14:33:43 +0800 | [diff] [blame] | 576 | config MST_IRQ |
| 577 | bool "MStar Interrupt Controller" |
Geert Uytterhoeven | 61b0648 | 2020-10-14 15:17:03 +0200 | [diff] [blame] | 578 | depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST |
Mark-PK Tsai | ad4c938 | 2020-09-02 14:33:43 +0800 | [diff] [blame] | 579 | default ARCH_MEDIATEK |
| 580 | select IRQ_DOMAIN |
| 581 | select IRQ_DOMAIN_HIERARCHY |
| 582 | help |
| 583 | Support MStar Interrupt Controller. |
| 584 | |
Jonathan Neuschäfer | fead4dd | 2021-04-06 14:09:17 +0200 | [diff] [blame] | 585 | config WPCM450_AIC |
| 586 | bool "Nuvoton WPCM450 Advanced Interrupt Controller" |
Marc Zyngier | 94bc942 | 2021-04-08 08:56:27 +0100 | [diff] [blame] | 587 | depends on ARCH_WPCM450 |
Jonathan Neuschäfer | fead4dd | 2021-04-06 14:09:17 +0200 | [diff] [blame] | 588 | help |
| 589 | Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. |
| 590 | |
Thomas Bogendoerfer | 529ea36 | 2021-04-22 16:53:28 +0200 | [diff] [blame] | 591 | config IRQ_IDT3243X |
| 592 | bool |
| 593 | select GENERIC_IRQ_CHIP |
| 594 | select IRQ_DOMAIN |
| 595 | |
Hector Martin | 76cde26 | 2021-01-21 08:55:15 +0900 | [diff] [blame] | 596 | config APPLE_AIC |
| 597 | bool "Apple Interrupt Controller (AIC)" |
| 598 | depends on ARM64 |
Geert Uytterhoeven | 5b44955 | 2021-04-13 14:21:58 +0200 | [diff] [blame] | 599 | depends on ARCH_APPLE || COMPILE_TEST |
Hector Martin | 76cde26 | 2021-01-21 08:55:15 +0900 | [diff] [blame] | 600 | help |
| 601 | Support for the Apple Interrupt Controller found on Apple Silicon SoCs, |
| 602 | such as the M1. |
| 603 | |
Jonathan Neuschäfer | 0149385 | 2019-10-02 16:44:52 +0200 | [diff] [blame] | 604 | endmenu |