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Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Randy Dunlapc94fb632017-10-16 11:04:33 -07002menu "IRQ chip support"
3
Thomas Petazzonif6e916b2012-11-20 23:00:52 +01004config IRQCHIP
5 def_bool y
6 depends on OF_IRQ
7
Rob Herring81243e42012-11-20 21:21:40 -06008config ARM_GIC
9 bool
Yingjoe Chen9a1091e2014-11-25 16:04:19 +080010 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier0c9e4982017-08-18 09:39:16 +010011 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Rob Herring81243e42012-11-20 21:21:40 -060012
Jon Hunter9c8eddd2016-06-07 16:12:34 +010013config ARM_GIC_PM
14 bool
15 depends on PM
16 select ARM_GIC
Jon Hunter9c8eddd2016-06-07 16:12:34 +010017
Linus Walleija27d21e2015-12-18 10:44:53 +010018config ARM_GIC_MAX_NR
19 int
Jiangfeng Xiao70265522019-06-14 20:57:09 +080020 depends on ARM_GIC
Linus Walleija27d21e2015-12-18 10:44:53 +010021 default 2 if ARCH_REALVIEW
22 default 1
23
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000024config ARM_GIC_V2M
25 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050026 depends on PCI
27 select ARM_GIC
28 select PCI_MSI
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000029
Rob Herring81243e42012-11-20 21:21:40 -060030config GIC_NON_BANKED
31 bool
32
Marc Zyngier021f6532014-06-30 16:01:31 +010033config ARM_GIC_V3
34 bool
Marc Zyngier443acc42014-11-24 14:35:09 +000035 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +010036 select PARTITION_PERCPU
Marc Zyngier956ae912017-08-18 09:39:17 +010037 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Marc Zyngier021f6532014-06-30 16:01:31 +010038
Marc Zyngier19812722014-11-24 14:35:19 +000039config ARM_GIC_V3_ITS
40 bool
Marc Zyngier29f41132017-11-13 17:25:59 +000041 select GENERIC_MSI_IRQ_DOMAIN
42 default ARM_GIC_V3
43
44config ARM_GIC_V3_ITS_PCI
45 bool
46 depends on ARM_GIC_V3_ITS
Arnd Bergmann3ee803642016-06-15 15:47:33 -050047 depends on PCI
48 depends on PCI_MSI
Marc Zyngier29f41132017-11-13 17:25:59 +000049 default ARM_GIC_V3_ITS
Uwe Kleine-König292ec082013-06-26 09:18:48 +020050
Bogdan Purcareata7afe0312018-02-05 08:07:43 -060051config ARM_GIC_V3_ITS_FSL_MC
52 bool
53 depends on ARM_GIC_V3_ITS
54 depends on FSL_MC_BUS
55 default ARM_GIC_V3_ITS
56
Rob Herring44430ec2012-10-27 17:25:26 -050057config ARM_NVIC
58 bool
Stefan Agner2d9f59f2015-05-16 11:44:16 +020059 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050060 select GENERIC_IRQ_CHIP
61
62config ARM_VIC
63 bool
64 select IRQ_DOMAIN
Rob Herring44430ec2012-10-27 17:25:26 -050065
66config ARM_VIC_NR
67 int
68 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050069 default 2
70 depends on ARM_VIC
71 help
72 The maximum number of VICs available in the system, for
73 power management.
74
Thomas Petazzonifed6d332016-02-10 15:46:56 +010075config ARMADA_370_XP_IRQ
76 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010077 select GENERIC_IRQ_CHIP
Arnd Bergmann3ee803642016-06-15 15:47:33 -050078 select PCI_MSI if PCI
Marc Zyngiere31793a2017-08-18 09:39:19 +010079 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Thomas Petazzonifed6d332016-02-10 15:46:56 +010080
Antoine Tenarte6b78f22016-02-19 16:22:44 +010081config ALPINE_MSI
82 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050083 depends on PCI
84 select PCI_MSI
Antoine Tenarte6b78f22016-02-19 16:22:44 +010085 select GENERIC_IRQ_CHIP
Antoine Tenarte6b78f22016-02-19 16:22:44 +010086
Talel Shenhar1eb77c32019-06-10 11:34:43 +030087config AL_FIC
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
91 select IRQ_DOMAIN
92 help
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
94
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020095config ATMEL_AIC_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020099 select SPARSE_IRQ
100
101config ATMEL_AIC5_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200105 select SPARSE_IRQ
106
Ralf Baechle0509cfd2015-07-08 14:46:08 +0200107config I8259
108 bool
109 select IRQ_DOMAIN
110
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000111config BCM6345_L1_IRQ
112 bool
113 select GENERIC_IRQ_CHIP
114 select IRQ_DOMAIN
Marc Zyngierd0ed5e82017-08-18 09:39:20 +0100115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000116
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800117config BCM7038_L1_IRQ
118 bool
119 select GENERIC_IRQ_CHIP
120 select IRQ_DOMAIN
Marc Zyngierb8d98842017-08-18 09:39:21 +0100121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800122
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800123config BCM7120_L2_IRQ
124 bool
125 select GENERIC_IRQ_CHIP
126 select IRQ_DOMAIN
127
Florian Fainelli7f646e92014-05-23 17:40:53 -0700128config BRCMSTB_L2_IRQ
129 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
Bartosz Golaszewski0145bee2019-02-14 15:52:16 +0100133config DAVINCI_AINTC
134 bool
135 select GENERIC_IRQ_CHIP
136 select IRQ_DOMAIN
137
Bartosz Golaszewski0fc3d742019-02-14 15:52:30 +0100138config DAVINCI_CP_INTC
139 bool
140 select GENERIC_IRQ_CHIP
141 select IRQ_DOMAIN
142
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200143config DW_APB_ICTL
144 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800145 select GENERIC_IRQ_CHIP
Zhen Lei54a38442020-09-24 15:17:51 +0800146 select IRQ_DOMAIN_HIERARCHY
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200147
Linus Walleij6ee532e2017-03-18 17:53:24 +0100148config FARADAY_FTINTC010
149 bool
150 select IRQ_DOMAIN
Linus Walleij6ee532e2017-03-18 17:53:24 +0100151 select SPARSE_IRQ
152
MaJun9a7c4ab2016-03-23 17:06:33 +0800153config HISILICON_IRQ_MBIGEN
154 bool
155 select ARM_GIC_V3
156 select ARM_GIC_V3_ITS
MaJun9a7c4ab2016-03-23 17:06:33 +0800157
James Hoganb6ef9162013-04-22 15:43:50 +0100158config IMGPDC_IRQ
159 bool
160 select GENERIC_IRQ_CHIP
161 select IRQ_DOMAIN
162
Linus Walleij5b978c12019-01-25 16:41:25 +0100163config IXP4XX_IRQ
164 bool
165 select IRQ_DOMAIN
Linus Walleij5b978c12019-01-25 16:41:25 +0100166 select SPARSE_IRQ
167
Richard Fitzgeraldda0abe12018-12-14 14:44:16 +0000168config MADERA_IRQ
169 tristate
170
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200171config IRQ_MIPS_CPU
172 bool
173 select GENERIC_IRQ_CHIP
Paul Burton3838a542017-03-30 12:06:11 -0700174 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200175 select IRQ_DOMAIN
Marc Zyngier18416e42017-08-18 09:39:24 +0100176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200177
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400178config CLPS711X_IRQCHIP
179 bool
180 depends on ARCH_CLPS711X
181 select IRQ_DOMAIN
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400182 select SPARSE_IRQ
183 default y
184
Stafford Horne9b544702017-10-30 21:38:35 +0900185config OMPIC
186 bool
187
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300188config OR1K_PIC
189 bool
190 select IRQ_DOMAIN
191
Felipe Balbi85980662014-09-15 16:15:02 -0500192config OMAP_IRQCHIP
193 bool
194 select GENERIC_IRQ_CHIP
195 select IRQ_DOMAIN
196
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200197config ORION_IRQCHIP
198 bool
199 select IRQ_DOMAIN
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200200
Cristian Birsanaaa86662016-01-13 18:15:35 -0700201config PIC32_EVIC
202 bool
203 select GENERIC_IRQ_CHIP
204 select IRQ_DOMAIN
205
Rich Felker981b58f2016-08-04 04:30:37 +0000206config JCORE_AIC
Rich Felker3602ffd2016-10-19 17:53:52 +0000207 bool "J-Core integrated AIC" if COMPILE_TEST
208 depends on OF
Rich Felker981b58f2016-08-04 04:30:37 +0000209 select IRQ_DOMAIN
210 help
211 Support for the J-Core integrated AIC.
212
Manivannan Sadhasivamd852e622018-12-10 23:05:43 +0530213config RDA_INTC
214 bool
215 select IRQ_DOMAIN
216
Magnus Damm44358042013-02-18 23:28:34 +0900217config RENESAS_INTC_IRQPIN
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
Magnus Damm44358042013-02-18 23:28:34 +0900219 select IRQ_DOMAIN
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200220 help
221 Enable support for the Renesas Interrupt Controller for external
222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
Magnus Damm44358042013-02-18 23:28:34 +0900223
Magnus Dammfbc83b72013-02-27 17:15:01 +0900224config RENESAS_IRQC
Lad Prabhakar72d44c0c2020-09-11 11:04:39 +0100225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
Magnus Damm99c221d2015-09-28 18:42:37 +0900226 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900227 select IRQ_DOMAIN
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200228 help
229 Enable support for the Renesas Interrupt Controller for external
Lad Prabhakar72d44c0c2020-09-11 11:04:39 +0100230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
Magnus Dammfbc83b72013-02-27 17:15:01 +0900231
Geert Uytterhoevena644ccb2019-05-27 14:17:11 +0200232config RENESAS_RZA1_IRQC
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
Geert Uytterhoevena644ccb2019-05-27 14:17:11 +0200234 select IRQ_DOMAIN_HIERARCHY
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200235 help
236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
237 to 8 external interrupts with configurable sense select.
Geert Uytterhoevena644ccb2019-05-27 14:17:11 +0200238
Michael Walle03ac9902020-09-14 23:43:32 +0200239config SL28CPLD_INTC
240 bool "Kontron sl28cpld IRQ controller"
241 depends on MFD_SL28CPLD=y || COMPILE_TEST
242 select REGMAP_IRQ
243 help
244 Interrupt controller driver for the board management controller
245 found on the Kontron sl28 CPLD.
246
Lee Jones07088482015-02-18 15:13:58 +0000247config ST_IRQCHIP
248 bool
249 select REGMAP
250 select MFD_SYSCON
251 help
252 Enables SysCfg Controlled IRQs on STi based platforms.
253
Christian Ruppertb06eb012013-06-25 18:29:57 +0200254config TB10X_IRQC
255 bool
256 select IRQ_DOMAIN
257 select GENERIC_IRQ_CHIP
258
Damien Riegeld01f8632015-12-21 15:11:23 -0500259config TS4800_IRQ
260 tristate "TS-4800 IRQ controller"
261 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100262 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100263 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500264 help
265 Support for the TS-4800 FPGA IRQ controller
266
Linus Walleij2389d502012-10-31 22:04:31 +0100267config VERSATILE_FPGA_IRQ
268 bool
269 select IRQ_DOMAIN
270
271config VERSATILE_FPGA_IRQ_NR
272 int
273 default 4
274 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400275
276config XTENSA_MX
277 bool
278 select IRQ_DOMAIN
Marc Zyngier50091212017-08-18 09:39:25 +0100279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Sricharan R96ca8482013-12-03 15:57:23 +0530280
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000281config XILINX_INTC
Robert Hancockdebf69c2021-04-23 12:58:53 -0600282 bool "Xilinx Interrupt Controller IP"
283 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000284 select IRQ_DOMAIN
Robert Hancockdebf69c2021-04-23 12:58:53 -0600285 help
286 Support for the Xilinx Interrupt Controller IP core.
287 This is used as a primary controller with MicroBlaze and can also
288 be used as a secondary chained controller on other platforms.
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000289
Sricharan R96ca8482013-12-03 15:57:23 +0530290config IRQ_CROSSBAR
291 bool
292 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900293 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530294 The primary irqchip invokes the crossbar's callback which inturn allocates
295 a free irq and configures the IP. Thus the peripheral interrupts are
296 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300297
298config KEYSTONE_IRQ
299 tristate "Keystone 2 IRQ controller IP"
300 depends on ARCH_KEYSTONE
301 help
302 Support for Texas Instruments Keystone 2 IRQ controller IP which
303 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700304
305config MIPS_GIC
306 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000307 select GENERIC_IRQ_IPI
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700308 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900309
Paul Burton44e08e72015-05-24 16:11:31 +0100310config INGENIC_IRQ
311 bool
312 depends on MACH_INGENIC
313 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700314
Paul Cercueil9536eba2019-07-24 13:16:08 -0400315config INGENIC_TCU_IRQ
316 bool "Ingenic JZ47xx TCU interrupt controller"
317 default MACH_INGENIC
318 depends on MIPS || COMPILE_TEST
319 select MFD_SYSCON
YueHaibing80844992019-08-13 09:56:02 +0800320 select GENERIC_IRQ_CHIP
Paul Cercueil9536eba2019-07-24 13:16:08 -0400321 help
322 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
323 JZ47xx SoCs.
324
325 If unsure, say N.
326
Yoshinori Sato8a764482015-05-10 02:30:47 +0900327config RENESAS_H8300H_INTC
328 bool
329 select IRQ_DOMAIN
330
331config RENESAS_H8S_INTC
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200332 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
Linus Torvalds78c10e52015-06-27 12:44:34 -0700333 select IRQ_DOMAIN
Geert Uytterhoeven02d7e042019-06-07 11:50:36 +0200334 help
335 Enable support for the Renesas H8/300 Interrupt Controller, as found
336 on Renesas H8S SoCs.
Shenwei Wange324c4d2015-08-24 14:04:15 -0500337
338config IMX_GPCV2
339 bool
340 select IRQ_DOMAIN
341 help
342 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200343
344config IRQ_MXS
345 def_bool y if MACH_ASM9260 || ARCH_MXS
346 select IRQ_DOMAIN
347 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100348
Alexandre Belloni19d99162018-03-22 16:15:24 +0100349config MSCC_OCELOT_IRQ
350 bool
351 select IRQ_DOMAIN
352 select GENERIC_IRQ_CHIP
353
Thomas Petazzonia68a63c2017-06-21 15:29:14 +0200354config MVEBU_GICP
355 bool
356
Thomas Petazzonie0de91a2017-06-21 15:29:15 +0200357config MVEBU_ICU
358 bool
359
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100360config MVEBU_ODMI
361 bool
Arnd Bergmannfa23b9d2017-03-14 13:54:12 +0100362 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100363
Thomas Petazzonia1098932016-08-05 16:55:19 +0200364config MVEBU_PIC
365 bool
366
Miquel Raynal61ce8d82018-10-01 16:13:51 +0200367config MVEBU_SEI
368 bool
369
Rasmus Villemoes0dcd9f82019-11-07 13:21:15 +0100370config LS_EXTIRQ
371 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
372 select MFD_SYSCON
373
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800374config LS_SCFG_MSI
375 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
376 depends on PCI && PCI_MSI
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800377
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100378config PARTITION_PERCPU
379 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700380
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200381config STM32_EXTI
382 bool
383 select IRQ_DOMAIN
Ludovic Barre0e7d7802017-11-06 18:03:31 +0100384 select GENERIC_IRQ_CHIP
Agustin Vega-Friasf20cc9b2017-02-02 18:23:59 -0500385
386config QCOM_IRQ_COMBINER
387 bool "QCOM IRQ combiner support"
388 depends on ARCH_QCOM && ACPI
Agustin Vega-Friasf20cc9b2017-02-02 18:23:59 -0500389 select IRQ_DOMAIN_HIERARCHY
390 help
391 Say yes here to add support for the IRQ combiner devices embedded
392 in Qualcomm Technologies chips.
Masahiro Yamada5ed34d3a2017-08-23 10:31:47 +0900393
394config IRQ_UNIPHIER_AIDET
395 bool "UniPhier AIDET support" if COMPILE_TEST
396 depends on ARCH_UNIPHIER || COMPILE_TEST
397 default ARCH_UNIPHIER
398 select IRQ_DOMAIN_HIERARCHY
399 help
400 Support for the UniPhier AIDET (ARM Interrupt Detector).
Randy Dunlapc94fb632017-10-16 11:04:33 -0700401
Jerome Brunet215f4cc2017-09-18 15:46:10 +0200402config MESON_IRQ_GPIO
403 bool "Meson GPIO Interrupt Multiplexer"
Thomas Gleixnerd9ee91c2017-10-20 11:15:36 +0200404 depends on ARCH_MESON
Jerome Brunet215f4cc2017-09-18 15:46:10 +0200405 select IRQ_DOMAIN_HIERARCHY
406 help
407 Support Meson SoC Family GPIO Interrupt Multiplexer
408
Miodrag Dinic4235ff52017-12-29 16:41:46 +0100409config GOLDFISH_PIC
410 bool "Goldfish programmable interrupt controller"
411 depends on MIPS && (GOLDFISH || COMPILE_TEST)
412 select IRQ_DOMAIN
413 help
414 Say yes here to enable Goldfish interrupt controller driver used
415 for Goldfish based virtual platforms.
416
Archana Sathyakumarf55c73a2018-02-28 10:27:29 -0700417config QCOM_PDC
Saravana Kannan4acd8a42021-05-18 21:19:21 +0000418 tristate "QCOM PDC"
Archana Sathyakumarf55c73a2018-02-28 10:27:29 -0700419 depends on ARCH_QCOM
Archana Sathyakumarf55c73a2018-02-28 10:27:29 -0700420 select IRQ_DOMAIN_HIERARCHY
421 help
422 Power Domain Controller driver to manage and configure wakeup
423 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
424
Guo Rend8a5f5f2018-09-16 15:57:14 +0800425config CSKY_MPINTC
Guo Renbe1abc52021-02-04 15:46:08 +0800426 bool
Guo Rend8a5f5f2018-09-16 15:57:14 +0800427 depends on CSKY
428 help
429 Say yes here to enable C-SKY SMP interrupt controller driver used
430 for C-SKY SMP system.
Randy Dunlap656b42d2020-01-28 18:25:14 -0800431 In fact it's not mmio map in hardware and it uses ld/st to visit the
Guo Rend8a5f5f2018-09-16 15:57:14 +0800432 controller's register inside CPU.
433
Guo Renedff1b42018-09-16 15:57:14 +0800434config CSKY_APB_INTC
435 bool "C-SKY APB Interrupt Controller"
436 depends on CSKY
437 help
438 Say yes here to enable C-SKY APB interrupt controller driver used
Randy Dunlap656b42d2020-01-28 18:25:14 -0800439 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
Guo Renedff1b42018-09-16 15:57:14 +0800440 the controller's register.
441
Lucas Stach0136afa2018-12-17 15:01:20 +0100442config IMX_IRQSTEER
443 bool "i.MX IRQSTEER support"
444 depends on ARCH_MXC || COMPILE_TEST
445 default ARCH_MXC
446 select IRQ_DOMAIN
447 help
448 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
449
Joakim Zhang2fbb1392020-01-17 06:10:10 +0000450config IMX_INTMUX
Geert Uytterhoevena890cae2021-02-08 15:56:05 +0100451 bool "i.MX INTMUX support" if COMPILE_TEST
452 default y if ARCH_MXC
Joakim Zhang2fbb1392020-01-17 06:10:10 +0000453 select IRQ_DOMAIN
454 help
455 Support for the i.MX INTMUX interrupt multiplexer.
456
Jiaxun Yang9e543e22019-02-01 14:22:35 +0800457config LS1X_IRQ
458 bool "Loongson-1 Interrupt Controller"
459 depends on MACH_LOONGSON32
460 default y
461 select IRQ_DOMAIN
462 select GENERIC_IRQ_CHIP
463 help
464 Support for the Loongson-1 platform Interrupt Controller.
465
Lokesh Vutlacd844b02019-04-30 15:42:25 +0530466config TI_SCI_INTR_IRQCHIP
467 bool
468 depends on TI_SCI_PROTOCOL
469 select IRQ_DOMAIN_HIERARCHY
470 help
471 This enables the irqchip driver support for K3 Interrupt router
472 over TI System Control Interface available on some new TI's SoCs.
473 If you wish to use interrupt router irq resources managed by the
474 TI System Controller, say Y here. Otherwise, say N.
475
Lokesh Vutla9f1463b2019-04-30 15:42:27 +0530476config TI_SCI_INTA_IRQCHIP
477 bool
478 depends on TI_SCI_PROTOCOL
479 select IRQ_DOMAIN_HIERARCHY
Lokesh Vutlaf011df62019-04-30 15:42:29 +0530480 select TI_SCI_INTA_MSI_DOMAIN
Lokesh Vutla9f1463b2019-04-30 15:42:27 +0530481 help
482 This enables the irqchip driver support for K3 Interrupt aggregator
483 over TI System Control Interface available on some new TI's SoCs.
484 If you wish to use interrupt aggregator irq resources managed by the
485 TI System Controller, say Y here. Otherwise, say N.
486
Grzegorz Jaszczyk04e2d1e2020-09-16 18:36:03 +0200487config TI_PRUSS_INTC
Suman Annab8e594f2021-01-08 10:29:01 -0600488 tristate
489 depends on TI_PRUSS
490 default TI_PRUSS
Grzegorz Jaszczyk04e2d1e2020-09-16 18:36:03 +0200491 select IRQ_DOMAIN
492 help
493 This enables support for the PRU-ICSS Local Interrupt Controller
494 present within a PRU-ICSS subsystem present on various TI SoCs.
495 The PRUSS INTC enables various interrupts to be routed to multiple
496 different processors within the SoC.
497
Anup Patel6b7ce8922020-06-01 14:45:40 +0530498config RISCV_INTC
499 bool "RISC-V Local Interrupt Controller"
500 depends on RISCV
501 default y
502 help
503 This enables support for the per-HART local interrupt controller
504 found in standard RISC-V systems. The per-HART local interrupt
505 controller handles timer interrupts, software interrupts, and
506 hardware interrupts. Without a per-HART local interrupt controller,
507 a RISC-V system will be unable to handle any interrupts.
508
509 If you don't know what to do here, say Y.
510
Christoph Hellwig8237f8b2018-07-26 16:27:00 +0200511config SIFIVE_PLIC
512 bool "SiFive Platform-Level Interrupt Controller"
513 depends on RISCV
Yash Shah466008f2019-12-10 16:41:11 +0530514 select IRQ_DOMAIN_HIERARCHY
Christoph Hellwig8237f8b2018-07-26 16:27:00 +0200515 help
516 This enables support for the PLIC chip found in SiFive (and
517 potentially other) RISC-V systems. The PLIC controls devices
518 interrupts and connects them to each core's local interrupt
519 controller. Aside from timer and software interrupts, all other
520 interrupt sources are subordinate to the PLIC.
521
522 If you don't know what to do here, say Y.
Jonathan Neuschäfer01493852019-10-02 16:44:52 +0200523
Hyunki Koob74416d2019-12-25 06:11:07 +0900524config EXYNOS_IRQ_COMBINER
525 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
526 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
527 help
528 Say yes here to add support for the IRQ combiner devices embedded
529 in Samsung Exynos chips.
530
Jiaxun Yangdbb15222020-03-25 11:54:54 +0800531config LOONGSON_LIOINTC
532 bool "Loongson Local I/O Interrupt Controller"
533 depends on MACH_LOONGSON64
534 default y
535 select IRQ_DOMAIN
536 select GENERIC_IRQ_CHIP
537 help
538 Support for the Loongson Local I/O Interrupt Controller.
539
Jiaxun Yanga93f1d92020-03-25 11:54:57 +0800540config LOONGSON_HTPIC
541 bool "Loongson3 HyperTransport PIC Controller"
542 depends on MACH_LOONGSON64
543 default y
544 select IRQ_DOMAIN
545 select GENERIC_IRQ_CHIP
Jiaxun Yanga93f1d92020-03-25 11:54:57 +0800546 help
547 Support for the Loongson-3 HyperTransport PIC Controller.
548
Jiaxun Yang818e9152020-05-28 23:27:49 +0800549config LOONGSON_HTVEC
550 bool "Loongson3 HyperTransport Interrupt Vector Controller"
Ingo Molnard77aeb52020-06-01 09:45:27 +0200551 depends on MACH_LOONGSON64
Jiaxun Yang818e9152020-05-28 23:27:49 +0800552 default MACH_LOONGSON64
553 select IRQ_DOMAIN_HIERARCHY
554 help
555 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
556
Jiaxun Yangef8c01e2020-05-28 23:27:51 +0800557config LOONGSON_PCH_PIC
558 bool "Loongson PCH PIC Controller"
559 depends on MACH_LOONGSON64 || COMPILE_TEST
560 default MACH_LOONGSON64
561 select IRQ_DOMAIN_HIERARCHY
562 select IRQ_FASTEOI_HIERARCHY_HANDLERS
563 help
564 Support for the Loongson PCH PIC Controller.
565
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800566config LOONGSON_PCH_MSI
Jiaxun Yanga23df9a2020-05-30 20:11:12 +0800567 bool "Loongson PCH MSI Controller"
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800568 depends on MACH_LOONGSON64 || COMPILE_TEST
569 depends on PCI
570 default MACH_LOONGSON64
571 select IRQ_DOMAIN_HIERARCHY
572 select PCI_MSI
573 help
574 Support for the Loongson PCH MSI Controller.
575
Mark-PK Tsaiad4c9382020-09-02 14:33:43 +0800576config MST_IRQ
577 bool "MStar Interrupt Controller"
Geert Uytterhoeven61b06482020-10-14 15:17:03 +0200578 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
Mark-PK Tsaiad4c9382020-09-02 14:33:43 +0800579 default ARCH_MEDIATEK
580 select IRQ_DOMAIN
581 select IRQ_DOMAIN_HIERARCHY
582 help
583 Support MStar Interrupt Controller.
584
Jonathan Neuschäferfead4dd2021-04-06 14:09:17 +0200585config WPCM450_AIC
586 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
Marc Zyngier94bc9422021-04-08 08:56:27 +0100587 depends on ARCH_WPCM450
Jonathan Neuschäferfead4dd2021-04-06 14:09:17 +0200588 help
589 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
590
Thomas Bogendoerfer529ea362021-04-22 16:53:28 +0200591config IRQ_IDT3243X
592 bool
593 select GENERIC_IRQ_CHIP
594 select IRQ_DOMAIN
595
Hector Martin76cde262021-01-21 08:55:15 +0900596config APPLE_AIC
597 bool "Apple Interrupt Controller (AIC)"
598 depends on ARM64
Geert Uytterhoeven5b449552021-04-13 14:21:58 +0200599 depends on ARCH_APPLE || COMPILE_TEST
Hector Martin76cde262021-01-21 08:55:15 +0900600 help
601 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
602 such as the M1.
603
Jonathan Neuschäfer01493852019-10-02 16:44:52 +0200604endmenu