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Thomas Gleixner50acfb22019-05-29 07:18:00 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -07002/*
3 * Copyright (C) 2015 Regents of the University of California
Atish Patra84469232020-03-17 18:11:34 -07004 * Copyright (c) 2020 Western Digital Corporation or its affiliates.
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -07005 */
6
7#ifndef _ASM_RISCV_SBI_H
8#define _ASM_RISCV_SBI_H
9
10#include <linux/types.h>
11
Christoph Hellwig3b03ac62019-10-28 13:10:34 +010012#ifdef CONFIG_RISCV_SBI
Atish Patrab9dcd9e2020-03-17 18:11:35 -070013enum sbi_ext_id {
Atish Patraefca1392020-03-17 18:11:37 -070014#ifdef CONFIG_RISCV_SBI_V01
Atish Patrab9dcd9e2020-03-17 18:11:35 -070015 SBI_EXT_0_1_SET_TIMER = 0x0,
16 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
17 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
18 SBI_EXT_0_1_CLEAR_IPI = 0x3,
19 SBI_EXT_0_1_SEND_IPI = 0x4,
20 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
21 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
22 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
23 SBI_EXT_0_1_SHUTDOWN = 0x8,
Atish Patraefca1392020-03-17 18:11:37 -070024#endif
Atish Patrab9dcd9e2020-03-17 18:11:35 -070025 SBI_EXT_BASE = 0x10,
Atish Patraecbacc22020-03-17 18:11:36 -070026 SBI_EXT_TIME = 0x54494D45,
27 SBI_EXT_IPI = 0x735049,
28 SBI_EXT_RFENCE = 0x52464E43,
Atish Patradb5a7942020-03-17 18:11:42 -070029 SBI_EXT_HSM = 0x48534D,
Atish Patrab9dcd9e2020-03-17 18:11:35 -070030};
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -070031
Atish Patrab9dcd9e2020-03-17 18:11:35 -070032enum sbi_ext_base_fid {
33 SBI_EXT_BASE_GET_SPEC_VERSION = 0,
34 SBI_EXT_BASE_GET_IMP_ID,
35 SBI_EXT_BASE_GET_IMP_VERSION,
36 SBI_EXT_BASE_PROBE_EXT,
37 SBI_EXT_BASE_GET_MVENDORID,
38 SBI_EXT_BASE_GET_MARCHID,
39 SBI_EXT_BASE_GET_MIMPID,
40};
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -070041
Atish Patraecbacc22020-03-17 18:11:36 -070042enum sbi_ext_time_fid {
43 SBI_EXT_TIME_SET_TIMER = 0,
44};
45
46enum sbi_ext_ipi_fid {
47 SBI_EXT_IPI_SEND_IPI = 0,
48};
49
50enum sbi_ext_rfence_fid {
51 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
52 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
53 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
54 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
55 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
56 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
57 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
58};
59
Atish Patradb5a7942020-03-17 18:11:42 -070060enum sbi_ext_hsm_fid {
61 SBI_EXT_HSM_HART_START = 0,
62 SBI_EXT_HSM_HART_STOP,
63 SBI_EXT_HSM_HART_STATUS,
64};
65
66enum sbi_hsm_hart_status {
67 SBI_HSM_HART_STATUS_STARTED = 0,
68 SBI_HSM_HART_STATUS_STOPPED,
69 SBI_HSM_HART_STATUS_START_PENDING,
70 SBI_HSM_HART_STATUS_STOP_PENDING,
71};
72
Atish Patrab9dcd9e2020-03-17 18:11:35 -070073#define SBI_SPEC_VERSION_DEFAULT 0x1
74#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
75#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
76#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -070077
Atish Patrab9dcd9e2020-03-17 18:11:35 -070078/* SBI return error codes */
79#define SBI_SUCCESS 0
80#define SBI_ERR_FAILURE -1
81#define SBI_ERR_NOT_SUPPORTED -2
82#define SBI_ERR_INVALID_PARAM -3
83#define SBI_ERR_DENIED -4
84#define SBI_ERR_INVALID_ADDRESS -5
85
86extern unsigned long sbi_spec_version;
87struct sbiret {
88 long error;
89 long value;
90};
91
Kefeng Wang641e8cd2020-11-26 10:40:38 +080092void sbi_init(void);
Atish Patrab9dcd9e2020-03-17 18:11:35 -070093struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
94 unsigned long arg1, unsigned long arg2,
95 unsigned long arg3, unsigned long arg4,
96 unsigned long arg5);
97
98void sbi_console_putchar(int ch);
99int sbi_console_getchar(void);
100void sbi_set_timer(uint64_t stime_value);
101void sbi_shutdown(void);
102void sbi_clear_ipi(void);
103void sbi_send_ipi(const unsigned long *hart_mask);
104void sbi_remote_fence_i(const unsigned long *hart_mask);
105void sbi_remote_sfence_vma(const unsigned long *hart_mask,
106 unsigned long start,
107 unsigned long size);
108
109void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
110 unsigned long start,
111 unsigned long size,
112 unsigned long asid);
Atish Patra1ef46c22020-03-17 18:11:38 -0700113int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
114 unsigned long start,
115 unsigned long size);
116int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
117 unsigned long start,
118 unsigned long size,
119 unsigned long vmid);
120int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
121 unsigned long start,
122 unsigned long size);
123int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
124 unsigned long start,
125 unsigned long size,
126 unsigned long asid);
Atish Patrab9dcd9e2020-03-17 18:11:35 -0700127int sbi_probe_extension(int ext);
128
129/* Check if current SBI specification version is 0.1 or not */
130static inline int sbi_spec_is_0_1(void)
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -0700131{
Atish Patrab9dcd9e2020-03-17 18:11:35 -0700132 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -0700133}
134
Atish Patrab9dcd9e2020-03-17 18:11:35 -0700135/* Get the major version of SBI */
136static inline unsigned long sbi_major_version(void)
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -0700137{
Atish Patrab9dcd9e2020-03-17 18:11:35 -0700138 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
139 SBI_SPEC_VERSION_MAJOR_MASK;
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -0700140}
141
Atish Patrab9dcd9e2020-03-17 18:11:35 -0700142/* Get the minor version of SBI */
143static inline unsigned long sbi_minor_version(void)
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -0700144{
Atish Patrab9dcd9e2020-03-17 18:11:35 -0700145 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
Palmer Dabbelt6d60b6e2017-07-10 18:05:09 -0700146}
Atish Patraf90b43c2020-03-17 18:11:41 -0700147
148int sbi_err_map_linux_errno(int err);
Christoph Hellwig8bf90f32019-10-28 13:10:36 +0100149#else /* CONFIG_RISCV_SBI */
Kefeng Wang641e8cd2020-11-26 10:40:38 +0800150static inline void sbi_remote_fence_i(const unsigned long *hart_mask) {}
151static inline void sbi_init(void) {}
Christoph Hellwig3b03ac62019-10-28 13:10:34 +0100152#endif /* CONFIG_RISCV_SBI */
153#endif /* _ASM_RISCV_SBI_H */