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Catalin Marinas6170a972012-03-05 11:49:29 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_FUTEX_H
17#define __ASM_FUTEX_H
18
19#ifdef __KERNEL__
20
21#include <linux/futex.h>
22#include <linux/uaccess.h>
James Morse338d4f42015-07-22 19:05:54 +010023
Catalin Marinas6170a972012-03-05 11:49:29 +000024#include <asm/errno.h>
25
26#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
Catalin Marinasbd389672016-07-01 14:58:21 +010027do { \
28 uaccess_enable(); \
Catalin Marinas6170a972012-03-05 11:49:29 +000029 asm volatile( \
Will Deacon0ea366f2015-05-29 13:31:10 +010030" prfm pstl1strm, %2\n" \
Will Deacon8e86f0b2014-02-04 12:29:12 +000031"1: ldxr %w1, %2\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000032 insn "\n" \
Will Deacon045afc22019-04-08 12:45:09 +010033"2: stlxr %w0, %w3, %2\n" \
34" cbnz %w0, 1b\n" \
Will Deacon8e86f0b2014-02-04 12:29:12 +000035" dmb ish\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000036"3:\n" \
37" .pushsection .fixup,\"ax\"\n" \
Will Deacon4da7a562013-11-06 19:31:24 +000038" .align 2\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000039"4: mov %w0, %w5\n" \
40" b 3b\n" \
41" .popsection\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010042 _ASM_EXTABLE(1b, 4b) \
43 _ASM_EXTABLE(2b, 4b) \
Catalin Marinas6170a972012-03-05 11:49:29 +000044 : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
45 : "r" (oparg), "Ir" (-EFAULT) \
Catalin Marinasbd389672016-07-01 14:58:21 +010046 : "memory"); \
47 uaccess_disable(); \
48} while (0)
Catalin Marinas6170a972012-03-05 11:49:29 +000049
50static inline int
Will Deacon91b2d342018-02-05 15:34:24 +000051arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr)
Catalin Marinas6170a972012-03-05 11:49:29 +000052{
Nathan Chancellorff8acf92019-04-17 00:21:21 -070053 int oldval = 0, ret, tmp;
Will Deacon91b2d342018-02-05 15:34:24 +000054 u32 __user *uaddr = __uaccess_mask_ptr(_uaddr);
Catalin Marinas6170a972012-03-05 11:49:29 +000055
David Hildenbrand2f09b222015-05-11 17:52:17 +020056 pagefault_disable();
Catalin Marinas6170a972012-03-05 11:49:29 +000057
58 switch (op) {
59 case FUTEX_OP_SET:
Will Deacon045afc22019-04-08 12:45:09 +010060 __futex_atomic_op("mov %w3, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000061 ret, oldval, uaddr, tmp, oparg);
62 break;
63 case FUTEX_OP_ADD:
Will Deacon045afc22019-04-08 12:45:09 +010064 __futex_atomic_op("add %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000065 ret, oldval, uaddr, tmp, oparg);
66 break;
67 case FUTEX_OP_OR:
Will Deacon045afc22019-04-08 12:45:09 +010068 __futex_atomic_op("orr %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000069 ret, oldval, uaddr, tmp, oparg);
70 break;
71 case FUTEX_OP_ANDN:
Will Deacon045afc22019-04-08 12:45:09 +010072 __futex_atomic_op("and %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000073 ret, oldval, uaddr, tmp, ~oparg);
74 break;
75 case FUTEX_OP_XOR:
Will Deacon045afc22019-04-08 12:45:09 +010076 __futex_atomic_op("eor %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000077 ret, oldval, uaddr, tmp, oparg);
78 break;
79 default:
80 ret = -ENOSYS;
81 }
82
David Hildenbrand2f09b222015-05-11 17:52:17 +020083 pagefault_enable();
Catalin Marinas6170a972012-03-05 11:49:29 +000084
Jiri Slaby30d6e0a2017-08-24 09:31:05 +020085 if (!ret)
86 *oval = oldval;
87
Catalin Marinas6170a972012-03-05 11:49:29 +000088 return ret;
89}
90
91static inline int
Will Deacon91b2d342018-02-05 15:34:24 +000092futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
Catalin Marinas6170a972012-03-05 11:49:29 +000093 u32 oldval, u32 newval)
94{
95 int ret = 0;
96 u32 val, tmp;
Will Deacon91b2d342018-02-05 15:34:24 +000097 u32 __user *uaddr;
Catalin Marinas6170a972012-03-05 11:49:29 +000098
Linus Torvalds96d4f262019-01-03 18:57:57 -080099 if (!access_ok(_uaddr, sizeof(u32)))
Catalin Marinas6170a972012-03-05 11:49:29 +0000100 return -EFAULT;
101
Will Deacon91b2d342018-02-05 15:34:24 +0000102 uaddr = __uaccess_mask_ptr(_uaddr);
Catalin Marinasbd389672016-07-01 14:58:21 +0100103 uaccess_enable();
Catalin Marinas6170a972012-03-05 11:49:29 +0000104 asm volatile("// futex_atomic_cmpxchg_inatomic\n"
Will Deacon0ea366f2015-05-29 13:31:10 +0100105" prfm pstl1strm, %2\n"
Will Deacon8e86f0b2014-02-04 12:29:12 +0000106"1: ldxr %w1, %2\n"
Catalin Marinas6170a972012-03-05 11:49:29 +0000107" sub %w3, %w1, %w4\n"
108" cbnz %w3, 3f\n"
109"2: stlxr %w3, %w5, %2\n"
110" cbnz %w3, 1b\n"
Will Deacon8e86f0b2014-02-04 12:29:12 +0000111" dmb ish\n"
Catalin Marinas6170a972012-03-05 11:49:29 +0000112"3:\n"
113" .pushsection .fixup,\"ax\"\n"
114"4: mov %w0, %w6\n"
115" b 3b\n"
116" .popsection\n"
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100117 _ASM_EXTABLE(1b, 4b)
118 _ASM_EXTABLE(2b, 4b)
Catalin Marinas6170a972012-03-05 11:49:29 +0000119 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
120 : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
Will Deacon95c41892014-02-04 12:29:13 +0000121 : "memory");
Catalin Marinasbd389672016-07-01 14:58:21 +0100122 uaccess_disable();
Catalin Marinas6170a972012-03-05 11:49:29 +0000123
124 *uval = val;
125 return ret;
126}
127
128#endif /* __KERNEL__ */
129#endif /* __ASM_FUTEX_H */