blob: ccaad1cb3c2e9e9ae8b8ddb81b32409c5508638c [file] [log] [blame]
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
5 */
6
7#include <linux/err.h>
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of_irq.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15
16#define MTK_BANK_CNT 3
17#define MTK_BANK_WIDTH 32
18
19#define GPIO_BANK_STRIDE 0x04
20#define GPIO_REG_CTRL 0x00
21#define GPIO_REG_POL 0x10
22#define GPIO_REG_DATA 0x20
23#define GPIO_REG_DSET 0x30
24#define GPIO_REG_DCLR 0x40
25#define GPIO_REG_REDGE 0x50
26#define GPIO_REG_FEDGE 0x60
27#define GPIO_REG_HLVL 0x70
28#define GPIO_REG_LLVL 0x80
29#define GPIO_REG_STAT 0x90
30#define GPIO_REG_EDGE 0xA0
31
32struct mtk_gc {
René van Dorstfa846672019-01-30 17:10:49 +010033 struct irq_chip irq_chip;
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020034 struct gpio_chip chip;
35 spinlock_t lock;
36 int bank;
37 u32 rising;
38 u32 falling;
39 u32 hlevel;
40 u32 llevel;
41};
42
43/**
Linus Walleij85124862018-07-09 13:51:57 +020044 * struct mtk - state container for
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020045 * data of the platform driver. It is 3
46 * separate gpio-chip each one with its
47 * own irq_chip.
48 * @dev: device instance
Linus Walleij85124862018-07-09 13:51:57 +020049 * @base: memory base address
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020050 * @gpio_irq: irq number from the device tree
51 * @gc_map: array of the gpio chips
52 */
Linus Walleij85124862018-07-09 13:51:57 +020053struct mtk {
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020054 struct device *dev;
Linus Walleij85124862018-07-09 13:51:57 +020055 void __iomem *base;
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020056 int gpio_irq;
57 struct mtk_gc gc_map[MTK_BANK_CNT];
58};
59
60static inline struct mtk_gc *
61to_mediatek_gpio(struct gpio_chip *chip)
62{
63 return container_of(chip, struct mtk_gc, chip);
64}
65
66static inline void
67mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
68{
69 struct gpio_chip *gc = &rg->chip;
Linus Walleij85124862018-07-09 13:51:57 +020070 struct mtk *mtk = gpiochip_get_data(gc);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020071
72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
Linus Walleij85124862018-07-09 13:51:57 +020073 gc->write_reg(mtk->base + offset, val);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020074}
75
76static inline u32
77mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
78{
79 struct gpio_chip *gc = &rg->chip;
Linus Walleij85124862018-07-09 13:51:57 +020080 struct mtk *mtk = gpiochip_get_data(gc);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020081
82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
Linus Walleij85124862018-07-09 13:51:57 +020083 return gc->read_reg(mtk->base + offset);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020084}
85
86static irqreturn_t
87mediatek_gpio_irq_handler(int irq, void *data)
88{
89 struct gpio_chip *gc = data;
90 struct mtk_gc *rg = to_mediatek_gpio(gc);
91 irqreturn_t ret = IRQ_NONE;
92 unsigned long pending;
93 int bit;
94
95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
96
97 for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
Marc Zyngierdbd1c542021-05-04 17:42:18 +010098 generic_handle_domain_irq(gc->irq.domain, bit);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +020099 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
100 ret |= IRQ_HANDLED;
101 }
102
103 return ret;
104}
105
106static void
107mediatek_gpio_irq_unmask(struct irq_data *d)
108{
109 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
110 struct mtk_gc *rg = to_mediatek_gpio(gc);
111 int pin = d->hwirq;
112 unsigned long flags;
113 u32 rise, fall, high, low;
114
115 spin_lock_irqsave(&rg->lock, flags);
116 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
117 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
118 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
119 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
120 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
121 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
122 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
123 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
124 spin_unlock_irqrestore(&rg->lock, flags);
125}
126
127static void
128mediatek_gpio_irq_mask(struct irq_data *d)
129{
130 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
131 struct mtk_gc *rg = to_mediatek_gpio(gc);
132 int pin = d->hwirq;
133 unsigned long flags;
134 u32 rise, fall, high, low;
135
136 spin_lock_irqsave(&rg->lock, flags);
137 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
138 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
139 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
140 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
141 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
142 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
143 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
144 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
145 spin_unlock_irqrestore(&rg->lock, flags);
146}
147
148static int
149mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
150{
151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
152 struct mtk_gc *rg = to_mediatek_gpio(gc);
153 int pin = d->hwirq;
154 u32 mask = BIT(pin);
155
156 if (type == IRQ_TYPE_PROBE) {
157 if ((rg->rising | rg->falling |
158 rg->hlevel | rg->llevel) & mask)
159 return 0;
160
161 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
162 }
163
164 rg->rising &= ~mask;
165 rg->falling &= ~mask;
166 rg->hlevel &= ~mask;
167 rg->llevel &= ~mask;
168
169 switch (type & IRQ_TYPE_SENSE_MASK) {
170 case IRQ_TYPE_EDGE_BOTH:
171 rg->rising |= mask;
172 rg->falling |= mask;
173 break;
174 case IRQ_TYPE_EDGE_RISING:
175 rg->rising |= mask;
176 break;
177 case IRQ_TYPE_EDGE_FALLING:
178 rg->falling |= mask;
179 break;
180 case IRQ_TYPE_LEVEL_HIGH:
181 rg->hlevel |= mask;
182 break;
183 case IRQ_TYPE_LEVEL_LOW:
184 rg->llevel |= mask;
185 break;
186 }
187
188 return 0;
189}
190
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200191static int
192mediatek_gpio_xlate(struct gpio_chip *chip,
193 const struct of_phandle_args *spec, u32 *flags)
194{
195 int gpio = spec->args[0];
196 struct mtk_gc *rg = to_mediatek_gpio(chip);
197
198 if (rg->bank != gpio / MTK_BANK_WIDTH)
199 return -EINVAL;
200
201 if (flags)
202 *flags = spec->args[1];
203
204 return gpio % MTK_BANK_WIDTH;
205}
206
207static int
Andy Shevchenko98044562021-12-20 15:24:39 +0200208mediatek_gpio_bank_probe(struct device *dev, int bank)
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200209{
Linus Walleij85124862018-07-09 13:51:57 +0200210 struct mtk *mtk = dev_get_drvdata(dev);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200211 struct mtk_gc *rg;
212 void __iomem *dat, *set, *ctrl, *diro;
213 int ret;
214
Linus Walleij85124862018-07-09 13:51:57 +0200215 rg = &mtk->gc_map[bank];
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200216 memset(rg, 0, sizeof(*rg));
217
218 spin_lock_init(&rg->lock);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200219 rg->bank = bank;
220
Linus Walleij85124862018-07-09 13:51:57 +0200221 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
222 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
223 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
224 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200225
Chuanhong Guo427cabe2020-03-15 20:13:38 +0800226 ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
227 BGPIOF_NO_SET_ON_INPUT);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200228 if (ret) {
Linus Walleij85124862018-07-09 13:51:57 +0200229 dev_err(dev, "bgpio_init() failed\n");
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200230 return ret;
231 }
232
233 rg->chip.of_gpio_n_cells = 2;
234 rg->chip.of_xlate = mediatek_gpio_xlate;
Linus Walleij85124862018-07-09 13:51:57 +0200235 rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
236 dev_name(dev), bank);
Nicholas Mc Guire59d646c2018-11-21 19:06:12 +0100237 if (!rg->chip.label)
238 return -ENOMEM;
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200239
Sergio Paracuellos0fb90392021-07-28 06:12:52 +0200240 rg->chip.offset = bank * MTK_BANK_WIDTH;
René van Dorstfa846672019-01-30 17:10:49 +0100241 rg->irq_chip.name = dev_name(dev);
242 rg->irq_chip.parent_device = dev;
243 rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
244 rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
245 rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
246 rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
247
Linus Walleij85124862018-07-09 13:51:57 +0200248 if (mtk->gpio_irq) {
Linus Walleijf4e9bcc2019-08-09 16:11:16 +0200249 struct gpio_irq_chip *girq;
250
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200251 /*
Linus Walleijf4e9bcc2019-08-09 16:11:16 +0200252 * Directly request the irq here instead of passing
Linus Walleij72780ce2020-01-13 23:08:00 +0100253 * a flow-handler because the irq is shared.
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200254 */
Linus Walleij85124862018-07-09 13:51:57 +0200255 ret = devm_request_irq(dev, mtk->gpio_irq,
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200256 mediatek_gpio_irq_handler, IRQF_SHARED,
257 rg->chip.label, &rg->chip);
258
259 if (ret) {
Linus Walleij85124862018-07-09 13:51:57 +0200260 dev_err(dev, "Error requesting IRQ %d: %d\n",
261 mtk->gpio_irq, ret);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200262 return ret;
263 }
264
Linus Walleijf4e9bcc2019-08-09 16:11:16 +0200265 girq = &rg->chip.irq;
266 girq->chip = &rg->irq_chip;
267 /* This will let us handle the parent IRQ in the driver */
268 girq->parent_handler = NULL;
269 girq->num_parents = 0;
270 girq->parents = NULL;
271 girq->default_type = IRQ_TYPE_NONE;
272 girq->handler = handle_simple_irq;
273 }
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200274
Linus Walleijf4e9bcc2019-08-09 16:11:16 +0200275 ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
276 if (ret < 0) {
277 dev_err(dev, "Could not register gpio %d, ret=%d\n",
278 rg->chip.ngpio, ret);
279 return ret;
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200280 }
281
282 /* set polarity to low for all gpios */
283 mtk_gpio_w32(rg, GPIO_REG_POL, 0);
284
Linus Walleij85124862018-07-09 13:51:57 +0200285 dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200286
287 return 0;
288}
289
290static int
291mediatek_gpio_probe(struct platform_device *pdev)
292{
Linus Walleij85124862018-07-09 13:51:57 +0200293 struct device *dev = &pdev->dev;
294 struct device_node *np = dev->of_node;
295 struct mtk *mtk;
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200296 int i;
Nicholas Mc Guirea109c2d2018-11-27 18:00:18 +0100297 int ret;
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200298
Linus Walleij85124862018-07-09 13:51:57 +0200299 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
300 if (!mtk)
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200301 return -ENOMEM;
302
Enrico Weigelt, metux IT consult92d718f2019-03-11 19:54:59 +0100303 mtk->base = devm_platform_ioremap_resource(pdev, 0);
Linus Walleij85124862018-07-09 13:51:57 +0200304 if (IS_ERR(mtk->base))
305 return PTR_ERR(mtk->base);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200306
Linus Walleij85124862018-07-09 13:51:57 +0200307 mtk->gpio_irq = irq_of_parse_and_map(np, 0);
308 mtk->dev = dev;
309 platform_set_drvdata(pdev, mtk);
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200310
Nicholas Mc Guirea109c2d2018-11-27 18:00:18 +0100311 for (i = 0; i < MTK_BANK_CNT; i++) {
Andy Shevchenko98044562021-12-20 15:24:39 +0200312 ret = mediatek_gpio_bank_probe(dev, i);
Nicholas Mc Guirea109c2d2018-11-27 18:00:18 +0100313 if (ret)
314 return ret;
315 }
Sergio Paracuellos4ba9c3a2018-07-05 15:43:10 +0200316
317 return 0;
318}
319
320static const struct of_device_id mediatek_gpio_match[] = {
321 { .compatible = "mediatek,mt7621-gpio" },
322 {},
323};
324MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
325
326static struct platform_driver mediatek_gpio_driver = {
327 .probe = mediatek_gpio_probe,
328 .driver = {
329 .name = "mt7621_gpio",
330 .of_match_table = mediatek_gpio_match,
331 },
332};
333
334builtin_platform_driver(mediatek_gpio_driver);