| Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ |
| 3 | #ifndef __CXL_PCI_H__ |
| 4 | #define __CXL_PCI_H__ |
| 5 | |
| 6 | #define CXL_MEMORY_PROGIF 0x10 |
| 7 | |
| 8 | /* |
| 9 | * See section 8.1 Configuration Space Registers in the CXL 2.0 |
| 10 | * Specification |
| 11 | */ |
| Ben Widawsky | 8adaf74 | 2021-02-16 20:09:51 -0800 | [diff] [blame] | 12 | #define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) |
| Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 13 | #define PCI_DVSEC_VENDOR_ID_CXL 0x1E98 |
| 14 | #define PCI_DVSEC_ID_CXL 0x0 |
| 15 | |
| Ben Widawsky | 4ad6181 | 2021-06-17 17:30:09 -0700 | [diff] [blame] | 16 | #define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID 0x8 |
| Ben Widawsky | 8adaf74 | 2021-02-16 20:09:51 -0800 | [diff] [blame] | 17 | #define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC |
| 18 | |
| 19 | /* BAR Indicator Register (BIR) */ |
| 20 | #define CXL_REGLOC_BIR_MASK GENMASK(2, 0) |
| 21 | |
| 22 | /* Register Block Identifier (RBI) */ |
| 23 | #define CXL_REGLOC_RBI_MASK GENMASK(15, 8) |
| 24 | #define CXL_REGLOC_RBI_EMPTY 0 |
| 25 | #define CXL_REGLOC_RBI_COMPONENT 1 |
| 26 | #define CXL_REGLOC_RBI_VIRT 2 |
| 27 | #define CXL_REGLOC_RBI_MEMDEV 3 |
| Ben Widawsky | 5b68705 | 2021-07-16 16:15:47 -0700 | [diff] [blame] | 28 | #define CXL_REGLOC_RBI_TYPES CXL_REGLOC_RBI_MEMDEV + 1 |
| Ben Widawsky | 8adaf74 | 2021-02-16 20:09:51 -0800 | [diff] [blame] | 29 | |
| 30 | #define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) |
| Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 31 | |
| 32 | #endif /* __CXL_PCI_H__ */ |