Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm64/include/asm/cpucaps.h |
| 3 | * |
| 4 | * Copyright (C) 2016 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | #ifndef __ASM_CPUCAPS_H |
| 19 | #define __ASM_CPUCAPS_H |
| 20 | |
| 21 | #define ARM64_WORKAROUND_CLEAN_CACHE 0 |
| 22 | #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 |
| 23 | #define ARM64_WORKAROUND_845719 2 |
| 24 | #define ARM64_HAS_SYSREG_GIC_CPUIF 3 |
| 25 | #define ARM64_HAS_PAN 4 |
| 26 | #define ARM64_HAS_LSE_ATOMICS 5 |
| 27 | #define ARM64_WORKAROUND_CAVIUM_23154 6 |
| 28 | #define ARM64_WORKAROUND_834220 7 |
| 29 | #define ARM64_HAS_NO_HW_PREFETCH 8 |
| 30 | #define ARM64_HAS_UAO 9 |
| 31 | #define ARM64_ALT_PAN_NOT_UAO 10 |
| 32 | #define ARM64_HAS_VIRT_HOST_EXTN 11 |
| 33 | #define ARM64_WORKAROUND_CAVIUM_27456 12 |
| 34 | #define ARM64_HAS_32BIT_EL0 13 |
Marc Zyngier | 71dcb8b | 2018-02-27 17:38:08 +0000 | [diff] [blame] | 35 | #define ARM64_HARDEN_EL2_VECTORS 14 |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 36 | #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 |
Linus Torvalds | f4000cd9 | 2016-12-13 16:39:21 -0800 | [diff] [blame] | 37 | #define ARM64_HAS_NO_FPSIMD 16 |
Christopher Covington | d9ff80f | 2017-01-31 12:50:19 -0500 | [diff] [blame] | 38 | #define ARM64_WORKAROUND_REPEAT_TLBI 17 |
Christopher Covington | 38fd94b | 2017-02-08 15:08:37 -0500 | [diff] [blame] | 39 | #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 |
Marc Zyngier | eeb1efb | 2017-03-20 17:18:06 +0000 | [diff] [blame] | 40 | #define ARM64_WORKAROUND_858921 19 |
David Daney | 690a341 | 2017-06-09 12:49:48 +0100 | [diff] [blame] | 41 | #define ARM64_WORKAROUND_CAVIUM_30115 20 |
Robin Murphy | d50e071 | 2017-07-25 11:55:42 +0100 | [diff] [blame] | 42 | #define ARM64_HAS_DCPOP 21 |
Dave Martin | 43994d8 | 2017-10-31 15:51:19 +0000 | [diff] [blame] | 43 | #define ARM64_SVE 22 |
Will Deacon | ea1e3de | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 44 | #define ARM64_UNMAP_KERNEL_AT_EL0 23 |
Will Deacon | 0f15adb | 2018-01-03 11:17:58 +0000 | [diff] [blame] | 45 | #define ARM64_HARDEN_BRANCH_PREDICTOR 24 |
Shanker Donthineni | 4bc352f | 2018-04-10 11:36:42 +0100 | [diff] [blame] | 46 | #define ARM64_HAS_RAS_EXTN 25 |
| 47 | #define ARM64_WORKAROUND_843419 26 |
| 48 | #define ARM64_HAS_CACHE_IDC 27 |
| 49 | #define ARM64_HAS_CACHE_DIC 28 |
| 50 | #define ARM64_HW_DBM 29 |
Marc Zyngier | a725e3d | 2018-05-29 13:11:08 +0100 | [diff] [blame] | 51 | #define ARM64_SSBD 30 |
Suzuki K Poulose | 314d53d | 2018-07-04 23:07:46 +0100 | [diff] [blame] | 52 | #define ARM64_MISMATCHED_CACHE_TYPE 31 |
Paolo Bonzini | 6319893 | 2018-08-22 14:07:56 +0200 | [diff] [blame] | 53 | #define ARM64_HAS_STAGE2_FWB 32 |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 54 | |
Paolo Bonzini | 6319893 | 2018-08-22 14:07:56 +0200 | [diff] [blame] | 55 | #define ARM64_NCAPS 33 |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 56 | |
| 57 | #endif /* __ASM_CPUCAPS_H */ |