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Thomas Gleixner16216332019-05-19 15:51:31 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Shawn Guo289569f2010-12-18 21:39:28 +08002/*
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
Oleksij Rempel7e4ac672015-10-12 21:15:34 +02004 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
5 * Add Alphascale ASM9260 support.
Shawn Guo289569f2010-12-18 21:39:28 +08006 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/irq.h>
Joel Porquet41a83e062015-07-07 17:11:46 -040011#include <linux/irqchip.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080012#include <linux/irqdomain.h>
Shawn Guo289569f2010-12-18 21:39:28 +080013#include <linux/io.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080014#include <linux/of.h>
Shawn Guo8256aa72013-03-25 21:13:22 +080015#include <linux/of_address.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080016#include <linux/of_irq.h>
Shawn Guocec6bae2013-03-25 21:20:05 +080017#include <linux/stmp_device.h>
Shawn Guo4e0a1b82012-08-20 10:14:56 +080018#include <asm/exception.h>
Shawn Guo289569f2010-12-18 21:39:28 +080019
Oleksij Rempel7e4ac672015-10-12 21:15:34 +020020#include "alphascale_asm9260-icoll.h"
21
Oleksij Rempel25e34b42015-10-12 21:15:33 +020022/*
23 * this device provide 4 offsets for each register:
24 * 0x0 - plain read write mode
25 * 0x4 - set mode, OR logic.
26 * 0x8 - clr mode, XOR logic.
27 * 0xc - togle mode.
28 */
29#define SET_REG 4
30#define CLR_REG 8
31
Shawn Guo289569f2010-12-18 21:39:28 +080032#define HW_ICOLL_VECTOR 0x0000
33#define HW_ICOLL_LEVELACK 0x0010
34#define HW_ICOLL_CTRL 0x0020
Shawn Guo4e0a1b82012-08-20 10:14:56 +080035#define HW_ICOLL_STAT_OFFSET 0x0070
Oleksij Rempel25e34b42015-10-12 21:15:33 +020036#define HW_ICOLL_INTERRUPT0 0x0120
37#define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10)
38#define BM_ICOLL_INTR_ENABLE BIT(2)
Shawn Guo289569f2010-12-18 21:39:28 +080039#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
40
Shawn Guo83a84ef2012-08-20 21:34:56 +080041#define ICOLL_NUM_IRQS 128
42
Oleksij Rempel7e4ac672015-10-12 21:15:34 +020043enum icoll_type {
44 ICOLL,
45 ASM9260_ICOLL,
46};
47
Oleksij Rempel25e34b42015-10-12 21:15:33 +020048struct icoll_priv {
49 void __iomem *vector;
50 void __iomem *levelack;
51 void __iomem *ctrl;
52 void __iomem *stat;
53 void __iomem *intr;
Oleksij Rempel7e4ac672015-10-12 21:15:34 +020054 void __iomem *clear;
55 enum icoll_type type;
Oleksij Rempel25e34b42015-10-12 21:15:33 +020056};
57
58static struct icoll_priv icoll_priv;
Shawn Guo83a84ef2012-08-20 21:34:56 +080059static struct irq_domain *icoll_domain;
Shawn Guo289569f2010-12-18 21:39:28 +080060
Oleksij Rempel7e4ac672015-10-12 21:15:34 +020061/* calculate bit offset depending on number of intterupt per register */
62static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
63{
64 /*
65 * mask lower part of hwirq to convert it
66 * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
67 */
68 return bit << ((d->hwirq & 3) << 3);
69}
70
71/* calculate mem offset depending on number of intterupt per register */
72static void __iomem *icoll_intr_reg(struct irq_data *d)
73{
74 /* offset = hwirq / intr_per_reg * 0x10 */
75 return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
76}
77
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010078static void icoll_ack_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080079{
80 /*
81 * The Interrupt Collector is able to prioritize irqs.
82 * Currently only level 0 is used. So acking can use
83 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
84 */
85 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
Oleksij Rempel25e34b42015-10-12 21:15:33 +020086 icoll_priv.levelack);
Shawn Guo289569f2010-12-18 21:39:28 +080087}
88
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010089static void icoll_mask_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080090{
Oleksij Rempel25e34b42015-10-12 21:15:33 +020091 __raw_writel(BM_ICOLL_INTR_ENABLE,
92 icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
Shawn Guo289569f2010-12-18 21:39:28 +080093}
94
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010095static void icoll_unmask_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080096{
Oleksij Rempel25e34b42015-10-12 21:15:33 +020097 __raw_writel(BM_ICOLL_INTR_ENABLE,
98 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
Shawn Guo289569f2010-12-18 21:39:28 +080099}
100
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200101static void asm9260_mask_irq(struct irq_data *d)
102{
103 __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
104 icoll_intr_reg(d) + CLR_REG);
105}
106
107static void asm9260_unmask_irq(struct irq_data *d)
108{
109 __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
110 icoll_priv.clear +
111 ASM9260_HW_ICOLL_CLEARn(d->hwirq));
112
113 __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
114 icoll_intr_reg(d) + SET_REG);
115}
116
Shawn Guo289569f2010-12-18 21:39:28 +0800117static struct irq_chip mxs_icoll_chip = {
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +0100118 .irq_ack = icoll_ack_irq,
119 .irq_mask = icoll_mask_irq,
120 .irq_unmask = icoll_unmask_irq,
Stefan Wahren88e20c72016-12-27 18:29:57 +0000121 .flags = IRQCHIP_MASK_ON_SUSPEND |
122 IRQCHIP_SKIP_SET_WAKE,
Shawn Guo289569f2010-12-18 21:39:28 +0800123};
124
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200125static struct irq_chip asm9260_icoll_chip = {
126 .irq_ack = icoll_ack_irq,
127 .irq_mask = asm9260_mask_irq,
128 .irq_unmask = asm9260_unmask_irq,
Stefan Wahren88e20c72016-12-27 18:29:57 +0000129 .flags = IRQCHIP_MASK_ON_SUSPEND |
130 IRQCHIP_SKIP_SET_WAKE,
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200131};
132
Shawn Guo4e0a1b82012-08-20 10:14:56 +0800133asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
134{
135 u32 irqnr;
136
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200137 irqnr = __raw_readl(icoll_priv.stat);
138 __raw_writel(irqnr, icoll_priv.vector);
Marc Zyngierb3410e52014-08-26 11:03:24 +0100139 handle_domain_irq(icoll_domain, irqnr, regs);
Shawn Guo4e0a1b82012-08-20 10:14:56 +0800140}
141
Shawn Guo83a84ef2012-08-20 21:34:56 +0800142static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
143 irq_hw_number_t hw)
Shawn Guo289569f2010-12-18 21:39:28 +0800144{
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200145 struct irq_chip *chip;
146
147 if (icoll_priv.type == ICOLL)
148 chip = &mxs_icoll_chip;
149 else
150 chip = &asm9260_icoll_chip;
151
152 irq_set_chip_and_handler(virq, chip, handle_level_irq);
Shawn Guo289569f2010-12-18 21:39:28 +0800153
Shawn Guo83a84ef2012-08-20 21:34:56 +0800154 return 0;
155}
156
Krzysztof Kozlowski96009732015-04-27 21:54:24 +0900157static const struct irq_domain_ops icoll_irq_domain_ops = {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800158 .map = icoll_irq_domain_map,
159 .xlate = irq_domain_xlate_onecell,
160};
161
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200162static void __init icoll_add_domain(struct device_node *np,
163 int num)
164{
165 icoll_domain = irq_domain_add_linear(np, num,
166 &icoll_irq_domain_ops, NULL);
167
168 if (!icoll_domain)
Rob Herringe81f54c2017-07-18 16:43:10 -0500169 panic("%pOF: unable to create irq domain", np);
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200170}
171
172static void __iomem * __init icoll_init_iobase(struct device_node *np)
173{
174 void __iomem *icoll_base;
175
176 icoll_base = of_io_request_and_map(np, 0, np->name);
Vladimir Zapolskiyedf8fcd2016-03-09 03:21:40 +0200177 if (IS_ERR(icoll_base))
Rob Herringe81f54c2017-07-18 16:43:10 -0500178 panic("%pOF: unable to map resource", np);
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200179 return icoll_base;
180}
181
Rob Herring10776b52014-05-12 11:37:07 -0500182static int __init icoll_of_init(struct device_node *np,
Shawn Guo83a84ef2012-08-20 21:34:56 +0800183 struct device_node *interrupt_parent)
184{
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200185 void __iomem *icoll_base;
186
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200187 icoll_priv.type = ICOLL;
188
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200189 icoll_base = icoll_init_iobase(np);
190 icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
191 icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
192 icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
193 icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
194 icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200195 icoll_priv.clear = NULL;
Shawn Guo8256aa72013-03-25 21:13:22 +0800196
Shawn Guo289569f2010-12-18 21:39:28 +0800197 /*
198 * Interrupt Collector reset, which initializes the priority
199 * for each irq to level 0.
200 */
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200201 stmp_reset_block(icoll_priv.ctrl);
Shawn Guo289569f2010-12-18 21:39:28 +0800202
Oleksij Rempel25e34b42015-10-12 21:15:33 +0200203 icoll_add_domain(np, ICOLL_NUM_IRQS);
Oleksij Rempele59a8452015-10-12 21:15:30 +0200204
205 return 0;
Shawn Guo83a84ef2012-08-20 21:34:56 +0800206}
Shawn Guo6a8e95b2013-03-25 21:34:51 +0800207IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200208
209static int __init asm9260_of_init(struct device_node *np,
210 struct device_node *interrupt_parent)
211{
212 void __iomem *icoll_base;
213 int i;
214
215 icoll_priv.type = ASM9260_ICOLL;
216
217 icoll_base = icoll_init_iobase(np);
218 icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
219 icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
220 icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
221 icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
222 icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
223 icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
224
225 writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
226 icoll_priv.ctrl);
227 /*
228 * ASM9260 don't provide reset bit. So, we need to set level 0
229 * manually.
230 */
231 for (i = 0; i < 16 * 0x10; i += 0x10)
232 writel(0, icoll_priv.intr + i);
233
234 icoll_add_domain(np, ASM9260_NUM_IRQS);
Oleksij Rempelc5b63522016-01-29 10:57:53 +0100235 set_handle_irq(icoll_handle_irq);
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200236
237 return 0;
238}
239IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);