Thomas Gleixner | 1621633 | 2019-05-19 15:51:31 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 4 | * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> |
| 5 | * Add Alphascale ASM9260 support. |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/kernel.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/irq.h> |
Joel Porquet | 41a83e06 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 11 | #include <linux/irqchip.h> |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 12 | #include <linux/irqdomain.h> |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 13 | #include <linux/io.h> |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 14 | #include <linux/of.h> |
Shawn Guo | 8256aa7 | 2013-03-25 21:13:22 +0800 | [diff] [blame] | 15 | #include <linux/of_address.h> |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 16 | #include <linux/of_irq.h> |
Shawn Guo | cec6bae | 2013-03-25 21:20:05 +0800 | [diff] [blame] | 17 | #include <linux/stmp_device.h> |
Shawn Guo | 4e0a1b8 | 2012-08-20 10:14:56 +0800 | [diff] [blame] | 18 | #include <asm/exception.h> |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 19 | |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 20 | #include "alphascale_asm9260-icoll.h" |
| 21 | |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 22 | /* |
| 23 | * this device provide 4 offsets for each register: |
| 24 | * 0x0 - plain read write mode |
| 25 | * 0x4 - set mode, OR logic. |
| 26 | * 0x8 - clr mode, XOR logic. |
| 27 | * 0xc - togle mode. |
| 28 | */ |
| 29 | #define SET_REG 4 |
| 30 | #define CLR_REG 8 |
| 31 | |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 32 | #define HW_ICOLL_VECTOR 0x0000 |
| 33 | #define HW_ICOLL_LEVELACK 0x0010 |
| 34 | #define HW_ICOLL_CTRL 0x0020 |
Shawn Guo | 4e0a1b8 | 2012-08-20 10:14:56 +0800 | [diff] [blame] | 35 | #define HW_ICOLL_STAT_OFFSET 0x0070 |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 36 | #define HW_ICOLL_INTERRUPT0 0x0120 |
| 37 | #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10) |
| 38 | #define BM_ICOLL_INTR_ENABLE BIT(2) |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 39 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 |
| 40 | |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 41 | #define ICOLL_NUM_IRQS 128 |
| 42 | |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 43 | enum icoll_type { |
| 44 | ICOLL, |
| 45 | ASM9260_ICOLL, |
| 46 | }; |
| 47 | |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 48 | struct icoll_priv { |
| 49 | void __iomem *vector; |
| 50 | void __iomem *levelack; |
| 51 | void __iomem *ctrl; |
| 52 | void __iomem *stat; |
| 53 | void __iomem *intr; |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 54 | void __iomem *clear; |
| 55 | enum icoll_type type; |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 56 | }; |
| 57 | |
| 58 | static struct icoll_priv icoll_priv; |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 59 | static struct irq_domain *icoll_domain; |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 60 | |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 61 | /* calculate bit offset depending on number of intterupt per register */ |
| 62 | static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) |
| 63 | { |
| 64 | /* |
| 65 | * mask lower part of hwirq to convert it |
| 66 | * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3) |
| 67 | */ |
| 68 | return bit << ((d->hwirq & 3) << 3); |
| 69 | } |
| 70 | |
| 71 | /* calculate mem offset depending on number of intterupt per register */ |
| 72 | static void __iomem *icoll_intr_reg(struct irq_data *d) |
| 73 | { |
| 74 | /* offset = hwirq / intr_per_reg * 0x10 */ |
| 75 | return icoll_priv.intr + ((d->hwirq >> 2) * 0x10); |
| 76 | } |
| 77 | |
Uwe Kleine-König | bf0c1118 | 2011-02-18 21:31:41 +0100 | [diff] [blame] | 78 | static void icoll_ack_irq(struct irq_data *d) |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 79 | { |
| 80 | /* |
| 81 | * The Interrupt Collector is able to prioritize irqs. |
| 82 | * Currently only level 0 is used. So acking can use |
| 83 | * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. |
| 84 | */ |
| 85 | __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 86 | icoll_priv.levelack); |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 87 | } |
| 88 | |
Uwe Kleine-König | bf0c1118 | 2011-02-18 21:31:41 +0100 | [diff] [blame] | 89 | static void icoll_mask_irq(struct irq_data *d) |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 90 | { |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 91 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
| 92 | icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 93 | } |
| 94 | |
Uwe Kleine-König | bf0c1118 | 2011-02-18 21:31:41 +0100 | [diff] [blame] | 95 | static void icoll_unmask_irq(struct irq_data *d) |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 96 | { |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 97 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
| 98 | icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 99 | } |
| 100 | |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 101 | static void asm9260_mask_irq(struct irq_data *d) |
| 102 | { |
| 103 | __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), |
| 104 | icoll_intr_reg(d) + CLR_REG); |
| 105 | } |
| 106 | |
| 107 | static void asm9260_unmask_irq(struct irq_data *d) |
| 108 | { |
| 109 | __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq), |
| 110 | icoll_priv.clear + |
| 111 | ASM9260_HW_ICOLL_CLEARn(d->hwirq)); |
| 112 | |
| 113 | __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), |
| 114 | icoll_intr_reg(d) + SET_REG); |
| 115 | } |
| 116 | |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 117 | static struct irq_chip mxs_icoll_chip = { |
Uwe Kleine-König | bf0c1118 | 2011-02-18 21:31:41 +0100 | [diff] [blame] | 118 | .irq_ack = icoll_ack_irq, |
| 119 | .irq_mask = icoll_mask_irq, |
| 120 | .irq_unmask = icoll_unmask_irq, |
Stefan Wahren | 88e20c7 | 2016-12-27 18:29:57 +0000 | [diff] [blame] | 121 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
| 122 | IRQCHIP_SKIP_SET_WAKE, |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 123 | }; |
| 124 | |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 125 | static struct irq_chip asm9260_icoll_chip = { |
| 126 | .irq_ack = icoll_ack_irq, |
| 127 | .irq_mask = asm9260_mask_irq, |
| 128 | .irq_unmask = asm9260_unmask_irq, |
Stefan Wahren | 88e20c7 | 2016-12-27 18:29:57 +0000 | [diff] [blame] | 129 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
| 130 | IRQCHIP_SKIP_SET_WAKE, |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 131 | }; |
| 132 | |
Shawn Guo | 4e0a1b8 | 2012-08-20 10:14:56 +0800 | [diff] [blame] | 133 | asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) |
| 134 | { |
| 135 | u32 irqnr; |
| 136 | |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 137 | irqnr = __raw_readl(icoll_priv.stat); |
| 138 | __raw_writel(irqnr, icoll_priv.vector); |
Marc Zyngier | b3410e5 | 2014-08-26 11:03:24 +0100 | [diff] [blame] | 139 | handle_domain_irq(icoll_domain, irqnr, regs); |
Shawn Guo | 4e0a1b8 | 2012-08-20 10:14:56 +0800 | [diff] [blame] | 140 | } |
| 141 | |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 142 | static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, |
| 143 | irq_hw_number_t hw) |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 144 | { |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 145 | struct irq_chip *chip; |
| 146 | |
| 147 | if (icoll_priv.type == ICOLL) |
| 148 | chip = &mxs_icoll_chip; |
| 149 | else |
| 150 | chip = &asm9260_icoll_chip; |
| 151 | |
| 152 | irq_set_chip_and_handler(virq, chip, handle_level_irq); |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 153 | |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 154 | return 0; |
| 155 | } |
| 156 | |
Krzysztof Kozlowski | 9600973 | 2015-04-27 21:54:24 +0900 | [diff] [blame] | 157 | static const struct irq_domain_ops icoll_irq_domain_ops = { |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 158 | .map = icoll_irq_domain_map, |
| 159 | .xlate = irq_domain_xlate_onecell, |
| 160 | }; |
| 161 | |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 162 | static void __init icoll_add_domain(struct device_node *np, |
| 163 | int num) |
| 164 | { |
| 165 | icoll_domain = irq_domain_add_linear(np, num, |
| 166 | &icoll_irq_domain_ops, NULL); |
| 167 | |
| 168 | if (!icoll_domain) |
Rob Herring | e81f54c | 2017-07-18 16:43:10 -0500 | [diff] [blame] | 169 | panic("%pOF: unable to create irq domain", np); |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | static void __iomem * __init icoll_init_iobase(struct device_node *np) |
| 173 | { |
| 174 | void __iomem *icoll_base; |
| 175 | |
| 176 | icoll_base = of_io_request_and_map(np, 0, np->name); |
Vladimir Zapolskiy | edf8fcd | 2016-03-09 03:21:40 +0200 | [diff] [blame] | 177 | if (IS_ERR(icoll_base)) |
Rob Herring | e81f54c | 2017-07-18 16:43:10 -0500 | [diff] [blame] | 178 | panic("%pOF: unable to map resource", np); |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 179 | return icoll_base; |
| 180 | } |
| 181 | |
Rob Herring | 10776b5 | 2014-05-12 11:37:07 -0500 | [diff] [blame] | 182 | static int __init icoll_of_init(struct device_node *np, |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 183 | struct device_node *interrupt_parent) |
| 184 | { |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 185 | void __iomem *icoll_base; |
| 186 | |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 187 | icoll_priv.type = ICOLL; |
| 188 | |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 189 | icoll_base = icoll_init_iobase(np); |
| 190 | icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR; |
| 191 | icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK; |
| 192 | icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL; |
| 193 | icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET; |
| 194 | icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 195 | icoll_priv.clear = NULL; |
Shawn Guo | 8256aa7 | 2013-03-25 21:13:22 +0800 | [diff] [blame] | 196 | |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 197 | /* |
| 198 | * Interrupt Collector reset, which initializes the priority |
| 199 | * for each irq to level 0. |
| 200 | */ |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 201 | stmp_reset_block(icoll_priv.ctrl); |
Shawn Guo | 289569f | 2010-12-18 21:39:28 +0800 | [diff] [blame] | 202 | |
Oleksij Rempel | 25e34b4 | 2015-10-12 21:15:33 +0200 | [diff] [blame] | 203 | icoll_add_domain(np, ICOLL_NUM_IRQS); |
Oleksij Rempel | e59a845 | 2015-10-12 21:15:30 +0200 | [diff] [blame] | 204 | |
| 205 | return 0; |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 206 | } |
Shawn Guo | 6a8e95b | 2013-03-25 21:34:51 +0800 | [diff] [blame] | 207 | IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 208 | |
| 209 | static int __init asm9260_of_init(struct device_node *np, |
| 210 | struct device_node *interrupt_parent) |
| 211 | { |
| 212 | void __iomem *icoll_base; |
| 213 | int i; |
| 214 | |
| 215 | icoll_priv.type = ASM9260_ICOLL; |
| 216 | |
| 217 | icoll_base = icoll_init_iobase(np); |
| 218 | icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR; |
| 219 | icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK; |
| 220 | icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL; |
| 221 | icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET; |
| 222 | icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0; |
| 223 | icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0; |
| 224 | |
| 225 | writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE, |
| 226 | icoll_priv.ctrl); |
| 227 | /* |
| 228 | * ASM9260 don't provide reset bit. So, we need to set level 0 |
| 229 | * manually. |
| 230 | */ |
| 231 | for (i = 0; i < 16 * 0x10; i += 0x10) |
| 232 | writel(0, icoll_priv.intr + i); |
| 233 | |
| 234 | icoll_add_domain(np, ASM9260_NUM_IRQS); |
Oleksij Rempel | c5b6352 | 2016-01-29 10:57:53 +0100 | [diff] [blame] | 235 | set_handle_irq(icoll_handle_irq); |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 236 | |
| 237 | return 0; |
| 238 | } |
| 239 | IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init); |