Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 1 | menu "Kernel hacking" |
| 2 | |
| 3 | source "lib/Kconfig.debug" |
| 4 | |
Laura Abbott | c9465b4 | 2014-11-26 00:28:39 +0000 | [diff] [blame] | 5 | config ARM64_PTDUMP |
| 6 | bool "Export kernel pagetable layout to userspace via debugfs" |
| 7 | depends on DEBUG_KERNEL |
| 8 | select DEBUG_FS |
| 9 | help |
| 10 | Say Y here if you want to show the kernel pagetable layout in a |
| 11 | debugfs file. This information is only useful for kernel developers |
| 12 | who are working in architecture specific areas of the kernel. |
| 13 | It is probably not a good idea to enable this feature in a production |
| 14 | kernel. |
| 15 | If in doubt, say "N" |
| 16 | |
Will Deacon | ec45d1c | 2013-01-17 12:31:45 +0000 | [diff] [blame] | 17 | config PID_IN_CONTEXTIDR |
| 18 | bool "Write the current PID to the CONTEXTIDR register" |
| 19 | help |
| 20 | Enabling this option causes the kernel to write the current PID to |
| 21 | the CONTEXTIDR register, at the expense of some additional |
| 22 | instructions during context switch. Say Y here only if you are |
| 23 | planning to use hardware trace tools with this kernel. |
| 24 | |
Mark Rutland | da57a36 | 2014-06-24 16:51:37 +0100 | [diff] [blame] | 25 | config ARM64_RANDOMIZE_TEXT_OFFSET |
| 26 | bool "Randomize TEXT_OFFSET at build time" |
| 27 | help |
| 28 | Say Y here if you want the image load offset (AKA TEXT_OFFSET) |
| 29 | of the kernel to be randomized at build-time. When selected, |
| 30 | this option will cause TEXT_OFFSET to be randomized upon any |
| 31 | build of the kernel, and the offset will be reflected in the |
| 32 | text_offset field of the resulting Image. This can be used to |
| 33 | fuzz-test bootloaders which respect text_offset. |
| 34 | |
| 35 | This option is intended for bootloader and/or kernel testing |
| 36 | only. Bootloaders must make no assumptions regarding the value |
| 37 | of TEXT_OFFSET and platforms must not require a specific |
| 38 | value. |
| 39 | |
Laura Abbott | 11d91a7 | 2014-08-19 20:41:43 +0100 | [diff] [blame] | 40 | config DEBUG_SET_MODULE_RONX |
| 41 | bool "Set loadable kernel module data as NX and text as RO" |
| 42 | depends on MODULES |
| 43 | help |
| 44 | This option helps catch unintended modifications to loadable |
| 45 | kernel module's text and read-only data. It also prevents execution |
| 46 | of module data. Such protection may interfere with run-time code |
| 47 | patching and dynamic kernel tracing - and they might also protect |
| 48 | against certain classes of kernel exploits. |
| 49 | If in doubt, say "N". |
| 50 | |
Laura Abbott | da14170 | 2015-01-21 17:36:06 -0800 | [diff] [blame] | 51 | config DEBUG_RODATA |
| 52 | bool "Make kernel text and rodata read-only" |
| 53 | help |
| 54 | If this is set, kernel text and rodata will be made read-only. This |
| 55 | is to help catch accidental or malicious attempts to change the |
| 56 | kernel's executable code. Additionally splits rodata from kernel |
| 57 | text so it can be made explicitly non-executable. |
| 58 | |
| 59 | If in doubt, say Y |
| 60 | |
| 61 | config DEBUG_ALIGN_RODATA |
Suzuki K. Poulose | 755e70b | 2015-10-19 14:19:32 +0100 | [diff] [blame] | 62 | depends on DEBUG_RODATA && ARM64_4K_PAGES |
Laura Abbott | da14170 | 2015-01-21 17:36:06 -0800 | [diff] [blame] | 63 | bool "Align linker sections up to SECTION_SIZE" |
| 64 | help |
| 65 | If this option is enabled, sections that may potentially be marked as |
| 66 | read only or non-executable will be aligned up to the section size of |
| 67 | the kernel. This prevents sections from being split into pages and |
| 68 | avoids a potential TLB penalty. The downside is an increase in |
| 69 | alignment and potentially wasted space. Turn on this option if |
| 70 | performance is more important than memory pressure. |
| 71 | |
| 72 | If in doubt, say N |
| 73 | |
Mathieu Poirier | 01081f5 | 2015-03-30 14:13:41 -0600 | [diff] [blame] | 74 | source "drivers/hwtracing/coresight/Kconfig" |
Mathieu Poirier | 3288731 | 2015-03-30 14:13:36 -0600 | [diff] [blame] | 75 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 76 | endmenu |