Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3 Power Management Routines |
| 3 | * |
| 4 | * Copyright (C) 2006-2008 Nokia Corporation |
| 5 | * Tony Lindgren <tony@atomide.com> |
| 6 | * Jouni Hogander |
| 7 | * |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 8 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 9 | * Rajendra Nayak <rnayak@ti.com> |
| 10 | * |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 11 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 12 | * Richard Woodruff <r-woodruff2@ti.com> |
| 13 | * |
| 14 | * Based on pm.c for omap1 |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/pm.h> |
| 22 | #include <linux/suspend.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/list.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/gpio.h> |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 28 | #include <linux/clk.h> |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 29 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 31 | #include <linux/console.h> |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 32 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 33 | #include <plat/sram.h> |
| 34 | #include <plat/clockdomain.h> |
| 35 | #include <plat/powerdomain.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 36 | #include <plat/serial.h> |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 37 | #include <plat/sdrc.h> |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 38 | #include <plat/prcm.h> |
| 39 | #include <plat/gpmc.h> |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 40 | #include <plat/dma.h> |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 41 | |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 42 | #include <asm/tlbflush.h> |
| 43 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame^] | 44 | #include "cm2xxx_3xxx.h" |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 45 | #include "cm-regbits-34xx.h" |
| 46 | #include "prm-regbits-34xx.h" |
| 47 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame^] | 48 | #include "prm2xxx_3xxx.h" |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 49 | #include "pm.h" |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 50 | #include "sdrc.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 51 | #include "control.h" |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 52 | |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 53 | #ifdef CONFIG_SUSPEND |
| 54 | static suspend_state_t suspend_state = PM_SUSPEND_ON; |
| 55 | static inline bool is_suspending(void) |
| 56 | { |
| 57 | return (suspend_state != PM_SUSPEND_ON); |
| 58 | } |
| 59 | #else |
| 60 | static inline bool is_suspending(void) |
| 61 | { |
| 62 | return false; |
| 63 | } |
| 64 | #endif |
| 65 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 66 | /* Scratchpad offsets */ |
Kevin Hilman | de65815 | 2010-10-08 22:43:45 +0000 | [diff] [blame] | 67 | #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 |
| 68 | #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 |
| 69 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 70 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 71 | /* pm34xx errata defined in pm.h */ |
| 72 | u16 pm34xx_errata; |
| 73 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 74 | struct power_state { |
| 75 | struct powerdomain *pwrdm; |
| 76 | u32 next_state; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 77 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 78 | u32 saved_state; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 79 | #endif |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 80 | struct list_head node; |
| 81 | }; |
| 82 | |
| 83 | static LIST_HEAD(pwrst_list); |
| 84 | |
| 85 | static void (*_omap_sram_idle)(u32 *addr, int save_state); |
| 86 | |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 87 | static int (*_omap_save_secure_sram)(u32 *addr); |
| 88 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 89 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
| 90 | static struct powerdomain *core_pwrdm, *per_pwrdm; |
Tero Kristo | c16c3f6 | 2008-12-11 16:46:57 +0200 | [diff] [blame] | 91 | static struct powerdomain *cam_pwrdm; |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 92 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 93 | static inline void omap3_per_save_context(void) |
| 94 | { |
| 95 | omap_gpio_save_context(); |
| 96 | } |
| 97 | |
| 98 | static inline void omap3_per_restore_context(void) |
| 99 | { |
| 100 | omap_gpio_restore_context(); |
| 101 | } |
| 102 | |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 103 | static void omap3_enable_io_chain(void) |
| 104 | { |
| 105 | int timeout = 0; |
| 106 | |
| 107 | if (omap_rev() >= OMAP3430_REV_ES3_1) { |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 108 | prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
| 109 | PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 110 | /* Do a readback to assure write has been done */ |
| 111 | prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
| 112 | |
Kevin Hilman | 0b96a3a | 2010-06-09 13:53:09 +0300 | [diff] [blame] | 113 | while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 114 | OMAP3430_ST_IO_CHAIN_MASK)) { |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 115 | timeout++; |
| 116 | if (timeout > 1000) { |
| 117 | printk(KERN_ERR "Wake up daisy chain " |
| 118 | "activation failed.\n"); |
| 119 | return; |
| 120 | } |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 121 | prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
Kevin Hilman | 0b96a3a | 2010-06-09 13:53:09 +0300 | [diff] [blame] | 122 | WKUP_MOD, PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 123 | } |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | static void omap3_disable_io_chain(void) |
| 128 | { |
| 129 | if (omap_rev() >= OMAP3430_REV_ES3_1) |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 130 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
| 131 | PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 132 | } |
| 133 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 134 | static void omap3_core_save_context(void) |
| 135 | { |
| 136 | u32 control_padconf_off; |
| 137 | |
| 138 | /* Save the padconf registers */ |
| 139 | control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); |
| 140 | control_padconf_off |= START_PADCONF_SAVE; |
| 141 | omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); |
| 142 | /* wait for the save to complete */ |
Roel Kluin | 1b6e821 | 2010-01-08 10:29:07 -0800 | [diff] [blame] | 143 | while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) |
| 144 | & PADCONF_SAVE_DONE)) |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 145 | udelay(1); |
| 146 | |
| 147 | /* |
| 148 | * Force write last pad into memory, as this can fail in some |
Jean Pihet | 8352129 | 2010-12-18 16:44:46 +0100 | [diff] [blame] | 149 | * cases according to errata 1.157, 1.185 |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 150 | */ |
| 151 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), |
| 152 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); |
| 153 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 154 | /* Save the Interrupt controller context */ |
| 155 | omap_intc_save_context(); |
| 156 | /* Save the GPMC context */ |
| 157 | omap3_gpmc_save_context(); |
| 158 | /* Save the system control module context, padconf already save above*/ |
| 159 | omap3_control_save_context(); |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 160 | omap_dma_global_context_save(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | static void omap3_core_restore_context(void) |
| 164 | { |
| 165 | /* Restore the control module context, padconf restored by h/w */ |
| 166 | omap3_control_restore_context(); |
| 167 | /* Restore the GPMC context */ |
| 168 | omap3_gpmc_restore_context(); |
| 169 | /* Restore the interrupt controller context */ |
| 170 | omap_intc_restore_context(); |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 171 | omap_dma_global_context_restore(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 172 | } |
| 173 | |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 174 | /* |
| 175 | * FIXME: This function should be called before entering off-mode after |
| 176 | * OMAP3 secure services have been accessed. Currently it is only called |
| 177 | * once during boot sequence, but this works as we are not using secure |
| 178 | * services. |
| 179 | */ |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 180 | static void omap3_save_secure_ram_context(u32 target_mpu_state) |
| 181 | { |
| 182 | u32 ret; |
| 183 | |
| 184 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 185 | /* |
| 186 | * MPU next state must be set to POWER_ON temporarily, |
| 187 | * otherwise the WFI executed inside the ROM code |
| 188 | * will hang the system. |
| 189 | */ |
| 190 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
| 191 | ret = _omap_save_secure_sram((u32 *) |
| 192 | __pa(omap3_secure_ram_storage)); |
| 193 | pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); |
| 194 | /* Following is for error tracking, it should not happen */ |
| 195 | if (ret) { |
| 196 | printk(KERN_ERR "save_secure_sram() returns %08x\n", |
| 197 | ret); |
| 198 | while (1) |
| 199 | ; |
| 200 | } |
| 201 | } |
| 202 | } |
| 203 | |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 204 | /* |
| 205 | * PRCM Interrupt Handler Helper Function |
| 206 | * |
| 207 | * The purpose of this function is to clear any wake-up events latched |
| 208 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event |
| 209 | * may occur whilst attempting to clear a PM_WKST_x register and thus |
| 210 | * set another bit in this register. A while loop is used to ensure |
| 211 | * that any peripheral wake-up events occurring while attempting to |
| 212 | * clear the PM_WKST_x are detected and cleared. |
| 213 | */ |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 214 | static int prcm_clear_mod_irqs(s16 module, u8 regs) |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 215 | { |
Vikram Pandita | 71a8077 | 2009-07-17 19:33:09 -0500 | [diff] [blame] | 216 | u32 wkst, fclk, iclk, clken; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 217 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
| 218 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; |
| 219 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; |
Paul Walmsley | 5d80597 | 2009-07-22 10:18:07 -0700 | [diff] [blame] | 220 | u16 grpsel_off = (regs == 3) ? |
| 221 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 222 | int c = 0; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 223 | |
| 224 | wkst = prm_read_mod_reg(module, wkst_off); |
Paul Walmsley | 5d80597 | 2009-07-22 10:18:07 -0700 | [diff] [blame] | 225 | wkst &= prm_read_mod_reg(module, grpsel_off); |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 226 | if (wkst) { |
| 227 | iclk = cm_read_mod_reg(module, iclk_off); |
| 228 | fclk = cm_read_mod_reg(module, fclk_off); |
| 229 | while (wkst) { |
Vikram Pandita | 71a8077 | 2009-07-17 19:33:09 -0500 | [diff] [blame] | 230 | clken = wkst; |
| 231 | cm_set_mod_reg_bits(clken, module, iclk_off); |
| 232 | /* |
| 233 | * For USBHOST, we don't know whether HOST1 or |
| 234 | * HOST2 woke us up, so enable both f-clocks |
| 235 | */ |
| 236 | if (module == OMAP3430ES2_USBHOST_MOD) |
| 237 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; |
| 238 | cm_set_mod_reg_bits(clken, module, fclk_off); |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 239 | prm_write_mod_reg(wkst, module, wkst_off); |
| 240 | wkst = prm_read_mod_reg(module, wkst_off); |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 241 | c++; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 242 | } |
| 243 | cm_write_mod_reg(iclk, module, iclk_off); |
| 244 | cm_write_mod_reg(fclk, module, fclk_off); |
| 245 | } |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 246 | |
| 247 | return c; |
| 248 | } |
| 249 | |
| 250 | static int _prcm_int_handle_wakeup(void) |
| 251 | { |
| 252 | int c; |
| 253 | |
| 254 | c = prcm_clear_mod_irqs(WKUP_MOD, 1); |
| 255 | c += prcm_clear_mod_irqs(CORE_MOD, 1); |
| 256 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); |
| 257 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 258 | c += prcm_clear_mod_irqs(CORE_MOD, 3); |
| 259 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); |
| 260 | } |
| 261 | |
| 262 | return c; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | /* |
| 266 | * PRCM Interrupt Handler |
| 267 | * |
| 268 | * The PRM_IRQSTATUS_MPU register indicates if there are any pending |
| 269 | * interrupts from the PRCM for the MPU. These bits must be cleared in |
| 270 | * order to clear the PRCM interrupt. The PRCM interrupt handler is |
| 271 | * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear |
| 272 | * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU |
| 273 | * register indicates that a wake-up event is pending for the MPU and |
| 274 | * this bit can only be cleared if the all the wake-up events latched |
| 275 | * in the various PM_WKST_x registers have been cleared. The interrupt |
| 276 | * handler is implemented using a do-while loop so that if a wake-up |
| 277 | * event occurred during the processing of the prcm interrupt handler |
| 278 | * (setting a bit in the corresponding PM_WKST_x register and thus |
| 279 | * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) |
| 280 | * this would be handled. |
| 281 | */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 282 | static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) |
| 283 | { |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 284 | u32 irqenable_mpu, irqstatus_mpu; |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 285 | int c = 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 286 | |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 287 | irqenable_mpu = prm_read_mod_reg(OCP_MOD, |
| 288 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 289 | irqstatus_mpu = prm_read_mod_reg(OCP_MOD, |
| 290 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 291 | irqstatus_mpu &= irqenable_mpu; |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 292 | |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 293 | do { |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 294 | if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | |
| 295 | OMAP3430_IO_ST_MASK)) { |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 296 | c = _prcm_int_handle_wakeup(); |
| 297 | |
| 298 | /* |
| 299 | * Is the MPU PRCM interrupt handler racing with the |
| 300 | * IVA2 PRCM interrupt handler ? |
| 301 | */ |
| 302 | WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " |
| 303 | "but no wakeup sources are marked\n"); |
| 304 | } else { |
| 305 | /* XXX we need to expand our PRCM interrupt handler */ |
| 306 | WARN(1, "prcm: WARNING: PRCM interrupt received, but " |
| 307 | "no code to handle it (%08x)\n", irqstatus_mpu); |
| 308 | } |
| 309 | |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 310 | prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
| 311 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 312 | |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 313 | irqstatus_mpu = prm_read_mod_reg(OCP_MOD, |
| 314 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 315 | irqstatus_mpu &= irqenable_mpu; |
| 316 | |
| 317 | } while (irqstatus_mpu); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 318 | |
| 319 | return IRQ_HANDLED; |
| 320 | } |
| 321 | |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 322 | static void restore_control_register(u32 val) |
| 323 | { |
| 324 | __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); |
| 325 | } |
| 326 | |
| 327 | /* Function to restore the table entry that was modified for enabling MMU */ |
| 328 | static void restore_table_entry(void) |
| 329 | { |
Manjunath Kondaiah G | 4d63bc1 | 2010-10-08 09:56:11 -0700 | [diff] [blame] | 330 | void __iomem *scratchpad_address; |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 331 | u32 previous_value, control_reg_value; |
| 332 | u32 *address; |
| 333 | |
| 334 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); |
| 335 | |
| 336 | /* Get address of entry that was modified */ |
| 337 | address = (u32 *)__raw_readl(scratchpad_address + |
| 338 | OMAP343X_TABLE_ADDRESS_OFFSET); |
| 339 | /* Get the previous value which needs to be restored */ |
| 340 | previous_value = __raw_readl(scratchpad_address + |
| 341 | OMAP343X_TABLE_VALUE_OFFSET); |
| 342 | address = __va(address); |
| 343 | *address = previous_value; |
| 344 | flush_tlb_all(); |
| 345 | control_reg_value = __raw_readl(scratchpad_address |
| 346 | + OMAP343X_CONTROL_REG_VALUE_OFFSET); |
| 347 | /* This will enable caches and prediction */ |
| 348 | restore_control_register(control_reg_value); |
| 349 | } |
| 350 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 351 | void omap_sram_idle(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 352 | { |
| 353 | /* Variable to tell what needs to be saved and restored |
| 354 | * in omap_sram_idle*/ |
| 355 | /* save_state = 0 => Nothing to save and restored */ |
| 356 | /* save_state = 1 => Only L1 and logic lost */ |
| 357 | /* save_state = 2 => Only L2 lost */ |
| 358 | /* save_state = 3 => L1, L2 and logic lost */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 359 | int save_state = 0; |
| 360 | int mpu_next_state = PWRDM_POWER_ON; |
| 361 | int per_next_state = PWRDM_POWER_ON; |
| 362 | int core_next_state = PWRDM_POWER_ON; |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 363 | int core_prev_state, per_prev_state; |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 364 | u32 sdrc_pwr = 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 365 | |
| 366 | if (!_omap_sram_idle) |
| 367 | return; |
| 368 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 369 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
| 370 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); |
| 371 | pwrdm_clear_all_prev_pwrst(core_pwrdm); |
| 372 | pwrdm_clear_all_prev_pwrst(per_pwrdm); |
| 373 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 374 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
| 375 | switch (mpu_next_state) { |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 376 | case PWRDM_POWER_ON: |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 377 | case PWRDM_POWER_RET: |
| 378 | /* No need to save context */ |
| 379 | save_state = 0; |
| 380 | break; |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 381 | case PWRDM_POWER_OFF: |
| 382 | save_state = 3; |
| 383 | break; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 384 | default: |
| 385 | /* Invalid state */ |
| 386 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); |
| 387 | return; |
| 388 | } |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 389 | pwrdm_pre_transition(); |
| 390 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 391 | /* NEON control */ |
| 392 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) |
Jouni Hogander | 7139178 | 2008-10-28 10:59:05 +0200 | [diff] [blame] | 393 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 394 | |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 395 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 396 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 397 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
Kevin Hilman | d5c47d7 | 2010-08-10 16:04:35 -0700 | [diff] [blame] | 398 | if (omap3_has_io_wakeup() && |
| 399 | (per_next_state < PWRDM_POWER_ON || |
| 400 | core_next_state < PWRDM_POWER_ON)) { |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 401 | prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 402 | omap3_enable_io_chain(); |
| 403 | } |
| 404 | |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 405 | /* Block console output in case it is on one of the OMAP UARTs */ |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 406 | if (!is_suspending()) |
| 407 | if (per_next_state < PWRDM_POWER_ON || |
| 408 | core_next_state < PWRDM_POWER_ON) |
| 409 | if (try_acquire_console_sem()) |
| 410 | goto console_still_active; |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 411 | |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 412 | /* PER */ |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 413 | if (per_next_state < PWRDM_POWER_ON) { |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 414 | omap_uart_prepare_idle(2); |
Govindraj.R | cd4f1fa | 2010-09-27 20:20:32 +0530 | [diff] [blame] | 415 | omap_uart_prepare_idle(3); |
Kevin Hilman | 43ffcd9 | 2009-01-27 11:09:24 -0800 | [diff] [blame] | 416 | omap2_gpio_prepare_for_idle(per_next_state); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 417 | if (per_next_state == PWRDM_POWER_OFF) |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 418 | omap3_per_save_context(); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | /* CORE */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 422 | if (core_next_state < PWRDM_POWER_ON) { |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 423 | omap_uart_prepare_idle(0); |
| 424 | omap_uart_prepare_idle(1); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 425 | if (core_next_state == PWRDM_POWER_OFF) { |
| 426 | omap3_core_save_context(); |
| 427 | omap3_prcm_save_context(); |
| 428 | } |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 429 | } |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 430 | |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 431 | omap3_intc_prepare_idle(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 432 | |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 433 | /* |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 434 | * On EMU/HS devices ROM code restores a SRDC value |
| 435 | * from scratchpad which has automatic self refresh on timeout |
Jean Pihet | 8352129 | 2010-12-18 16:44:46 +0100 | [diff] [blame] | 436 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 437 | * Hence store/restore the SDRC_POWER register here. |
| 438 | */ |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 439 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
| 440 | omap_type() != OMAP2_DEVICE_TYPE_GP && |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 441 | core_next_state == PWRDM_POWER_OFF) |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 442 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 443 | |
| 444 | /* |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 445 | * omap3_arm_context is the location where ARM registers |
| 446 | * get saved. The restore path then reads from this |
| 447 | * location and restores them back. |
| 448 | */ |
| 449 | _omap_sram_idle(omap3_arm_context, save_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 450 | cpu_init(); |
| 451 | |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 452 | /* Restore normal SDRC POWER settings */ |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 453 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
| 454 | omap_type() != OMAP2_DEVICE_TYPE_GP && |
| 455 | core_next_state == PWRDM_POWER_OFF) |
| 456 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); |
| 457 | |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 458 | /* Restore table entry modified during MMU restoration */ |
| 459 | if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) |
| 460 | restore_table_entry(); |
| 461 | |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 462 | /* CORE */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 463 | if (core_next_state < PWRDM_POWER_ON) { |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 464 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
| 465 | if (core_prev_state == PWRDM_POWER_OFF) { |
| 466 | omap3_core_restore_context(); |
| 467 | omap3_prcm_restore_context(); |
| 468 | omap3_sram_restore_context(); |
Kalle Jokiniemi | 8a917d2 | 2009-05-13 13:32:11 +0300 | [diff] [blame] | 469 | omap2_sms_restore_context(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 470 | } |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 471 | omap_uart_resume_idle(0); |
| 472 | omap_uart_resume_idle(1); |
| 473 | if (core_next_state == PWRDM_POWER_OFF) |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 474 | prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 475 | OMAP3430_GR_MOD, |
| 476 | OMAP3_PRM_VOLTCTRL_OFFSET); |
| 477 | } |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 478 | omap3_intc_resume_idle(); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 479 | |
| 480 | /* PER */ |
| 481 | if (per_next_state < PWRDM_POWER_ON) { |
| 482 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); |
Kevin Hilman | 43ffcd9 | 2009-01-27 11:09:24 -0800 | [diff] [blame] | 483 | omap2_gpio_resume_after_idle(); |
| 484 | if (per_prev_state == PWRDM_POWER_OFF) |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 485 | omap3_per_restore_context(); |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 486 | omap_uart_resume_idle(2); |
Govindraj.R | cd4f1fa | 2010-09-27 20:20:32 +0530 | [diff] [blame] | 487 | omap_uart_resume_idle(3); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 488 | } |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 489 | |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 490 | if (!is_suspending()) |
| 491 | release_console_sem(); |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 492 | |
| 493 | console_still_active: |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 494 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
Kevin Hilman | 58a5559 | 2010-08-16 09:21:19 +0300 | [diff] [blame] | 495 | if (omap3_has_io_wakeup() && |
| 496 | (per_next_state < PWRDM_POWER_ON || |
| 497 | core_next_state < PWRDM_POWER_ON)) { |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 498 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 499 | omap3_disable_io_chain(); |
| 500 | } |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 501 | |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 502 | pwrdm_post_transition(); |
| 503 | |
Tero Kristo | c16c3f6 | 2008-12-11 16:46:57 +0200 | [diff] [blame] | 504 | omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 505 | } |
| 506 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 507 | int omap3_can_sleep(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 508 | { |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 509 | if (!sleep_while_idle) |
| 510 | return 0; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 511 | if (!omap_uart_can_sleep()) |
| 512 | return 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 513 | return 1; |
| 514 | } |
| 515 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 516 | static void omap3_pm_idle(void) |
| 517 | { |
| 518 | local_irq_disable(); |
| 519 | local_fiq_disable(); |
| 520 | |
| 521 | if (!omap3_can_sleep()) |
| 522 | goto out; |
| 523 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 524 | if (omap_irq_pending() || need_resched()) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 525 | goto out; |
| 526 | |
| 527 | omap_sram_idle(); |
| 528 | |
| 529 | out: |
| 530 | local_fiq_enable(); |
| 531 | local_irq_enable(); |
| 532 | } |
| 533 | |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 534 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 535 | static int omap3_pm_suspend(void) |
| 536 | { |
| 537 | struct power_state *pwrst; |
| 538 | int state, ret = 0; |
| 539 | |
Ari Kauppi | 8e2efde | 2010-03-23 09:04:59 +0200 | [diff] [blame] | 540 | if (wakeup_timer_seconds || wakeup_timer_milliseconds) |
| 541 | omap2_pm_wakeup_on_timer(wakeup_timer_seconds, |
| 542 | wakeup_timer_milliseconds); |
Kevin Hilman | d7814e4 | 2009-10-06 14:30:23 -0700 | [diff] [blame] | 543 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 544 | /* Read current next_pwrsts */ |
| 545 | list_for_each_entry(pwrst, &pwrst_list, node) |
| 546 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
| 547 | /* Set ones wanted by suspend */ |
| 548 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 549 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 550 | goto restore; |
| 551 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) |
| 552 | goto restore; |
| 553 | } |
| 554 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 555 | omap_uart_prepare_suspend(); |
Tero Kristo | 2bbe3af | 2009-10-23 19:03:48 +0300 | [diff] [blame] | 556 | omap3_intc_suspend(); |
| 557 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 558 | omap_sram_idle(); |
| 559 | |
| 560 | restore: |
| 561 | /* Restore next_pwrsts */ |
| 562 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 563 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
| 564 | if (state > pwrst->next_state) { |
| 565 | printk(KERN_INFO "Powerdomain (%s) didn't enter " |
| 566 | "target state %d\n", |
| 567 | pwrst->pwrdm->name, pwrst->next_state); |
| 568 | ret = -1; |
| 569 | } |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 570 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 571 | } |
| 572 | if (ret) |
| 573 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); |
| 574 | else |
| 575 | printk(KERN_INFO "Successfully put all powerdomains " |
| 576 | "to target state\n"); |
| 577 | |
| 578 | return ret; |
| 579 | } |
| 580 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 581 | static int omap3_pm_enter(suspend_state_t unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 582 | { |
| 583 | int ret = 0; |
| 584 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 585 | switch (suspend_state) { |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 586 | case PM_SUSPEND_STANDBY: |
| 587 | case PM_SUSPEND_MEM: |
| 588 | ret = omap3_pm_suspend(); |
| 589 | break; |
| 590 | default: |
| 591 | ret = -EINVAL; |
| 592 | } |
| 593 | |
| 594 | return ret; |
| 595 | } |
| 596 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 597 | /* Hooks to enable / disable UART interrupts during suspend */ |
| 598 | static int omap3_pm_begin(suspend_state_t state) |
| 599 | { |
Jean Pihet | c166381 | 2010-12-09 18:39:58 +0100 | [diff] [blame] | 600 | disable_hlt(); |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 601 | suspend_state = state; |
| 602 | omap_uart_enable_irqs(0); |
| 603 | return 0; |
| 604 | } |
| 605 | |
| 606 | static void omap3_pm_end(void) |
| 607 | { |
| 608 | suspend_state = PM_SUSPEND_ON; |
| 609 | omap_uart_enable_irqs(1); |
Jean Pihet | c166381 | 2010-12-09 18:39:58 +0100 | [diff] [blame] | 610 | enable_hlt(); |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 611 | return; |
| 612 | } |
| 613 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 614 | static struct platform_suspend_ops omap_pm_ops = { |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 615 | .begin = omap3_pm_begin, |
| 616 | .end = omap3_pm_end, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 617 | .enter = omap3_pm_enter, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 618 | .valid = suspend_valid_only_mem, |
| 619 | }; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 620 | #endif /* CONFIG_SUSPEND */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 621 | |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 622 | |
| 623 | /** |
| 624 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into |
| 625 | * retention |
| 626 | * |
| 627 | * In cases where IVA2 is activated by bootcode, it may prevent |
| 628 | * full-chip retention or off-mode because it is not idle. This |
| 629 | * function forces the IVA2 into idle state so it can go |
| 630 | * into retention/off and thus allow full-chip retention/off. |
| 631 | * |
| 632 | **/ |
| 633 | static void __init omap3_iva_idle(void) |
| 634 | { |
| 635 | /* ensure IVA2 clock is disabled */ |
| 636 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 637 | |
| 638 | /* if no clock activity, nothing else to do */ |
| 639 | if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
| 640 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
| 641 | return; |
| 642 | |
| 643 | /* Reset IVA2 */ |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 644 | prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
| 645 | OMAP3430_RST2_IVA2_MASK | |
| 646 | OMAP3430_RST3_IVA2_MASK, |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 647 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 648 | |
| 649 | /* Enable IVA2 clock */ |
Kevin Hilman | dfa6d6f | 2010-02-24 12:05:48 -0700 | [diff] [blame] | 650 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 651 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 652 | |
| 653 | /* Set IVA2 boot mode to 'idle' */ |
| 654 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, |
| 655 | OMAP343X_CONTROL_IVA2_BOOTMOD); |
| 656 | |
| 657 | /* Un-reset IVA2 */ |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 658 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 659 | |
| 660 | /* Disable IVA2 clock */ |
| 661 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 662 | |
| 663 | /* Reset IVA2 */ |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 664 | prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
| 665 | OMAP3430_RST2_IVA2_MASK | |
| 666 | OMAP3430_RST3_IVA2_MASK, |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 667 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 668 | } |
| 669 | |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 670 | static void __init omap3_d2d_idle(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 671 | { |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 672 | u16 mask, padconf; |
| 673 | |
| 674 | /* In a stand alone OMAP3430 where there is not a stacked |
| 675 | * modem for the D2D Idle Ack and D2D MStandby must be pulled |
| 676 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and |
| 677 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ |
| 678 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ |
| 679 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); |
| 680 | padconf |= mask; |
| 681 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); |
| 682 | |
| 683 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); |
| 684 | padconf |= mask; |
| 685 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); |
| 686 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 687 | /* reset modem */ |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 688 | prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
| 689 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 690 | CORE_MOD, OMAP2_RM_RSTCTRL); |
| 691 | prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 692 | } |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 693 | |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 694 | static void __init prcm_setup_regs(void) |
| 695 | { |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 696 | u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? |
| 697 | OMAP3630_AUTO_UART4_MASK : 0; |
| 698 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
| 699 | OMAP3630_EN_UART4_MASK : 0; |
| 700 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? |
| 701 | OMAP3630_GRPSEL_UART4_MASK : 0; |
| 702 | |
| 703 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 704 | /* XXX Reset all wkdeps. This should be done when initializing |
| 705 | * powerdomains */ |
| 706 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); |
| 707 | prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); |
| 708 | prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); |
| 709 | prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); |
| 710 | prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); |
| 711 | prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); |
| 712 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 713 | prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); |
| 714 | prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); |
| 715 | } else |
| 716 | prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); |
| 717 | |
| 718 | /* |
| 719 | * Enable interface clock autoidle for all modules. |
| 720 | * Note that in the long run this should be done by clockfw |
| 721 | */ |
| 722 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 723 | OMAP3430_AUTO_MODEM_MASK | |
| 724 | OMAP3430ES2_AUTO_MMC3_MASK | |
| 725 | OMAP3430ES2_AUTO_ICR_MASK | |
| 726 | OMAP3430_AUTO_AES2_MASK | |
| 727 | OMAP3430_AUTO_SHA12_MASK | |
| 728 | OMAP3430_AUTO_DES2_MASK | |
| 729 | OMAP3430_AUTO_MMC2_MASK | |
| 730 | OMAP3430_AUTO_MMC1_MASK | |
| 731 | OMAP3430_AUTO_MSPRO_MASK | |
| 732 | OMAP3430_AUTO_HDQ_MASK | |
| 733 | OMAP3430_AUTO_MCSPI4_MASK | |
| 734 | OMAP3430_AUTO_MCSPI3_MASK | |
| 735 | OMAP3430_AUTO_MCSPI2_MASK | |
| 736 | OMAP3430_AUTO_MCSPI1_MASK | |
| 737 | OMAP3430_AUTO_I2C3_MASK | |
| 738 | OMAP3430_AUTO_I2C2_MASK | |
| 739 | OMAP3430_AUTO_I2C1_MASK | |
| 740 | OMAP3430_AUTO_UART2_MASK | |
| 741 | OMAP3430_AUTO_UART1_MASK | |
| 742 | OMAP3430_AUTO_GPT11_MASK | |
| 743 | OMAP3430_AUTO_GPT10_MASK | |
| 744 | OMAP3430_AUTO_MCBSP5_MASK | |
| 745 | OMAP3430_AUTO_MCBSP1_MASK | |
| 746 | OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ |
| 747 | OMAP3430_AUTO_MAILBOXES_MASK | |
| 748 | OMAP3430_AUTO_OMAPCTRL_MASK | |
| 749 | OMAP3430ES1_AUTO_FSHOSTUSB_MASK | |
| 750 | OMAP3430_AUTO_HSOTGUSB_MASK | |
| 751 | OMAP3430_AUTO_SAD2D_MASK | |
| 752 | OMAP3430_AUTO_SSI_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 753 | CORE_MOD, CM_AUTOIDLE1); |
| 754 | |
| 755 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 756 | OMAP3430_AUTO_PKA_MASK | |
| 757 | OMAP3430_AUTO_AES1_MASK | |
| 758 | OMAP3430_AUTO_RNG_MASK | |
| 759 | OMAP3430_AUTO_SHA11_MASK | |
| 760 | OMAP3430_AUTO_DES1_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 761 | CORE_MOD, CM_AUTOIDLE2); |
| 762 | |
| 763 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 764 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 765 | OMAP3430_AUTO_MAD2D_MASK | |
| 766 | OMAP3430ES2_AUTO_USBTLL_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 767 | CORE_MOD, CM_AUTOIDLE3); |
| 768 | } |
| 769 | |
| 770 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 771 | OMAP3430_AUTO_WDT2_MASK | |
| 772 | OMAP3430_AUTO_WDT1_MASK | |
| 773 | OMAP3430_AUTO_GPIO1_MASK | |
| 774 | OMAP3430_AUTO_32KSYNC_MASK | |
| 775 | OMAP3430_AUTO_GPT12_MASK | |
| 776 | OMAP3430_AUTO_GPT1_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 777 | WKUP_MOD, CM_AUTOIDLE); |
| 778 | |
| 779 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 780 | OMAP3430_AUTO_DSS_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 781 | OMAP3430_DSS_MOD, |
| 782 | CM_AUTOIDLE); |
| 783 | |
| 784 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 785 | OMAP3430_AUTO_CAM_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 786 | OMAP3430_CAM_MOD, |
| 787 | CM_AUTOIDLE); |
| 788 | |
| 789 | cm_write_mod_reg( |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 790 | omap3630_auto_uart4_mask | |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 791 | OMAP3430_AUTO_GPIO6_MASK | |
| 792 | OMAP3430_AUTO_GPIO5_MASK | |
| 793 | OMAP3430_AUTO_GPIO4_MASK | |
| 794 | OMAP3430_AUTO_GPIO3_MASK | |
| 795 | OMAP3430_AUTO_GPIO2_MASK | |
| 796 | OMAP3430_AUTO_WDT3_MASK | |
| 797 | OMAP3430_AUTO_UART3_MASK | |
| 798 | OMAP3430_AUTO_GPT9_MASK | |
| 799 | OMAP3430_AUTO_GPT8_MASK | |
| 800 | OMAP3430_AUTO_GPT7_MASK | |
| 801 | OMAP3430_AUTO_GPT6_MASK | |
| 802 | OMAP3430_AUTO_GPT5_MASK | |
| 803 | OMAP3430_AUTO_GPT4_MASK | |
| 804 | OMAP3430_AUTO_GPT3_MASK | |
| 805 | OMAP3430_AUTO_GPT2_MASK | |
| 806 | OMAP3430_AUTO_MCBSP4_MASK | |
| 807 | OMAP3430_AUTO_MCBSP3_MASK | |
| 808 | OMAP3430_AUTO_MCBSP2_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 809 | OMAP3430_PER_MOD, |
| 810 | CM_AUTOIDLE); |
| 811 | |
| 812 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 813 | cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 814 | OMAP3430ES2_AUTO_USBHOST_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 815 | OMAP3430ES2_USBHOST_MOD, |
| 816 | CM_AUTOIDLE); |
| 817 | } |
| 818 | |
Paul Walmsley | 2fd0f75 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 819 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
Tero Kristo | b296c81 | 2009-10-23 19:03:49 +0300 | [diff] [blame] | 820 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 821 | /* |
| 822 | * Set all plls to autoidle. This is needed until autoidle is |
| 823 | * enabled by clockfw |
| 824 | */ |
| 825 | cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, |
| 826 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); |
| 827 | cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, |
| 828 | MPU_MOD, |
| 829 | CM_AUTOIDLE2); |
| 830 | cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | |
| 831 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), |
| 832 | PLL_MOD, |
| 833 | CM_AUTOIDLE); |
| 834 | cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, |
| 835 | PLL_MOD, |
| 836 | CM_AUTOIDLE2); |
| 837 | |
| 838 | /* |
| 839 | * Enable control of expternal oscillator through |
| 840 | * sys_clkreq. In the long run clock framework should |
| 841 | * take care of this. |
| 842 | */ |
| 843 | prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
| 844 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
| 845 | OMAP3430_GR_MOD, |
| 846 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); |
| 847 | |
| 848 | /* setup wakup source */ |
Paul Walmsley | 2fd0f75 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 849 | prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
| 850 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 851 | WKUP_MOD, PM_WKEN); |
| 852 | /* No need to write EN_IO, that is always enabled */ |
Paul Walmsley | 275f675 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 853 | prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
| 854 | OMAP3430_GRPSEL_GPT1_MASK | |
| 855 | OMAP3430_GRPSEL_GPT12_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 856 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
| 857 | /* For some reason IO doesn't generate wakeup event even if |
| 858 | * it is selected to mpu wakeup goup */ |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 859 | prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 860 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 861 | |
Subramani Venkatesh | b92c572 | 2009-12-22 15:07:50 +0530 | [diff] [blame] | 862 | /* Enable PM_WKEN to support DSS LPR */ |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 863 | prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
Subramani Venkatesh | b92c572 | 2009-12-22 15:07:50 +0530 | [diff] [blame] | 864 | OMAP3430_DSS_MOD, PM_WKEN); |
| 865 | |
Kevin Hilman | b427f92 | 2009-10-22 14:48:13 -0700 | [diff] [blame] | 866 | /* Enable wakeups in PER */ |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 867 | prm_write_mod_reg(omap3630_en_uart4_mask | |
| 868 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
Paul Walmsley | 2fd0f75 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 869 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
| 870 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | |
| 871 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | |
| 872 | OMAP3430_EN_MCBSP4_MASK, |
Kevin Hilman | b427f92 | 2009-10-22 14:48:13 -0700 | [diff] [blame] | 873 | OMAP3430_PER_MOD, PM_WKEN); |
Kevin Hilman | eb350f7 | 2009-09-10 15:53:08 +0000 | [diff] [blame] | 874 | /* and allow them to wake up MPU */ |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 875 | prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
| 876 | OMAP3430_GRPSEL_GPIO2_MASK | |
Paul Walmsley | 275f675 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 877 | OMAP3430_GRPSEL_GPIO3_MASK | |
| 878 | OMAP3430_GRPSEL_GPIO4_MASK | |
| 879 | OMAP3430_GRPSEL_GPIO5_MASK | |
| 880 | OMAP3430_GRPSEL_GPIO6_MASK | |
| 881 | OMAP3430_GRPSEL_UART3_MASK | |
| 882 | OMAP3430_GRPSEL_MCBSP2_MASK | |
| 883 | OMAP3430_GRPSEL_MCBSP3_MASK | |
| 884 | OMAP3430_GRPSEL_MCBSP4_MASK, |
Kevin Hilman | eb350f7 | 2009-09-10 15:53:08 +0000 | [diff] [blame] | 885 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
| 886 | |
Kevin Hilman | d3fd329 | 2009-05-05 16:34:25 -0700 | [diff] [blame] | 887 | /* Don't attach IVA interrupts */ |
| 888 | prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
| 889 | prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); |
| 890 | prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); |
| 891 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); |
| 892 | |
Kevin Hilman | b1340d1 | 2009-04-27 16:14:54 -0700 | [diff] [blame] | 893 | /* Clear any pending 'reset' flags */ |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 894 | prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
| 895 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); |
| 896 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); |
| 897 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); |
| 898 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); |
| 899 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); |
| 900 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); |
Kevin Hilman | b1340d1 | 2009-04-27 16:14:54 -0700 | [diff] [blame] | 901 | |
Kevin Hilman | 014c46d | 2009-04-27 07:50:23 -0700 | [diff] [blame] | 902 | /* Clear any pending PRCM interrupts */ |
| 903 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 904 | |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 905 | omap3_iva_idle(); |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 906 | omap3_d2d_idle(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 907 | } |
| 908 | |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 909 | void omap3_pm_off_mode_enable(int enable) |
| 910 | { |
| 911 | struct power_state *pwrst; |
| 912 | u32 state; |
| 913 | |
| 914 | if (enable) |
| 915 | state = PWRDM_POWER_OFF; |
| 916 | else |
| 917 | state = PWRDM_POWER_RET; |
| 918 | |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 919 | #ifdef CONFIG_CPU_IDLE |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 920 | /* |
| 921 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot |
| 922 | * enable OFF mode in a stable form for previous revisions, restrict |
| 923 | * instead to RET |
| 924 | */ |
| 925 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) |
| 926 | omap3_cpuidle_update_states(state, PWRDM_POWER_RET); |
| 927 | else |
| 928 | omap3_cpuidle_update_states(state, state); |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 929 | #endif |
| 930 | |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 931 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 932 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
| 933 | pwrst->pwrdm == core_pwrdm && |
| 934 | state == PWRDM_POWER_OFF) { |
| 935 | pwrst->next_state = PWRDM_POWER_RET; |
| 936 | WARN_ONCE(1, |
| 937 | "%s: Core OFF disabled due to errata i583\n", |
| 938 | __func__); |
| 939 | } else { |
| 940 | pwrst->next_state = state; |
| 941 | } |
| 942 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 943 | } |
| 944 | } |
| 945 | |
Tero Kristo | 68d4778 | 2008-11-26 12:26:24 +0200 | [diff] [blame] | 946 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
| 947 | { |
| 948 | struct power_state *pwrst; |
| 949 | |
| 950 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 951 | if (pwrst->pwrdm == pwrdm) |
| 952 | return pwrst->next_state; |
| 953 | } |
| 954 | return -EINVAL; |
| 955 | } |
| 956 | |
| 957 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) |
| 958 | { |
| 959 | struct power_state *pwrst; |
| 960 | |
| 961 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 962 | if (pwrst->pwrdm == pwrdm) { |
| 963 | pwrst->next_state = state; |
| 964 | return 0; |
| 965 | } |
| 966 | } |
| 967 | return -EINVAL; |
| 968 | } |
| 969 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 970 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 971 | { |
| 972 | struct power_state *pwrst; |
| 973 | |
| 974 | if (!pwrdm->pwrsts) |
| 975 | return 0; |
| 976 | |
Ming Lei | d3d381c | 2009-08-22 21:20:26 +0800 | [diff] [blame] | 977 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 978 | if (!pwrst) |
| 979 | return -ENOMEM; |
| 980 | pwrst->pwrdm = pwrdm; |
| 981 | pwrst->next_state = PWRDM_POWER_RET; |
| 982 | list_add(&pwrst->node, &pwrst_list); |
| 983 | |
| 984 | if (pwrdm_has_hdwr_sar(pwrdm)) |
| 985 | pwrdm_enable_hdwr_sar(pwrdm); |
| 986 | |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 987 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 988 | } |
| 989 | |
| 990 | /* |
| 991 | * Enable hw supervised mode for all clockdomains if it's |
| 992 | * supported. Initiate sleep transition for other clockdomains, if |
| 993 | * they are not used |
| 994 | */ |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 995 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 996 | { |
| 997 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) |
| 998 | omap2_clkdm_allow_idle(clkdm); |
| 999 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
| 1000 | atomic_read(&clkdm->usecount) == 0) |
| 1001 | omap2_clkdm_sleep(clkdm); |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 1005 | void omap_push_sram_idle(void) |
| 1006 | { |
| 1007 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, |
| 1008 | omap34xx_cpu_suspend_sz); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 1009 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
| 1010 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, |
| 1011 | save_secure_ram_context_sz); |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 1012 | } |
| 1013 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 1014 | static void __init pm_errata_configure(void) |
| 1015 | { |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 1016 | if (cpu_is_omap3630()) { |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 1017 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 1018 | /* Enable the l2 cache toggling in sleep logic */ |
| 1019 | enable_omap3630_toggle_l2_on_restore(); |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 1020 | if (omap_rev() < OMAP3630_REV_ES1_2) |
| 1021 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 1022 | } |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 1023 | } |
| 1024 | |
Kevin Hilman | 7cc515f | 2009-06-10 09:02:25 -0700 | [diff] [blame] | 1025 | static int __init omap3_pm_init(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1026 | { |
| 1027 | struct power_state *pwrst, *tmp; |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 1028 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1029 | int ret; |
| 1030 | |
| 1031 | if (!cpu_is_omap34xx()) |
| 1032 | return -ENODEV; |
| 1033 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 1034 | pm_errata_configure(); |
| 1035 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1036 | printk(KERN_ERR "Power Management for TI OMAP3.\n"); |
| 1037 | |
| 1038 | /* XXX prcm_setup_regs needs to be before enabling hw |
| 1039 | * supervised mode for powerdomains */ |
| 1040 | prcm_setup_regs(); |
| 1041 | |
| 1042 | ret = request_irq(INT_34XX_PRCM_MPU_IRQ, |
| 1043 | (irq_handler_t)prcm_interrupt_handler, |
| 1044 | IRQF_DISABLED, "prcm", NULL); |
| 1045 | if (ret) { |
| 1046 | printk(KERN_ERR "request_irq failed to register for 0x%x\n", |
| 1047 | INT_34XX_PRCM_MPU_IRQ); |
| 1048 | goto err1; |
| 1049 | } |
| 1050 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 1051 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1052 | if (ret) { |
| 1053 | printk(KERN_ERR "Failed to setup powerdomains\n"); |
| 1054 | goto err2; |
| 1055 | } |
| 1056 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 1057 | (void) clkdm_for_each(clkdms_setup, NULL); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1058 | |
| 1059 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
| 1060 | if (mpu_pwrdm == NULL) { |
| 1061 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); |
| 1062 | goto err2; |
| 1063 | } |
| 1064 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 1065 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
| 1066 | per_pwrdm = pwrdm_lookup("per_pwrdm"); |
| 1067 | core_pwrdm = pwrdm_lookup("core_pwrdm"); |
Tero Kristo | c16c3f6 | 2008-12-11 16:46:57 +0200 | [diff] [blame] | 1068 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 1069 | |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 1070 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
| 1071 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); |
| 1072 | per_clkdm = clkdm_lookup("per_clkdm"); |
| 1073 | core_clkdm = clkdm_lookup("core_clkdm"); |
| 1074 | |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 1075 | omap_push_sram_idle(); |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 1076 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1077 | suspend_set_ops(&omap_pm_ops); |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 1078 | #endif /* CONFIG_SUSPEND */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1079 | |
| 1080 | pm_idle = omap3_pm_idle; |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 1081 | omap3_idle_init(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1082 | |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 1083 | /* |
| 1084 | * RTA is disabled during initialization as per erratum i608 |
| 1085 | * it is safer to disable RTA by the bootloader, but we would like |
| 1086 | * to be doubly sure here and prevent any mishaps. |
| 1087 | */ |
| 1088 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) |
| 1089 | omap3630_ctrl_disable_rta(); |
| 1090 | |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 1091 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 1092 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
| 1093 | omap3_secure_ram_storage = |
| 1094 | kmalloc(0x803F, GFP_KERNEL); |
| 1095 | if (!omap3_secure_ram_storage) |
| 1096 | printk(KERN_ERR "Memory allocation failed when" |
| 1097 | "allocating for secure sram context\n"); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 1098 | |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 1099 | local_irq_disable(); |
| 1100 | local_fiq_disable(); |
| 1101 | |
| 1102 | omap_dma_global_context_save(); |
| 1103 | omap3_save_secure_ram_context(PWRDM_POWER_ON); |
| 1104 | omap_dma_global_context_restore(); |
| 1105 | |
| 1106 | local_irq_enable(); |
| 1107 | local_fiq_enable(); |
| 1108 | } |
| 1109 | |
| 1110 | omap3_save_scratchpad_contents(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1111 | err1: |
| 1112 | return ret; |
| 1113 | err2: |
| 1114 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); |
| 1115 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
| 1116 | list_del(&pwrst->node); |
| 1117 | kfree(pwrst); |
| 1118 | } |
| 1119 | return ret; |
| 1120 | } |
| 1121 | |
| 1122 | late_initcall(omap3_pm_init); |